Semiconductor device and method of manufacturing the same

- Canon

In a semiconductor device, an active layer is formed on an insulating substrate. The active layer is a polycrystalline semiconductor film having large diameter crystal grain. A carrier mobility of said polycrystalline semiconductor film is not lower than 10 cm.sup.2 /V.multidot.sec.

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Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device in which an active layer is formed on an insulating substrate and to a method of manufacturing this device.

2. Related Background Art

Recently, in association with very large and large scale integration of semiconductor elements, complete electrical isolation among elements and the reduction in stray capacitance are important subjects of consideration. In addition, due to development of a long or large-area image device, making of a long or large-area active element and the like are the significant subjects of consideration. To cope with these subjects, various kinds of researches have been made with respect to the technology to form a semiconductor thin film crystal on various insulating substrates (for example, SOI (Silicon on Insulator) technology) and semiconductor devices using this technology.

Recently, a semiconductor device has been realized in which an active layer is formed on an amorphous insulating substrate such as SiO.sub.2 or the like is particularly required for the purpose of application to a three-dimensional integrated circuit having a multilayer structure, plane liquid crystal display device, long line sensor, or the like. As a material to be used for such an active layer, for example, amorphous silicon, polycrystalline silicon, and silicon which was monocrystallized due to a melting recrystallization (hereinafter, this silicon is referred to as a "pseudo monocrystalline silicon") have been studied. In general, three states of amorphous, polycrystal, and pseudo monocrystal are determined by the forming temperature of the material. In the case of forming silicon on SiO.sub.2, it becomes amorphous at temperatures below a crystallization temperature T.sub.c (about 500.degree. C.), pseudo monocrystal at temperatures above a melting point T.sub.m (1420.degree. C.), and polycrystal at temperatures within a temperature range from about the crystallization temperature T.sub.c to the melting point T.sub.m.

After a semiconductor layer is first deposited on an insulating substrate, it is heated to temperatures above the melting point T.sub.m and then recrystallized due to a solidification cooling, thereby forming a pseudo monocrystalline semiconductor layer. Thus, the polycrystalline or monocrystalline semiconductor layer of large diameter particles is formed and active elements such as transistors and the like can be formed on this semiconductor layer. In the case where transistors were formed, its carrier mobility is hundreds of cm.sup.2 /V.multidot.sec. This mobility is nearly equal to that of the transistors formed on a monocrystalline silicon.

However, according to such a method, in the case of recrystallizing the semiconductor layer deposited, the temperature needs to be set to a high temperature above the melting point T.sub.m (about 1420.degree. C. in the case of silicon), so that there are the problems such that the semiconductor layer is softened or in the worst case, the substrate itself is fused.

On the other hand, in the case of manufacturing an integrated circuit having a multilayer structure such as a three-dimensional integrated circuit or the like, according to a method whereby the heat treatment at such a high temperature is necessary, there is also the problem such that the impurity profiles of the elements which have already been formed in the lower layer portion are changed due to the high temperature, so that it is difficult to realize desired characteristics.

On the contrary, a low pressure chemical vapor phase (LPCVD) method, an MBE method, and the like have been known as methods of forming a semiconductor layer at relatively low temperatures below the melting point T.sub.m. In this case, an amorphous or polycrstalline semiconductor layer is formed as mentioned above.

In the case of the amorphous semiconductor layer, however, since the long distance order of the crystal structure is lacking, a carrier mobility of transistors formed on this layer is below 1 cm.sup.2 /V.multidot.sec. Thus, high speed operation characteristics cannot be realized.

On the other hand, in the case of the polycrystalline semiconductor layer, because of the diffusion of carriers mainly due to the crystal grain boundary, a carrier mobility of transistors formed on this layer is less than 10 cm.sup.2 /V.multidot.sec. Therefore, this semiconductor layer is still insufficient when it is used as an active element for various kinds of devices.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor device in which high speed operation characteristics are improved compared to those of the conventional devices.

Another object of the invention is to provide a semiconductor device which can be manufactured at a lower temperature and which has a higher carrier mobility as compared with those of the conventional device.

Still another object of the invention is to provide a semiconductor device which is constituted by a polycrystalline semiconductor film having large diameter particles and can operate at a high speed and in which an active layer whose carrier mobility is about 10 cm.sup.2 /V.multidot.sec is formed on an insulating substrate and to provide a method of manufacturing such a semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatical view showing a state of grain growth of a polycrystalline thin film in the solid phase;

FIG. 2 is a graph showing the relation between a film thickness h of the polycrystalline thin film and a diameter d.sub.n of particle grown due to a primary grain growth;

FIGS. 3A to 3D are diagrams of manufacturing processes showing an embodiment of a method of manufacturing a semiconductor device according to the present invention; and

FIG. 4 is a graph showing the relation between the carrier mobility and the film thickness of the polycrystalline film which were obtained using another embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A growing method of enlarging polycrystalline grain will be first described.

FIG. 1 is a diagrammatical view showing a state of grain growth of a polycrystalline thin film in the solid phase. FIG. 2 is a graph showing the relation between a film thickness h of polycrystalline thin film and a diameter d.sub.n of particle grown due to a primary grain growth.

First, a temperature of an amorphous insulating substrate 1 is set to a value between the crystallization temperature T.sub.c and melting point T.sub.m of the polycrystalline thin film which is to be deposited. A thin film 2 having polycrystalline grain is deposited on the substrate 1 using an LPCVD method, a vacuum evaporation deposition method, or the like so as to have the thickness of only h. Subsequently, the polycrystalline grain is grown using heat treatment. This grain growth includes two kinds of phenomena called a primary grain growth and a secondary grain growth.

The primary grain growth is the process in which the diameter of crystal grain including a large amount of defects uniformly increases in the orientation which is unrelated to the surface of the substrate 1. The driving force in this case is generated because the defective energy and grain boundary energy before the growth decrease in association with the growth. However, in the primary grain growth, an enlargement of the diameter of crystal grain is limited due to the thickness h of polycrystalline thin film 2 as shown in an example of FIG. 2. Therefore, the diameter d.sub.n of crystal grain 3 after the primary grain growth can be substantially determined by setting the film thickness h.

The secondary grain growth is the phenomenon which appears under the conditions in the case where the film thickness h is so thin to be below 1000 .ANG. or where a large amount of impurities are added into the polycrystalline thin film 2, or the like. First, crystal grain 3 is grown due to the primary grain growth and thereafter it is subjected to a heat treatment at temperatures below the melting point T.sub.m. Thus, crystal grain 4 having a diameter d.sub.s which is hundreds of times as large as the diameter d.sub.n of crystal grain is grown and at the same time, its surface orientation becomes constant. This is because since the film thickness becomes extremely thin, a ratio of the surface area per volume of the crystal grain increases, so that the crystal grain having a surface orientation such that the surface energy is minimized grows so as to absorb the other crystal grain.

The polycrystalline film having large diameter crystal grain can be formed using such a grain growth due to low-temperature processes. An embodiment of the present invention will now be described in detail hereinbelow with reference to the drawings.

FIGS. 3A to 3D are diagrams of manufacturing processes showing an embodiment of a method of manufacturing a semiconductor device according to the present invention. In this embodiment, the primary grain growth is used as a method of forming the polycrystalline film of large diameter particle.

First, the polycrystalline film 2 of silicon or the like is deposited onto the amorphous insulating substrate 1 of SiO.sub.2 or the like due to an LPCVD method or vacuum evaporation deposition method so as to have a thickness of about 10 .mu.m. In this case, a temperature of the substrate 1 is held at a value above the crystallization temperature T.sub.c (400.degree. to 500.degree. C.), for example, within a range of 600.degree. to 800.degree. C. The diameter of crystal grain of the polycrystalline film 2 which is formed lies within a range of hundreds of .ANG. to thousands of .ANG. (FIG. 3A).

Next, the heat treatment is executed in the ambient atmosphere of N.sub.2 gas or the like at temperatures below the melting point T.sub.m (1420.degree. C.), e.g., within a range of 1100 to 1300.degree. C. Due to this, the primary grain growth occurs and the crystal grain 3 having a large diameter which is nearly the same as the thickness (10 .mu.m) of polycrystalline film 2 is grown. As already mentioned above, a diameter of crystal grain 3 can be arbitrarily decided due to a thickness of polycrystalline film 2 (FIG. 3B).

Subsequently, the polycrystalline film 2 having large diameter crystal grain is thinned due to wet etching, reactive ion etching, or the like so as to have a thickness suitable to form a transistor of a size below 0.5 .mu.m (FIG. 3C).

Then, a MOS transistor is formed using the thin polycrystalline film 2 as an active layer due to ordinary manufacturing processes. First, p type impurities are doped into the polycrystalline film 2 and the film 2 is etched to obtain island shapes. Then, a gate electrode 12 of polycrystalline silicon is formed through a gate oxide film 11 on a p region 10 in which n channel regions are formed. Next, an n.sup.+ source region 13 and an n.sup.+ drain region 14 are formed in a self-alignment manner using the gate electrode 12 as a mask. The whole surface is covered by an oxide film 15 and opening portions are formed in the electrode portions and metal is evaporation deposited into these opening portions, thereby forming a source electrode 16 and a drain electrode 17 (FIG. 3D).

According to the MOS transistor produced as described above, the good operation characteristics such that the electron mobility lies within a range of tens to hundreds of cm.sup.2 /V.multidot.sec were obtained.

A practical example will now be shown hereinbelow.

The SiO.sub.2 film 1 of the thickness of 0.1 .mu.m is grown on an Si wafer due to thermal oxidation. The polycrystalline silicon film 2 having the thickness of 10 .mu.m is formed on the film 1 due to a CVD method using SiH.sub.4 as a material gas. In this case, the temperature of the substrate was set to 700.degree. C. (refer to FIG. 3A).

Next, the heat treatment is performed at 1100.degree. C. for five to ten hours in the ambient atmosphere of N.sub.2 and the polycrystalline silicon film 2 is grown due to the primary grain growth so as to have a particle diameter which is nearly the same as the film thickness (10 .mu.m) (refer to FIG. 3B).

Next, an oxide film having the thickness of 9.5 .mu.m is formed due to high pressure oxidation. By removing this oxide film by use of hydrogen fluoride HF, the polycrystalline silicon film 2 having a large particle diameter is made thinner to have the thickness of 0.5 .mu.m (refer to FIG. 3C).

The thin polycrystalline silicon film 2 is formed into islands due to a reactive ion etching using (SF.sub.6 +CCl.sub.2 S.sub.2) gases, thereby electrically isolating the portions from the other portions to form a transistor. Subsequently, gate oxide film (SiO.sub.2) 11 having the thickness of 0.05 .mu.m is formed due to a thermal oxidation. Thereafter, the polycrystalline silicon is deposited at 600.degree. C. due to an LPCVD method so as to have the thickness of 0.3 .mu.m and patterned to form the gate electrode 12. Next, the source and drain regions 13 and 14 and the source and drain electrodes 16 and 17 are formed due to ordinary diffusion processes and lithography processes. Finally, an SiN film is deposited as a passivation film due to a plasma CVD method, thereby forming the MOS transistor. According to the MOS transistor manufactured in this way, good operation characteristics, such that the electron mobility is about 10 cm.sup.2 /V.multidot.sec were derived.

If the polycrystalline film 2 which is deposited onto the amorphous insulating substrate 1 is formed so as to have a very thin thickness below 1000 .ANG., the polycrystalline film having further large particle diameters can be formed by use of the secondary grain growth. A field effect transistor using such a polycrystalline film as an active layer may be manufactured as another embodiment of the invention due to the processes similar to the above.

FIG. 4 is a graph showing the relation between the electron mobility and the thickness of polycrystalline film which were obtained using another embodiment of the invention.

As shown in this graph, it will be appreciated that with a decrease in film thickness h, the electron mobility increases. This is because, the grain boundary interval of the polycrystalline film increases as the particle diameter increases, so that the diffusion of the carriers running in the polycrystalline film at the grain boundary is reduced.

As described in detail above, the semiconductor device according to the invention can be sufficiently used as an active element having the high speed operation characteristics since the carrier mobility is above 10 cm.sup.2 /V.multidot.sec in spite of the fact that its active layer is the polycrystalline semiconductor.

On the other hand, the method of manufacturing the semiconductor device according to the invention merely needs requires the heat treatment at temperatures below the melting point. Therefore, the semiconductor device can be manufactured using processes at low temperatures. Consequently, this method is suitable to manufacture an integrated circuit having a multilayer structure such as a three-dimensional integrated circuit or the like, a large-area or long active element array, and the like.

Claims

1. A method of manufacturing a semiconductor device having a semiconductor film carrier mobility not lower than 10 cm.sup.2 /V.multidot.sec, comprising the steps of:

(1) heating a non-crystalline insulating substrate to maintain the substrate at a temperature above a crystallization temperature of the semiconductor film to be formed;
(2) depositing a polycrystalline semiconductor film of sufficient thickness on the substrate while it is maintained at the temperature (T.sub.1);
(3) subjecting the semiconductor film to heat treatment at a temperature (T.sub.2) not higher than the melting point of the semiconductor film, thereby enlarging its crystalline grain size by a predetermined amount; and
(4) removing a surface portion of the semiconductor film whose crystalline grain size is enlarged to make the semiconductor film into a thin film with a predetermined thickness.

Referenced Cited

U.S. Patent Documents

4214918 July 29, 1980 Gat et al.
4272880 June 16, 1981 Pashley
4514895 May 7, 1985 Nishimura
4557943 December 10, 1985 Rosler et al.
4581814 April 15, 1986 Celler et al.
4597160 July 1, 1986 Ipri
4625224 November 25, 1986 Nakagawa et al.
4626883 December 2, 1986 Kash et al.
4693759 September 15, 1987 Noguchi et al.

Foreign Patent Documents

62-008572 January 1987 JPX

Other references

  • Karmins et al, IEEE Trans. on Elec. Dev., vol. Ed-27, No. 1, Jan. 1980, "A Monolithic . . . Polysilicon", pp. 290-293. Nishimura et al, Appl. Phys. Lett., 1 Jan. 83, "Metal-Oxide-Semiconductor . . . Islands", pp. 102-104. Kamins, T., A Monolithic Integrated Circuit Fabricated in Laser-Annealed Polysilicon, IEEE Electron Devices, vol. Ed 27, No. 1, Jan. 1980. Mohammadi, F., A High-Voltage MOSFET in Polycrystalline Silicon, IEEE Electron Devices, vol. Ed. 27, No. 1, Jan. 1980. Lu, N., The Effect of Film Thickness on the Electrical Properties of LPCVD Polysilicon Films, J. Electrochem. Soc. 131, p. 898, Apr. 1984. Wolf, S., Silicon Processing for the VLSI Era, Chapters 4 and 6, Lattice Press, 1986. Ghandhi, S., VLSI Fabrication Principles, Chapter 8, Wiley and Sons, 1983. Sze, S., VLSI Technology, Chapter 3, McGraw-Hill, 1983. Hatalis, M., High-Performance Thin-Film Transistors in Low-Temperature Crystallized LPCVD Amorphous Silicon Films, IEEE Electron Device Letters, vol. EDL-8, No. 8, Aug. 1987. Levinson, J., Conductivity Behavior in Polycrystalline Semiconductor Thin Film Transistors, J. Appl. Phys., vol. 53, No. 2, Feb. 1982.

Patent History

Patent number: 4868140
Type: Grant
Filed: Jun 27, 1988
Date of Patent: Sep 19, 1989
Assignee: Canon Kabushiki Kaisha (Tokyo)
Inventor: Takao Yonehara (Atsugi)
Primary Examiner: Brian E. Hearn
Assistant Examiner: B. Everhart
Law Firm: Fitzpatrick, Cella, Harper & Scinto
Application Number: 7/212,088

Classifications

Current U.S. Class: 437/109; 437/84; 437/923; 437/967; 437/233; 437/247; 357/4; Polycrystalline (148/DIG122)
International Classification: H01L 2100; H01L 2102; H01L 2120; H01L 2136;