Abstract: The present invention provides a method of making a semiconductor substrate having an SOI structure by temporarily bonding together two wafers having different thermal expansion coefficients to allow thinning of at least one of the wafers by chemical and/or mechanical treatment(s) to reduce the risk of strain, separation, cracks to the wafers followed by one or more heat treating steps to fully bond the wafers together. The method can produce semiconductor substrate having an SOI structure which can provide a silicon layer thin enough to allow various integrated circuits, or TFL-LCD or the like to be formed.

Abstract: Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers. The silicide bonding takes place in the presense of a liquid oxidizer such as aqueous solution of HNO.sub.3 and H.sub.2 O.sub.2.

Abstract: A method of manufacturing a planar inductance element, including the steps of forming a thermal oxide film, a magnetic film, a first insulating interlayer, a planar coil, and a second insulating interlayer on a first semiconductor substrate, forming an insulating film and a magnetic film on a second semiconductor substrate, and adhering the first and the second semiconductor substrates such that the coil side of the first semiconductor substrate faces the magnetic film side of the second semiconductor substrate. According to this method, a stress generated by stacking thin films can be reduced compared with that of a conventional inductance element. Therefore, a high-frequency loss can be reduced, and a quality coefficient Q can be increased.

Abstract: In a method of bonding semiconductor substrates, a plurality of the semiconductor substrates are first prepared. Surfaces of the semiconductor substrates are mirror-polished. The mirror-polished surface of at least one of the semiconductor substrates is then provided with a hydrophilic property in such a way that an oxide layer is formed on the mirror-polished surface by exposing the mirror-polished surface to an atmosphere of at least one of an oxygen ion and an oxygen radical. A water molecule is then adhered to the mirror-polished surface. The semiconductor substrates then contact with each other through the mirror-polished surface. The contacted semiconductor substrates are then heated. According to such a method of bonding, the semiconductor substrates are strongly bonded to each other with hardly an unbonded region even if the semiconductor substrates are heated at a low temperature.

Abstract: A lateral insulating gate type field effect transistor can be manufactured with ease reliably by using a semiconductor substrate having excellent crystal property. A projected portion (2) is formed on a first major surface side of a semiconductor substrate (1). A first gate portion (3) having a width (length) smaller than that of the projected portion (2) is formed on the projected portion (2). An insulating layer (4) is formed on the whole surface of the semiconductor substrate (1) so as to bury the first gate portion (3). The semiconductor substrate (1) is removed horizontally from its second major surface side, i.e., from the opposite side of the side of the projected portion (2) to a position (a) at which the insulating layer (4) is formed so as to bury the projected portion (2) is exposed. A second gate portion (5) is formed on such exposed surface.

Abstract: A method for fabricating a laminated substrate for a semiconductor device having a high voltage power device and a low voltage element formed in a region isolated from the power device with a P-N junction. The region for the low voltage element is formed on a buried layer of P type formed in the region of N type in which the power device is formed and surrounded by a isolating region of P type reaching the buried layer from the surface of the laminated substrate.

Abstract: A method for preparing a semiconductor member comprising steps of: making a silicon substrate porous; forming a non-porous silicon monocrystalline layer on the porous silicon substrate at a first temperature; bonding a surface of the non-porous silicon monocrystalline layer on to another substrate having an insulating material on the surface thereof; etching the porous silicon by removing the porous silicon of the bonded substrate by chemical etching; and forming a monocrystalline silicon layer on the non-porous silicon monocrystalline layer by epitaxial growth at a second temperature higher than the first temperature.

Abstract: According to the present invention, there is provided semiconductor wafer, comprises a plurality of non-porous monocrystal layers laminated with interposition of an insulating layer or insulating layers on a substrate.

Abstract: Process for the preparation of thin moncrystalline or polycrystalline semiconductor material films, characterized in that it comprises subjecting a semiconductor material wafer having a planar face to the three following stages: a first stage of implantation by bombardment (2) of the face (4) of the said wafer (1) by means of ions creating in the volume of said wafer a layer (3) of gaseous microbubbles defining in the volume of said wafer a lower region (6) constituting the mass of the substrate and an upper region (5) constituting the thin film, a second stage of intimately contacting the planar face (4) of said wafer with a stiffener (7) constituted by at least one rigid material layer, a third stage of heat treating the assembly of said wafer (1) and said stiffener (7) at a temperature above that at which the ion bombardment (2) was carried out and sufficient to create by a crystalline rearrangement effect in said wafer (1) and a pressure effect in the said microbubbles, a separation between the thin film

Abstract: A semiconductor laser screen in a cathode-ray tube with a sealed casing. The laser screen has a screen structure which is formed by a semiconductor member, a reflecting mirror and a partly transparent mirror on opposite sides of the semiconductor member. The screen structure is connected to a transparent support by means of a connecting layer which is formed by glass having a softening point of at least 675K. The materials of the semiconductor member, the transparent support, the connecting layer and the casing are made of materials with similarly low coefficients of expansion to prevent damage to the screen as it cools down from the manufacturing process.

Abstract: A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic thermal expansion coefficient. The second wafer comprises a second substrate having an insulation layer formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer.

Abstract: A process for planarizing a bonded wafer. The wafer has a layer of exposed oxide thereon which acts as a reference for the grinding and polishing of the wafer. The resulting ground and polished wafer has a thinned, substantially planar, working layer for subsequent fabrication of transistors, etc.

Abstract: Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.

Abstract: A method is provided for manufacturing a bipolar transistor, comprising the teps of: 1) abutting a polished surface of a substantially single crystal silicon wafer with a polished surface of an insulating substrate; 2) heating the abutting silicon wafer and insulating substrate at about 200.degree. C. for about 30 minutes to form a bonded wafer having a silicon layer; 3) forming a silicon island from the silicon layer; 4) ion implanting a first dopant species having a first conductivity into the silicon island to form a base region in the silicon island; 5) ion implanting a second dopant species having a second conductivity opposite the first conductivity into the silicon island to form an emitter region and a collector region in the silicon island; 6) ion implanting a third dopant species having the first conductivity into the base region of the silicon island; 7) heating the bonded wafer at a temperature of about 800.degree. C.

Abstract: A method of forming a radiation hardened SOI structure is disclosed. The buried oxide layer of an SOI structure is hardened prior to the bonding of a device wafer which forms the silicon portion of the silicon-on-insulator. The radiation hardening is done by implantation of recombination center-generating impurities. All the radiation hardening is done prior to the bonding of the device silicon layer and allows for radiation hardening of the buried oxide layer of an SOI structure without any damage to the silicon device layer.

Abstract: A method of manufacturing a semiconductor device includes the following steps. A wide groove portion is formed in a predetermined portion of one major surface of a first semiconductor substrate. A first insulating film is formed on the bottom surface of the groove portion. The major surface of the first semiconductor substrate except for the first insulating film is polished to form a mirror-polished surface on the same level as the surface of the first insulating film. One major surface of a second semiconductor substrate is bonded to the mirror-polished surface of the first semiconductor substrate and the surface of the first insulating film by direct bonding, and the resultant structure is heat-treated, thereby forming a composite semiconductor substrate. A groove having a ring-like planar shape is formed to extend from the other major surface of the first semiconductor substrate constituting the composite semiconductor substrate to the first insulating film.

Abstract: A silicon wafer and a III-V semiconductor wafer are bonded together through a bonding interlayer which is deposited on the III-V semiconductor wafer. By forming the bonding interlayer on the III-V semiconductor wafer, rather than the silicon wafer, the bonding process is facilitated, creating a sufficiently strong bond to carry out further processing. The III-V semiconductor wafer is thinned to relieve stress after the bonding procedure. The bonded wafers may be subjected to a second bonding procedure to increase the bond strength. The bonded wafers can then be subjected to high temperature processing used in semiconductor device fabrication.

Abstract: A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer.

Abstract: A bonded wafer comprising a filmy bond wafer, a base wafer, and an intermediate silicon dioxide layer, wherein the periphery of the bond wafer is etched; this bonded wafer is made by: subjecting the bond wafer to an oxidation treatment to form an oxide film over it; joining the two wafers in a manner such that the oxide film-covered face of the bond wafer is put on the base wafer to thereby sandwich the oxide film between the wafers; heating the combined wafers to thereby create a bonding strength between the two wafers; grinding the exposed face of the bond; etching the periphery of the bond wafer to remove the portion which is not in contact with the base wafer; and polishing the exposed face of the bond wafer until it becomes a thin film.

Abstract: A dielectrically isolated substrate is comprised of a single-crystal silicon substrate or bond substrate and a single-crystal silicon substrate or base substrate bonded together into a composite structure. The bond substrate has a (110) plane as a main crystal plane and is provided with vertically walled moats and substantially squared islands positioned adjacent to the moats. The moats and islands result from anisotropic etching using a specific mask pattern. Also disclosed is a process for producing the composite structure.

Abstract: A method is provided for forming a multi-cell photovoltaic circuit on an insulating substrate, comprising the steps of: forming a photovoltaic junction between p-type and n-type layers in a silicon wafer; bonding the silicon wafer to an insulating substrate after forming the photovoltaic junction; patterning the silicon wafer to produce isolated photovoltaic cells; and electrically interconnecting the photovoltaic cells.

Abstract: A method of manufacturing a semiconductor device using simplified processing and eliminating and/or minimizing the extrinsic parasitic elements of the device. The method is particularly suited for manufacturing heterojunction bipolar transistors where the extrinsic parasitic base resistance and the extrinsic parasitic base-collector and base-emitter capacitances can be virtually eliminated and the base contact resistance can be greatly reduced. The method includes formming symmetric emitter and collector portions using front and backside processing of the wafer, respectively. The symmetric emitter and collector virtually eliminates the extrinsic collector and emitter regions of the device thereby virtually eliminating the extrinsic base-collector and base-emitter capacitance. The extrinsic base contact region may also be increased to minimize the base contact resistance without increasing parasitic capacitive elements of the device.

Abstract: A method of forming a thin semiconductor layer having ultra-high thickness uniformity and upon which semiconductor structures can subsequently be formed is disclosed. The method comprises providing a primary substrate having a prescribed total thickness variation (TTV). A stack is formed upon the primary substrate for compressing thickness variation to be transferred into the thin semiconductor layer. An epitaxial silicon layer of a desired SOI thickness is formed upon the stack. The epitaxial silicon layer is then bonded to a mechanical substrate to form a bonded substrate pair, the mechanical substrate having a prescribed TTV and the bonded substrate pair having a combined TTV equal to the sum of the TTVs of the primary and mechanical substrates, respectively. The primary substrate is subsequently removed, wherein the combined TTV of the bonded substrate pair is transferred and compressed into the stack by a first compression amount.

Abstract: High mobility thin film transistors for fabricating integrated drivers for active matrix displays and a special method of fabrication for obtaining the thin film transistors having mobility sufficiently high enough as drivers operable in the several megahertz frequency range needed for driving high resolution active matrix displays.

Abstract: A method of manufacturing an SOI type substrate by forming a poly-Si layer on the surface of the one Si single crystal wafer (A), then forming a SiO.sub.2 film on the surface of the other Si single crystal wafer (B), bonding these wafers with each other, removing the end portion of the one Si single crystal wafer (A) by a polishing method leaving a part of this Si single crystal wafer as an element forming layer, providing a high concentration impurity region by selectively introducing impurity into the element forming layer and forming a high concentration impurity diffused region in the vicinity of interface with the poly-Si layer of the element forming layer by heat treatment; and a bipolar transistor formed on an SOI type substrate forming a high concentration impurity diffused region as a buried collector layer.

Abstract: A semiconductor wafer (40) is placed in a first pressure chamber (37) of a bonding apparatus (10 or 60). A major surface (46) of a submount (44) is placed on a submount support (30 or 62). The major surface (46) of the submount (44) seals the first pressure chamber (37). A pressure differential is generated between the first pressure chamber (37) and a second pressure chamber (47) The pressure differential bows a central portion of the submount (44) toward the semiconductor wafer (40). The central portion of the submount (44) contacts an adhesive coating over a central portion of the semiconductor wafer (40). The submount support (30 or 62) is displaced to decrease a curvature on the submount (44). The pressure differential is increased to an end-point to facilitate bond formation between the semiconductor wafer (40) and the submount (44).

Abstract: The invention provides a silicon-on-insulator semiconductor substrate structure and a method of fabricating the same. The structure includes a base silicon substrate, a mono-crystalline silicon film formed on the base silicon substrate in a predetermined region, a poly-crystalline silicon film formed on the base silicon substrate in opposite region to the predetermined region, an insulator film formed on the polycrystalline silicon film, and a mono-crystalline silicon layer overlaying both the insulator film and the mono-crystalline silicon film so that the mono-crystalline silicon layer is electrically connected to the base silicon substrate through the mono-crystalline silicon film. The mono-crystalline silicon film permits not the mono-crystalline silicon layer only but also the base silicon substrate to serve as active regions.

Abstract: The invention is directed to method for making a dielectrically isolated metal base transistors and permeable base transistors. The first step is the production of a silicon/metal silicide/silicon heterostructure. Thereafter the surface of the heterostructure is oxidized so as to provide a bonding surface. A second silicon substrate has its surface oxidized and is bonded to the heterostructure. The surface of the heterostructure is then etched back so as to expose individual transistors which are disposed on the oxidized surface of the second substrate. With suitable processing of the metal silicide layer it may act as the base region for a metal base or permeable base transistor.

Abstract: A method of bonding a first silicon wafer to a second silicon wafer comprises the steps of diffusing a high conductivity pattern into a surface of a first semiconductor wafer, etching a portion of the surface to raise at least a portion of the pattern, providing a second semiconductor wafer having an insulating layer of a silicon compound disposed thereon, contacting the surface of the pattern to the insulating layer, and bonding the first and second semiconductor wafers at an elevated temperature.

Abstract: There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon la

Abstract: A method of manufacturing a semiconductor body (1), whereby a carrier wafer (2) with an optically smooth main surface (3) is provided with a semiconducting top layer (4) in that the main surface (3) is brought into contact with an optically smooth main surface (5) of a monocrystalline semiconductor wafer (6), a permanent bond being formed, after which the semiconductor wafer (6) is made thin by means of a grinding process and a polishing process in that order. The semiconductor wafer (6) is made thin in the polishing process in that the exposed main surface (9) of the carrier wafer (2) is made wear-resistant, and in that then the carrier wafer (2) bonded to the semiconductor wafer (6) is arranged between two plane polishing discs (10) and (11) provided with a polishing liquid, upon which these polishing discs (10, 11) and the exposed main surfaces (8, 9) are moved relative to one another.

Abstract: A process for preparing a semiconductor device substrate comprises a step of making at least one surface of a first substrate composed of Si material porous, a step of oxidizing inside walls of pores in the resulting porous Si surface layer, a step of forming a monocrystalline Si layer on the porous Si surface layer, a step of bonding the monocrystalline Si layer to one surface of a second substrate through an insulating layer therebetween, a first etching step of removing the first substrate by selective etching except for the porous Si layer, and a second etching step of impregnating the porous Si layer exposed by the removal of the first substrate with hydrofluoric acid or a first liquid mixture of hydrofluoric acid and at least one of an alcohol and a hydrogen peroxide solution, or by buffered hydrofluoric acid or a second liquid mixture of bufffered hydrofluoric acid and at least one of an alcohol and an hydrogen peroxide solution, thereby selectively removing the porous Si layer.

Abstract: A conductivity modulation type MOSFET (IGBT) including an n-type high resistance layer, p-type base regions selectively formed in a first major surface of the high resistance layer, n-type source regions formed in the surface of each base region, a p.sup.+ well region formed in a central region of each of the base regions, a channel in the base region between one of the n-type source regions and the high resistance layer, a gate electrode formed above the channel, an emitter electrode formed in contact with the p.sup.+ well region and the n-type source region, a gate insulating film formed between the gate electrode and the channel, and a metal electrode formed in contact with a second major surface of the high resistance layer opposite the first major source, the electrode forming a Schottky barrier junction.

Abstract: A semiconductor-on-insulator structure incorporating a layer of diamond material and method for preparing such. The structure comprises a layer containing diamond material and having a first surface. A layer of silicon nitride is formed on the first surface and a layer of semiconductor material is positioned over the silicon nitride layer. In one embodiment of the method there is provided a removable deposition surface. A layer of crystalline diamond material is formed on the deposition surface. A first surface of the diamond material is separated from the deposition surface. The structure is useful for formation of integrated circuits thereon.

Abstract: A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.

Abstract: A first semiconductor substrate comprises an integrated circuit formed therein and an alignment mark formed thereon. The top surface of the first semiconductor substrate is covered with a first insulating layer and is planarized. The alignment mark is formed in a space between a plurality of groups of elements, such as a scribe line area. A second semiconductor substrate is provided with a groove corresponding to said space, or scribe line area, and a second insulating layer is formed on thereon and so as to bury the groove, and the exposed surface of the second insulating layer is planarized. The two planarized surfaces of the first and second semiconductor substrates are positioned in facing, contiguous relationship and are bonded to each other, while an infra-red microscope is used for alignment of the space and the groove. The back surface of the second semiconductor substrate is selectively etched until the second insulating layer, as filed in the groove, is exposed.

Abstract: A detector useful for detecting infrared (IR) radiation is described which is formed of an epitaxial film of superconductive material having a high transition temperature Tc. Specifically, an oxide of yttrium barium and copper is preferred for the high Tc material. The sensor is formed on a single crystalline silicon body suspended by a silicon nitride membrane over a gap formed in a silicon base body and thermally isolated thereby.

Abstract: A method of bonding together two dissimilar planar bodies, one of which is a semiconductor. A film of palladium is deposited on one of the bodies. The two bodies are pressed together with moderate force with the palladium in between. The palladium chemically reacts with the semiconductor and, at least in the case of GaAs, dissolves the surface oxide and forms a crystalline palladium/semiconductor product topotaxial with the semiconductor.

Abstract: A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices.

Abstract: A method for fabricating single crystal islands on a high temperature substrate, thereby allowing for the use of high temperature processes to further make devices incorporating the islands such as, for example, high mobility thin film transistor integrated drivers for active matrix displays.

Abstract: A method for making a laser screen for a cathode-ray tube involves forming a partly transparent mirror of a material resistant to etching solutions on a polished side of a semiconductor member to cover a part of the surface area of the polished side of the semiconductor member surrounding an image forming area. A layer of the semiconductor member of a thickness of 20 to 50 .mu.m is etched off on this polished side to define a support surface surrounding the image forming area which is equally spaced from the outer surface of the partly transparent mirror. A transparent support member is cemented to the outer surface of the partly transparent mirror. The other side of the semiconductor member opposite to the support member is polished, and a reflecting mirror is formed on this surface.

Abstract: A method of producing a semiconductor substrate, comprises the steps of: forming pores in the entire body of a single-crystal silicon substrate by anodization; epitaxially growing a single-crystal silicon layer on a surface of the porous single-crystal silicon substrate; sticking a supporting substrate to the surface of the epitaxial layer of single-crystal silicon by using an adhesive; selectively etching the porous single-crystal silicon substrate; sticking the epitaxial layer fast to a transparent insulating substrate containing SiO.sub.2 as a main constituent; separating the supporting layer from the epitaxial layer by removing the adhesive; and heat-treating the epitaxial layer stuck fast on the transparent insulating layer. Alternatively, a porous layer is formed in a surface portion of a single-crystal silicon substrate, and then, the non-porous portion is removed before the porous layer is selectively etched.

Abstract: A solar cell device is produced by forming at least one semiconductor layer of single crystalline material having an uneven surface on a substrate. A photovoltaic element utilizing the semiconductor layer is formed and bonded to another substrate. The produced solar cell device has a large area, high conversion efficiency and may be mass produced at low cost.

Abstract: A method of making a backside illuminated image includes forming a device on the frontside of thin device layer provided on an oxide layer which is mounted on a sacrificial substrate and bonding the front side of the device layer to a permanent silicon support substrate. Thereafter, the oxide layer and sacrificial layer are removed by chemical etching to expose the backside of the thin device layer.

Abstract: This invention relates to a process and an apparatus for making a substrate of a semiconductor of a monolithic silicon wafer, or the like, for use as a discrete element such as a transistor, diode, or the like. In particular, the invention is directed to re-slicing the silicon wafer into two further pieces, to dope impurity diffused layers on both sides but not to provide any impurity diffused layer in the core portion of the silicon wafer. The re-slicing process is performed from substantially the center portion of its core thickness of the wafer so as to provide each re-sliced surface as a plain surface without any impurity diffused layer and for doping a further new impurity diffused layer, so as to obtain two pieces of a substrate as discrete elements simultaneously from one piece of the wafer by the re-slicing process and apparatus of the invention.

Abstract: A first semiconductor substrate provided with an oxide film having protruded portions on a principal surface thereof is laminated and thermally bonded to a second substrate having recessed portions corresponding to the protruded portions. Alternatively, a first semiconductor substrate provided with an oxide film having recessed portions formed on a principal surface thereof is laminated and thermally bonded to a second semiconductor substrate provided with an oxide film constituting protruded portions corresponding to the recessed portions. The thermally bonded semiconductor substrates are polished from the side of the semiconductor toward the oxide film, and the protruded portions of the oxide film are used as a stopper, thus enabling a semiconductor layer having a desired thickness to be formed on the oxide film.

Abstract: This invention provides a bonded wafer of the n/n.sup.+ or p/p.sup.+ step junction or the SOI configuration possessing an outstanding getter effect by bonding two wafers thereby forming a n/n.sup.+ or p/p.sup.+ stage junction or a SOI configuration and, prior to the bonding, incorporating in one of the wafer surfaces an oxidation-induced stacking fault capable of producing a gettering effect. When a semiconductor device is produced by forming necessary components on the second semiconductor wafer surface side of the bonded wafer of this invention, therefore, the leak current across the pn junction of the semiconductor device is decreased, the life time of the carrier is improved, and the yield of the semiconductor device is notably enhanced without reference to the discrimination between the MOS type and the bipolar type.

Abstract: A process for supporting an image sensor wafer includes providing a support oxide layer on one surface of a support wafer and an etch resistant layer on the opposite surface. The support oxide layer is bonded to the image sensor oxide layer.

Abstract: A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed.

Abstract: A bonded wafer enjoying high strength of bonding of component wafers thereof is produced by a method which comprises causing the surfaces for mutual attachment of two semiconductor wafers to be irradiated with an ultraviolet light in an atmosphere of oxygen immediately before the two semiconductor wafers are joined to each other. One of the two semiconductor wafers to be used for the bonded wafer optionally has an oxide film formed on one surface thereof. One of the component wafers of the bonded wafer is optionally polished until the component wafer is reduced to a thin film.