Abstract: A semiconductor device fabricating method is capable of securing an increased margin for absorbing an error in aligning a viahole with an underlying wiring layer when forming a viahole in a layer insulating film to connect an upper wiring layer overlying the layer insulating film and a lower wiring layer underlying the layer insulating film to enable the miniaturization of a pattern and the miniaturization of the semiconductor device. The semiconductor device fabricating method forms a first Si.sub.3 N.sub.4 film between a first wiring layer and a second wiring layer, and a second layer insulating film, a third layer insulating film and a fourth layer insulating film all of SiO.sub.2 over the second wiring layer. When forming a third viahole through the layer insulating films so as to reach the second wiring layer, the layer insulating films are etched in a high SiO.sub.2 /Si.sub.3 N.sub.4 selectivity of about twenty.

Abstract: The present invention teaches a method for fabricating semiconductors. The method initially comprises the step of forming a conformal layer superjacent at least two conductive layers. The conformal layer preferably comprises tetraethylorthosilicate ("TEOS") and has a thickness of at least 50 .ANG.. Subsequently, a barrier layer is formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer preferably comprises Si.sub.3 N.sub.4, though other suitable materials known to one of ordinary skill in the art may be employed. Further, a glass layer is then formed superjacent the barrier layer. The glass layer comprises at least one of SiO.sub.2, phosphosilicate glass, borosilicate glass, and borophosphosilicate glass, and has a thickness of at least 1 k.ANG.. Upon forming the glass layer, the glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.

Abstract: The semiconductor device includes in a semiconductor substrate (1) at least one predetermined region (6) of the substrate intended subsequently to form an active area, uncovered on its upper surface and situated between lateral trenches (7) containing an insulative material including a layer (9) of a planarising first oxide and at least one underlying layer (8) of a conformal second oxide. The insulative material can form on either side of said uncovered predetermined region (6) of the substrate a boss (16) on the plane upper surface of the device (D) less than 1000 .ANG. high.

Abstract: A semiconductor device including a layer formed without being affected by a stepped ground pattern and a method of fabricating the semiconductor device are disclosed. Cap portions (30) (insulating layers) formed over trenches (13) and covering doped polysilicon (5) have an inclined surface (26) which satisfies Y/X <5 where X is the length of the inclined surface (26) in a direction of the surface of a body (50) and Y is the height of the inclined surface (26) from the surface of the body (50). Formation of the insulating layers having the smooth inclined surface satisfying Y/X<5 permits a first main electrode to be formed nondefectively without being affected by the ground pattern including the insulating layers.

Abstract: A process for producing a semiconductor device, comprising the steps of: (i) forming a transistor having a gate electrode, channel region and source/drain regions on a semiconductor substrate, followed by forming an interlayer insulation film on the entire semiconductor substrate including the transistor; (ii) forming a contact hole extending to either of the gate electrode and each of source/drain regions in the interlayer insulation film on the gate electrode or source/drain regions of the transistor; (iii) forming a resist mask having an opening above the channel region of the transistor on the interlayer insulation film, and implanting ions into the channel region by using the resist mask to write data; (iv) annealing the entire semiconductor substrate at a temperature of about 700.degree. C. to about 800.degree. C. in an atmosphere of an inert gas; and (v) forming a wiring.

Abstract: The present invention teaches a method for fabricating semiconductors. The method initially comprises the step of forming a conformal layer superjacent at least two conductive layers. The conformal layer preferably comprises tetraethylorthosilicate ("TEOS") and has a thickness of at least 50 .ANG.. Subsequently, a barrier layer is formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer preferably comprises Si.sub.3 N.sub.4, though other suitable materials known to one of ordinary skill in the art may be employed. Further, a glass layer is then formed superjacent the barrier layer. The glass layer comprises at least one of SiO.sub.2, phosphosilicate glass, borosilicate glass, and borophosphosilicate glass, and has a thickness of at least 1 k.ANG.. Upon forming the glass layer, the glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.

Abstract: In a method of planarizing a semiconductor wafer having aluminum interconnect tracks formed thereon, a method is disclosed for applying inorganic spin-on glass which comprises applying the spin-on glass to the wafer in a coating and spinning chamber in a moisture-free environment, transferring the wafer in a moisture-free environment to a curing station, curing the spin-on glass at a temperature in the range of about 80.degree. to 250.degree. C. in the moisture-free environment at the curing station, and returning the wafers to the coating and spinning chamber. The above steps are repeated until a sufficient film thickness has been achieved without in the interim exposing the wafer to moisture conditions such that reverse hydrolysis si minimized during the planarization process. In this way crack-free inorganic SOG films can be produced.

Abstract: A method of reflowing borophosphosilicate glass wherein wafers on a support that holds the wafers upright in spaced parallel relationship are introduced into a furnace. The wafers are heated to a temperature to achieve reflow while a main stream of heated inert gas is flowed over the wafers in a direction perpendicular to the planes of the substrates, while simultaneously an auxiliary stream of heated inert gas is flowed in a direction perpendicular to the main stream to prevent the formation of BPO.sub.4 crystals during reflow.

Abstract: There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film.

Abstract: A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate.

Abstract: A method for fabricating semiconductors is provided in which a conformal layer is formed superjacent at least two conductive layers. The conformal layer has a thickness of at least 50 .ANG.. A barrier layer is then formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer is preferably Si.sub.3 N.sub.4. A glass layer is then formed superjacent the barrier layer. The glass layer has a thickness of at least 1 k.ANG.. The glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.2 at a high temperature to cause vaporization, thereby causing the glass layer to reflow. Next, the glass layer is exposed to a gas and radiant energy for 5 to 60 seconds, thereby making said glass layer planar. The radiant energy generates a temperature within the range of 700.degree. C. to 1250.degree. C. Further, the gas is at least one of N.sub.2, NH.sub.3, O.sub.2, N.sub.2 O, Ar, Ar-H.sub.2, H.sub.

Abstract: A method for forming a planar insulating layer over the surface of a semiconductor workpiece 8 which includes at least one low region 13 is discussed herein. The first step is to form a layer of blocking material 14 on the surface of the workpiece 8. A first material region 20 is then formed in the low region 13 and an insulating layer 21 is formed over the surface of the workpiece 8 including the first material region 20. The workpiece 8 is then heated in the presence of an active ambient such that the insulation layer 21 reflows and also so that the first material 20 region reacts with the active ambient to create an internal stress in said insulation layer 21. Other systems and methods are also disclosed.

Abstract: A manufacturing method of semiconductor devices according to this invention, comprises the step of forming pattern portions containing internal wiring layers on a semiconductor substrate, the step of forming interlayer insulating films on said semiconductor substrate, the step of forming an opening portion in said interlayer insulating films so as to allow the pattern portions and the substrate to appear, and the step of forming a sidewall insulating film on the sidewall of the pattern portions appearing in the opening portion.

Abstract: A CMOS integrated circuit fabrication technique for forming self-aligned transistors combined with local planarization in the vicinity of the transistors so as to allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. The technique is compatible with planarization schemes using BPSG, BPTEOS, SOG or CMP. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer is etched back to planarize the surface. Using a buried contact mask the remaining portions of the glass layer and underlying oxide layer are removed in the area of the buried contact only.

Abstract: Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.

Abstract: An embodiment of the present invention is a semiconductor fabrication process that deposits an oxide layer after a step to make contact openings in a BPSG layer and before a contact reflow step. The oxide allows implant dopants to be properly activated in the contact reflow step without excessive reflow of the BPSG.

Abstract: A method for making a NMOS self-aligned contact in CMOS circuits without an extra mask is described. The maskless contact technique makes use of the fact that the blanket N-type implant, self-aligned to exposed field-oxide edge, will not change the P+ diffusion to N-type. The net P+ concentration in the contact region is reduced slightly but does not degrade the PMOS device performance.

Abstract: A method of reflowing a semiconductor device to increase the planarization thereof includes the steps of first forming a first insulating layer over a silicon semiconductor substrate, forming at least one electrode over the first insulating layer, and then forming a second insulating layer over the at least one electrode and the first insulating layer. A first borophospho silicate glass (BPSG) layer of low concentration is then formed over the resultant surface to a thickness of 6000 to 9000 .ANG. and containing 3-4 wt. % boron and 5-7 wt. % phosphorous. A second borophospho silicate glass (BPSG) layer of high concentration is formed over the resultant surface of the first borophospho silicate glass (BPSG) layer to a thickness of 2000 to 6000 .ANG. and containing 4-7 wt. % boron and 8-10 wt. % phosphorous.

Abstract: Reverse engineering of integrated circuit devices is prevented by denying visual access to the topology of an integrated circuit device. Visual access is denied by coating the device with an opaque ceramic. The opaque ceramic is produced by first mixing opaque particulate with a silica precursor. The mixture is then applied to the surface of the integrated circuit device. The coated device is heated to a temperature in the range of 50.degree. C. to 450.degree. C. in an inert environment for a time within the range of 1 second to 6 hours to allow the coating to flow across the surface of the device without ceramifying. The coated device is then heated to a temperature in the range of 20.degree. C. to 1000.degree. C. in a reactive environment for a time in the range of 2 to 12 hours to allow the coating to ceramify.

Abstract: A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer if insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.

Abstract: A method for forming field effect devices having lightly doped drain regions requires only a single dope and implant step. After patterning of the polycrystalline silicon gates, sloped sidewall spacers are formed alongside the gates. These spacers have a relatively linear slope from the top corners of the polycrystalline silicon gates to the substrate. A single implant of dopant results in heavily doped regions beyond the sidewall spacers with more lightly, and shallowly, doped regions next to the channel.

Abstract: A planarizing process for planarizing an integrated circuit structure in a CVD apparatus is disclosed using a low melting inorganic planarizing material which comprises flowing white depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon, then dry etching the low melting inorganic planarizing layer to planarize the structure, and then depositing a further layer of an insulating material to encapsulate any remaining portions of the low melting glass planarizing layer which may be hygroscopic. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are all carried out without removing the integrated circuit structure from the apparatus.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming an insulating layer by the CVD method on a main surface of a semiconductor substrate, fluidizing the insulating layer by heat treatment, unifying a thickness of the insulating layer, opening contact holes in desired points of the insulating layer, and forming conductor contacts for interconnection on the contact holes. The insulating layer is has a uniform thickness in any area on the semiconductor device, so that over-etching of the insulating layer in opening contact holes can be prevented, and the step coverage is well improved.

Abstract: The method for fabrication of openings in semiconductor devices to improve metal step coverage includes forming an active region over a substrate. A metal oxide layer is then formed over the source/drain region. An insulating layer is formed over the metal oxide layer. A photoresist layer is formed over the insulating layer, and patterned to form an opening, exposing a portion of the insulating. The insulating layer is then etched to expose a portion of the metal oxide layer. The photoresist layer is removed and the insulating layer is reflowed so as to form rounded corners at the opening of the insulating layer. The exposed portion of the metal oxide layer is removed to expose a portion of the active region.

Abstract: A method for introducing an impurity into a polysilicon formed on an insulating film is described. A silicate glass layer (13) containing As is formed on a polysilicon layer (12) formed on an insulating film (2) and is thermally treated to introduce As into the polysilicon layer (12). The silicate glass layer (13) has a concentration of arsenic of not less than 25 wt. %, calculated as As.sub.2 O.sub.3 and the thermal treatment is effected in an atmosphere of a mixed gas of N.sub.2 and O.sub.2 with an oxygen partial pressure ratio of 0.05-0.7 at not lower than 1000.degree. C. for not shorter than 60 minutes.

Abstract: A planarizing process is disclosed for planarizing an integrated circuit structure using a low melting inorganic planarizing material which comprises flowing while depositing a low melting inorganic planarizing layer such as a boron oxide glass over a layer of insulating material such as an oxide of silicon and then dry etching the low melting inorganic planarizing layer to planarize the structure. The method eliminates the need for separate coating, drying, and curing steps associated with the application of organic-based planarizing layers usually carried out outside of a vacuum apparatus. In a preferred embodiment, the deposition steps and the etching step are carried out without removing the integrated circuit structure from the vacuum apparatus. An additional etching step may be carried out after depositing the insulating layer and prior to deposition of the planarizing layer to remove any voids formed in the insulating layer.

Abstract: A process of fabricating a multi-level wiring structure starts with preparation of a semiconductor substrate covered with a lower insulating film, and comprises the steps of forming lower-level wiring strips on the lower insulating film, covering the lower-level wiring strips and exposed portions of the lower insulating film with a first intermediate insulating film, coating the entire surface with an organic glass film, removing the organic film except for pieces of the organic glass film in valleys between the lower-level wiring strips, coating the entire surface with an inorganic glass film, removing the inorganic glass film except for pieces of the inorganic glass film on the pieces of the organic glass film, covering the entire surface with a second intermediate insulating film, and forming upper-level wiring strips on the intermediate insulating film, wherein the pieces of the inorganic glass film prevent the upper-level wiring strips from corrosion due to water vapor produced from the pieces of the org

Abstract: A glass deposition viscoelastic flow process for forming planar and semi-planar insulator structures on semiconductor devices, which comprises feeding vaporized reactants into a reaction chamber at a reaction temperature between 750.degree.-950.degree. C. and subjecting the surface of the semiconductor devices to a high reactant velocity. The high reactant velocity allows the formation of a high quality, uniform glass layer at temperatures compatible with the fusion temperature, so that deposition occurs simultaneously with the viscoelastic flow of the glass. The simultaneous deposition and flow provides for topographical planarization substantially free of voids and other layer inconsistencies.

Abstract: A method for encapsulation of an integrated circuit array that suppresses or eliminates absorption and subsequent out-gassing of water vapor and suppresses or eliminates out-gassing of toxic constituents of the encapsulation layer such as trimethyl borate. A first layer of borophosphosilicate glass is deposited on the integrated circuit array, followed immediately by deposit of a thin cap layer of undoped oxide of silicon. The method also allows use of boron and phosphorous concentrations in the borophosphosilicate glass as high as 9 weight percent with no loss of stability of that layer, before or after thermal treatment. Reflow processing temperatures as low as T.sub.r =700.degree.-900.degree. C. may be used here. Alternatively, silicon nitride can replace the silicon oxide in the cap layer, using either a high temperature process or a lower temperature plasma-enhanced process.

Abstract: A method of manufacturing a semiconductor device in which an element is flattened by improving a technique of forming an interlayer insulating film. A thick insulating film having a film thickness necessary for a convexo-concave pattern to be flattened is deposited on a semiconductor substrate comprising the convexo-concave pattern of an element, a wiring and the like. Then, the thick insulating film is etched until it becomes a predetermined film thickness to form an interlayer insulating film having a predetermined film thickness from said thick insulating film. At this time, since acid and water are attached on the surface of the interlayer insulating film, a new film is formed on the surface of the interlayer insulating film to cover this water and acid. Then, a resist pattern having a desired configuration is formed on this new film. A contact hole is formed on the interlayer insulating film using this resist pattern.

Abstract: A method is set forth of bonding together two bodies (1, 2), according to which a first body (1) is provided with a flat surface (5) and the second body (2) is provided with a silicon oxide layer (4) with a flat surface (6), after which a connecting layer (7) containing boron is provided on at least one of the two flat surfaces. Subsequently, the two bodies (1, 2) are pressed together at elevated temperature, so that a borosilicate glass layer is formed. According to the invention, a layer of practically pure boron is used by way of connecting layer (7). Among the advantages of this is that the composition of the borosilicate glass layer is exclusively determined by the previously chosen layer thicknesses.

Abstract: This invention is directed to a process of producing semiconductor devices which involves deposition of protective glass layers by a particle beam technique from targets of phosphosilicate glass, as well as a process for production of such targets. The phosphosilicate glass containing 1-15 mole percent P.sub.2 O.sub.5 is produced by a sol/gel technique which involves mixing of a fumed silica, with a surface area of 50-400 m.sup.2 /g, preferably about 200 m.sup.2 /g, with phosphoric acid and water to form a sol with 20-55 wt. % silica, allowing it to gel, drying at ambient conditions, dehydrating at about 650.degree. C. in an atmosphere of an inert gas and chlorine and fluorine containing gases, heating up at a certain rate of from 100.degree. to 180.degree. C. per hour to a peak sintering temperature below 1200.degree. C. and cooling so as to produce amorphous and transparent glass suitable for use as a target. The glass layers are highly advantageous as encapsulating layers, diffusion barrier layers, etc.

Abstract: A technique for effectively doping a storage node capacitor plate constructed from low temperature deposited rugged polysilicon. A phosphorus silica glass is deposited prior polysilicon deposition and used primarily to uniformly diffuse n-type dopants into the subsequently deposited rugged poly capacitor plate. This doping technique eliminates the need for high temperature doping and will maintain the rugged surface in the poly of the capacitor plate.

Abstract: The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer.

Abstract: A method of fabricating high speed, low leakage, radiation hardened integrated circuit semiconductor devices. In accordance with the method a SIMOX (separation by ion implantation of oxygen) wafer is masked with a separation mask to form silicon islands. The separation mask forms groups of N-channel and P-channel devices that are isolated from each other. The N- and P-channel device separation assists in preventing device latch-up. N- and N-channel devices are isolated by controlling the process due to high field inversion thresholds and radiation hardened field oxide to eliminate any channel-to-channel leakage current after high dosage irradiation. A relatively thin gate oxide layer is formed over the islands, and the island edges are covered with phosphoroborosilicate glass deposited at a relatively low temperature (850.degree. C.) to eliminate sharp island edges and hence edge leakage.

Abstract: In a process of fabrication of a semiconductor device having a relatively deep contact hole and a relatively shallow contact hole; a lower interlayer insulating layer is formed on a semiconductor substrate, and then subjected to heat treatment to flow; an upper interlayer insulating film is then formed on the lower interlayer insulating film, and is then subjected to heat treatment to flow; a non-flowing film which does not flow is then formed in the area where the shallow contact hole will be formed; and the deep and the shallow holes are then formed through the upper interlayer insulating film and the non-flowing film and heat treatment is conducted to cause flow of the upper interlayer insulating film whereby the flow of the upper interlayer insulating layer occurs except at the area covered by the non-flowing film. The deep and the shallow contact holes are then filled with metal by selective CVD; and an interconnection is then formed to have contact with the metal filling the contact holes.

Abstract: A Phospho Silicate Glass layer is used for an insulation layer between a lower wiring layer including a refractory metal silicide and an upper wiring layer in a semiconductor device of a multilevel interconnection structure. A reflow treatment is performed on the Phospho Silicate Glass layer using steam. A part of the lower wiring layer is oxidized during the reflow treatment, and the resistivity of the lower wiring layer is simultaneously lowered during the reflow treatment.

Abstract: A method of making a fine mask pattern suitable for making a compound semiconductor device in which a source and drain regions are formed on both sides of a groove defined in a substrate and both regions are separated from the side walls of the groove by predetermined intervals through a first region with a depth shallower than the groove. A second region is formed between the source and drain region with a depth deeper than said groove. A gate electrode is formed on the surface of the second region in the groove for Schottky contacting with the upper surface of the second region.

Abstract: An improved planarization process is disclosed which comprises depositing over a patterned integrated circuit structure on a semiconductor wafer a conformal insulation layer by ECR plasma deposition of an insulation material. The ECR plasma deposition is carried out until the trenches or low regions between adjacent raised portions of the structure are completely filled with insulation material. A planarization layer of a low melting glass material, such as a boron oxide glass, is then flowed as it is deposited over the integrated circuit structure to a depth or thickness sufficient to cover the highest portions of the ECR plasma deposited insulation layer. This planarization layer is then anistropically etched back sufficiently to provide a planarized surface on the ECR plasma deposited insulation layer.

Abstract: A method of manufacturing a semiconductor device, includes the following steps: part of an insulation film is left on the bottom of a contact hole of the insulation film formed on a semiconductor substrate or a separate insulation film is otherwise formed, under which condition a satisfactory slope is formed on the peripheral edge and the side wall of the contact hold by providing the semiconductor substrate with a heat treatment. According to the present invention, it is possible thereafter to improve the step coverage of a metal interconnection to be formed on the surface of the insulation film and to prevent breakage of the metal interconnection, thereby substantially improving the reliability of the resulting semiconductor device.

Abstract: A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500.degree. C.

Abstract: A method for fabricating contacts in a semiconductor substrate includes forming a thin buffer oxide layer (26) over a substrate (10) with active devices defined therein. Access openings (28), (30) and (32) are then formed in the thin oxide layer (26) and then aluminum columnar contacts (38), (40) and (42) formed therein with a predetermined height. A thick oxide layer of phosphorous silicate glass (50) is then formed over the built-up structure. A planarizing resist layer (52) is formed over top of the structure with a substantially thinner area defined proximate the upper surfaces of the columnar contacts (38, 40, 42). The thin areas (54, 56, 58) are removed by selectively etching away the upper surface of the resist layer (52) by an excited plasma process. The structure is then subjected to a phosphorous selective etch to remove only those portions of the thick oxide layer (52') proximate the upper surfaces of the columnar contacts (38, 40, 42).

Abstract: A method for forming a smooth borophosphosilicate glass film on a semiconductor substrate is described, in which a semiconductor substrate having at least one stepped portion thereon is formed with one side of the substrate a borophosphosilicate glass layer having a defined boron content and a defined phosphorus content with a defined total content of the boron and phosphorus. The layer is subjected to thermal treatment under conditions of a temperature of not lower than 940.degree. C. and a time of not shorter than 15 minutes in an atmospheric gas supplied at a flow rate of not lower than 19 liters/minute. As a result, the BPSG glass layer is smoothed on the surface thereof without formation of undesirable grains on the surface. This thermal treatment is particularly suitable for fabrication of a semiconductor element or device using an insulating film of the borophosphosilicate glass.

Abstract: A process for manufacturing an insulated gate field effect semiconductor device having self-aligned contact regions. The process avoids the need for a masking step for the application of interconnecting contacts by providing a dielectric material having a low melting point over the gate region of the semiconductor. The dielectric material is heated to its melting point such that it covers and encapsulates the gate. Contact material is then subsequently provided using the self-alignment feature of the melted dielectric which isolates the gate from the contacts.

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.

Abstract: A process for manufacturing a bipolar semiconductor device having self-aligned contact regions. The process avoids the need for a masking step for the application of interconnecting contacts by providing a dielectric material having a low melting point over the emitter region of the semiconductor. The dielectric material is heated to its melting point such that it covers and encapsulates the emitter. Conductive contact material is then subsequently provided using the self-alignment feature of the melted dielectric which isolates the base from the contacts.

Abstract: A glass reflow step to round off sharp edges of contact vias is typically included in processes for making integrated-circuit devices. In the course of making such devices with closely spaced vias, it has been found that unacceptable overhangs occur on the sidewalls of the vias. Neither changes in the composition of the glass nor modifications in the processing parameters of reflow were effective to avoid the overhang phenomenon. In accordance with the invention, it has been discovered that the overhang problem can be consistently avoided if the ratio of glass thickness to via-to-via spacing is about .ltoreq.0.393.

Abstract: A method for the manufacture of a large scale integration (LSI) MOS field effect transistor wherein a gate electrode is generated on a doped silicon substrate, source/drain regions are formed by ion implantation using the gate electrode as an implantation mask and the source/drain regions are shielded by means of an oxide layer extending to the sidewalls of the gate electrode so that the diffusion of the implanted source/drain regions under the gate electrode area are reduced. The specific improvement of the present invention involves applying a readily flowable silicate glass layer as a gate edge masking for the source/drain ion implantation after formation of the gate electrode, the silicate glass layer being applied by deposition from the vapor phase at a thickness such that the dopant ions in the subsequent source/drain ion implantation are still implanted into the zone near the surface under the silicate glass layer but ion implantation into the zones at the edges of the gate is suppressed.

Abstract: An improved integrated circuit structure characterized by enhanced step coverage and a method of making it are disclosed. The structure comprises a base layer of silicon, a first oxide layer on the silicon layer, strips of poly silicon having selected portions thereof reacted with a metal capable of forming a metal silicide in situ on the surface of the poly silicon strips, a further oxide layer over the metal silicide, and a metal layer providing electrical contact to selected portions of the structure. The construction makes it possible to remove all of an intermediate oxide layer during manufacture except for an oxide layer above the poly load resistor. This elimination of one oxide layer, together with the integration of the conductive metal silicide and underlying poly silicon into one layer and the rounding of the metal silicide edge with oxide spacers via anisotropic etching of the intermediate oxide layer, permits better step coverage for the resulting structure.

Abstract: Reduction of the encroachment of a grown field oxide layer during MOS device fabrication by covering a masking anti-oxidant layer that defines the active element area of a semiconductor substrate with a layer of passivation material which extends over the edge of the anti-oxidant layer to contact the pad oxide over the semiconductor substrate surface.