Schottky Barrier Contacts Patents (Class 148/DIG140)
  • Patent number: 5693548
    Abstract: A method for making a T-shaped gate of a field effect transistor is disclosed. The method includes the steps of sequentially depositing first and second photoresist layers on a semiconductor substrate and performing an exposure using electron beams having different energy, one of the electron beams having a first energy to lightly expose only the second photoresist layer and the other of the electron beams having a second energy to lightly expose all of the first and second layers. The invention reduces gate resistance and parasitic capacitance of the T-shaped gate.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: December 2, 1997
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jin-Hee Lee, Sang-Soo Choi, Hyung-Sup Youn, Chul-Soon Park, Hyung-Jun Yoo, Hyung-Moo Park
  • Patent number: 5688703
    Abstract: A method of manufacturing a gate structure (19) for a semiconductor device (10) utilizes a dielectric layer (17) containing aluminum to protect the surface of a substrate (11) from residues resulting from deposition and etching of the gate structure (19). The gate structure (19) forms a refractory contact to the substrate (11), and the source and drain regions (26) are self-aligned to the gate structure (19). Semiconductor devices manufactured using methods in accordance with the present invention are observed to have a higher breakdown voltage and a higher transconductance, among other improved electrical performance characteristics.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: November 18, 1997
    Assignee: Motorola, Inc.
    Inventors: Lawrence S. Klingbeil, Jr., Marino J. Martinez
  • Patent number: 5610097
    Abstract: A method for forming electrodes on a semiconductor includes introducing at least one reactive oxidizing gas selected from the group consisting of ozone, atomic oxygen, nitrogen dioxide, oxygen ion and oxygen plasma to an oxide semiconductor surface and depositing electrode material on the oxide semiconductor surface without exposing the surface to the outside atmosphere.
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: March 11, 1997
    Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventor: Takashi Shimizu
  • Patent number: 5569614
    Abstract: An insulating film is formed on the surface of the base of a semiconductor, and a portion of the insulating film is removed to cause the surface to appear outside. The exposed surface is terminated with hydrogen, and then energy beams are applied to selectively remove the terminating hydrogen. Metal is selectively deposited on the portion terminated with left hydrogen atoms.
    Type: Grant
    Filed: May 5, 1995
    Date of Patent: October 29, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuzo Kataoka, Tetsuo Asaba, Kenji Makino, Hiroshi Yuzurihara, Kei Fujita, Seiji Kamei, Yutaka Akino, Yutaka Yuge, Mineo Shimotsusa, Hideshi Kuwabara
  • Patent number: 5563081
    Abstract: A method for making a nonvolatile memory device having a field effect transistor for storing information, and a Schottky diode in series with the field effect transistor. The field effect transistor includes source and drain regions in a semiconductor substrate, with a channel region interposed between them and a gate electrode above the channel region. A ferroelectric gate film is sandwiched between the channel region and the gate electrode. In the method, a conductive barrier meterial is deposited in contact with the source region of the field effect transistor to make the Schottky diode. In reading information from the memory device, voltage is applied to a serial circuit consisting of the field effect transistor and the Schottky diode to turn the Schottky diode on.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: October 8, 1996
    Assignee: Rohm Co., Inc.
    Inventor: Takanori Ozawa
  • Patent number: 5550065
    Abstract: A method of fabricating a self-aligned FET having a semi-insulating substrate of GaAs or InP with a conductive channel formed either by doping the surface or an epitaxially grown channel by molecular beam epitaxy or metalorganic vapor phase epitaxy in the substrate adjacent the surface. Forming a high temperature stable LaB.sub.6 /TiWN "T-shaped" Schottky gate contact on the substrate surface, which is used for source and drain ohmic region implants into the substrate adjacent to the surface and self-aligned to the "T-shaped" gate, with source and drain ohmic contacts also self-aligned with respect to the gate.
    Type: Grant
    Filed: November 25, 1994
    Date of Patent: August 27, 1996
    Assignee: Motorola
    Inventors: Majid M. Hashemi, Saied N. Tehrani, Patricia A. Norton
  • Patent number: 5478764
    Abstract: A method of producing a semiconductor device including a Schottky barrier diode (SBD) comprising the steps of: selectively forming an insulating layer having a first contact hole and a second contact hole, on a (100) silicon semiconductor substrate; selectively forming a polysilicon layer extending from the first contact hole to the second contact hole, the polysilicon layer having a viahole within the first contact hole for selectively exposing the silicon semiconductor substrate; and selectively depositing a refractory metal (tungsten or molybdenum) layer on the polysilicon layer and an exposed portion of the substrate within the viahole by a selective CVD process, so that the SBD is formed between the exposed portion and the metal layer. The refractory metal layer is formed on the silicon of the exposed portion of the substrate and the polysilicon layer and is not formed on the insulating layer, and thus it is unnecessary to perform a photolithography process for patterning the refractory metal layer.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: December 26, 1995
    Assignee: Fujitsu Limited
    Inventor: Kenichi Inoue
  • Patent number: 5418185
    Abstract: A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent to the Schottky barrier 40 and is separated from the conductive contact 36 by a portion of the semiconductor layer 24. No direct electrical path exists between the guard ring 26 and the conductive contact 36.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: May 23, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: James R. Todd, Joe R. Trogolo, Andrew Marshall, Eric G. Soenen
  • Patent number: 5393698
    Abstract: A process for fabricating gold/gallium arsenide structures, in situ, on molecular beam epitaxially grown gallium arsenide. The resulting interface proves to be Ohmic, an unexpected result which is interpreted in terms of increased electrode interdiffusion. More importantly, the present invention surprisingly permits the fabrication of Ohmic contacts in a III-V semiconductor material at room temperature. Although it may be desireable to heat the Ohmic contact to a temperature of, for example, 200 degrees Centigrade if one wishes to further decrease the resistance of the contact, such low temperature annealing is much less likely to have any deleterious affect on the underlying substrate. The use of the term "in situ" herein, contemplates continuously maintaining an ultra-high vacuum, that is a vacuum which is at least 10.sup.-8 Torr, until after the metallization has been completed.
    Type: Grant
    Filed: February 1, 1989
    Date of Patent: February 28, 1995
    Assignee: California Institute of Technology
    Inventors: William J. Kaiser, Frank J. Grunthaner, Michael H. Hecht, Lloyd D. Bell
  • Patent number: 5298437
    Abstract: A method for fabricating a diode, for example, for use in a Schottky clamped transistor, which as a process step disposes a layer of oxide between the substrate and the overlying layer of polysilicon which must ultimately be etched away. The oxide layer permits use of an end point dry etch process which in turn allows greater miniaturization of the circuit over wet etch processes. Use of the end point process made feasible by the oxide layer also prevents overetch of the silicon material. As a result, a more ideal metal silicide anode-to-substrate Schottky barrier is formed with corresponding improvements in the diode ideality factor. In addition the oxide layer eliminates Schottky mask alignment problems and further improves diode performance characteristics by elimination of parasitic diodes. The process can be implemented with minimal deviation from other core processes used to fabricate similar circuits.
    Type: Grant
    Filed: July 28, 1992
    Date of Patent: March 29, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Brian McFarlane, Frank Marazita, John E. Readdie
  • Patent number: 5268316
    Abstract: An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction.
    Type: Grant
    Filed: June 12, 1992
    Date of Patent: December 7, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Murray J. Robinson, Christopher C. Joyce, Tim Wah Luk
  • Patent number: 5229323
    Abstract: A method for manufacturing a semiconductor device with a Schottky electrode includes the steps of subjecting the surface of a GaAs substrate to a sputtering etching process in a sputtering processing chamber of a sputtering device; and depositing Schottky electrode material by sputtering on the surface of the substrate to form a Schottky electrode in the processing chamber without exposing the substrate to the atmosphere.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: July 20, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kizashi Shimada, Tatsuo Akiyama, Yutaka Koshino
  • Patent number: 5221638
    Abstract: According to the present invention, there is provided a method of manufacturing a Schottky barrier semiconductor device with lesser variation of barrier height .phi.B which may stably be adjusted in a wide range. A Schottky barrier is formed by combination of an electrode layer, a Ti thin layer and Al layer. The Ti thin oxide layer between the Ti thin and Al layers may prevent variation of barrier height .phi.B during heat treatment. By controlling vacuum.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: June 22, 1993
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Koji Ohtsuka, Noriyoshi Ohmuro, Gen Koreeda
  • Patent number: 5200357
    Abstract: Disclosed is a method for making self-aligned metal contacts on semiconductor devices, with a submicronic spacing between regions controlled by the contacts. On a semiconductor body supporting at least one raised pattern, a double layer of SiO.sub.2 and Si.sub.3 N.sub.4 is deposited by an isotropic method. A double ionic etching of Si.sub.3 N.sub.4 by SF.sub.6 and of SiO.sub.2 by CHF.sub.3 is done to insulate the sidewalls on the flanks of the pattern. A sub-etching by HF/NH.sub.4 F/H.sub.2 O creates a cap beneath each sidewall. The metal contacts, deposited by evaporation, are self-aligned and separated by a space "d" equal to the thickness of the insulating layers.
    Type: Grant
    Filed: June 6, 1991
    Date of Patent: April 6, 1993
    Assignee: Thomson-CSF
    Inventors: Philippe Collot, Paul Schmidt
  • Patent number: 5187111
    Abstract: The method of manufacturing the SB FET according to the present invention includes a first step of forming a first WN metal film on a GaAs substrate, a second step of forming a first ion-implanted region within the GaAs substrate, by ion implantation of n-type impurities, a third step of forming a second Mo metal film, a fourth step of forming second and third ion-implanted regions adjacent to said first ion-implanted region, within the GaAs substrate, and a fifth step of activating said first, second, and third ion-implanted regions. In the ion implantation of the second step, impurity ions are implanted into the GaAs substrate, through the first metal film. In the fifth step, the first metal film serves as a protective film during the activation of the first, second, and third ion-implanted regions.
    Type: Grant
    Filed: April 23, 1991
    Date of Patent: February 16, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Nogami, Hiroshi Iwasaki
  • Patent number: 5158909
    Abstract: A high voltage, high speed Schottky diode has an electrode of aluminum or like Schottky barrier metal formed on a semiconductor region to create a Schottky barrier therebetween. Also formed on the semiconductor region is a extremely thin resisitve layer of, typically, oxidized titanium surrounding the barrier metal electrode and electrically connected thereto. The resistive layer also creates a Schottky barrier at its interface with the semiconductor region and serves to expand the depletion region due to the barrier metal electrode, thereby preventing the concentration of the electric field at the periphery of the barrier metal electrode and so enhancing the voltage withstanding capability of the diode.
    Type: Grant
    Filed: October 17, 1990
    Date of Patent: October 27, 1992
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Koji Ohtsuka, Yoshiro Kutsuzawa, Kimio Ogata, Hideyuki Ichinosawa
  • Patent number: 5143856
    Abstract: A GaAs epitaxial layer is formed on a semi-insulative GaAs substrate by use of a crystal growth technique which allows control on the order of atomic layer level. A metal film is formed on the GaAs epitaxial layer by use of the same crystal growth technique. Ions are implanted in source and drain high-concentration layer-forming regions, through the metal film, and are activated.
    Type: Grant
    Filed: August 29, 1988
    Date of Patent: September 1, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwasaki
  • Patent number: 5143857
    Abstract: A method of fabricating an integrated circuit comprises providing a heavily compensated substrate having a source region, a drain region and a third region, each of a first conductivity type, and introducing dopant of a second conductivity type into the substrate to surround the third region.
    Type: Grant
    Filed: July 30, 1990
    Date of Patent: September 1, 1992
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Eric P. Finchem, William A. Vetanen, Bruce Odekirk, Irene G. Beers
  • Patent number: 5139968
    Abstract: A semiconductor device includes a relatively broad recess in a semiconductor substrate between a source electrode and a drain electrode, a relatively narrow, deeper recess closer to the source electrode than to the drain electrode, and a T-shaped gate electrode having a broad head disposed in the narrower recess. A production method for a semiconductor device having a T-shaped gate electrode provided with a broad head and disposed in a two stage recess includes producing a relatively broad recess in a semiconductor substrate leaving a dummy gate, producing a resist pattern for producing the head of the T-shaped gate electrode, exposing the dummy gate by removing some of the resist pattern, and thereafter producing a narrower, deeper recess closer to the source electrode than to the drain electrode, thereby producing a two stage recess structure and producing a T-shaped gate electrode in the deeper recess.
    Type: Grant
    Filed: October 31, 1990
    Date of Patent: August 18, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Iwao Hayase, Takuji Sonoda
  • Patent number: 5112763
    Abstract: Provided is a process for precisely forming a Schottky barrier gate on GaAs. In the process, a layer of polyimide is spun onto a doped GaAs substrate having a passivating layer thereon. A resist layer is then spun onto the polyimide, and either deep ultraviolet lithography in conjunction with a clear field mask, or direct electron beam exposure, is used to define a gate region. After exposure, the resist is developed, leaving the unexposed portion of the resist in place on the polyimide layer. A metal transfer layer is then deposited over the structure, and the remaining resist is dissolved leaving a hole in the metal transfer layer. The polyimide and the passivating layer are etched down to the surface of the substrate through the passivating layer. The substrate is then dry etched, and then wet chemical etched to form a recess for the Schottky gate. The Schottky gate metal is deposited onto the surface of the structure and through the hole onto the substrate.
    Type: Grant
    Filed: September 17, 1990
    Date of Patent: May 12, 1992
    Assignee: Hewlett-Packard Company
    Inventors: Thomas W. Taylor, Donald C. D'Avanzo
  • Patent number: 5112774
    Abstract: A semiconductor device such as a Schottky-barrier rectifier diode is disclosed which has a barrier electrode formed on a semiconductor substrate of gallium arsenide or the like. Formed around the barrier electrode is an annular resistive layer, typically of titanium oxide, creating a Schottky barrier at its interface with the semiconductor substrate. The resistive layer has a sheet resistance of more than 10 kilohms per square. In order to prevent preliminary breakdowns from taking place at the peripheral part of the resistive layer before final breakdown of the device, the sheet resistance of the resistive layer is made higher as it extends away from the barrier electrode. For the ease of manufacture, the resistive layer can be divided into two or more annular regions of distinctly different sheet resistances.
    Type: Grant
    Filed: February 15, 1991
    Date of Patent: May 12, 1992
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Koji Ohtsuka, Hirokazu Goto
  • Patent number: 5098858
    Abstract: The method of manufacturing the metal-semiconductor junction in accordance with the present invention includes the step of forming a 2.times.2 surface superstructure in an ultrahigh vacuum by removing an oxide layer by means of a heat cleaning at temperatures not lower than 600.degree. C. while irradiating a (111) A or (111) B surface of a zincblende-type III-V compound semiconductor substrate with a beam of a group V element, the step of cooling the substrate down to room temperature while maintaining the surface superstructure and the step of depositing a metal on the surface.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: March 24, 1992
    Assignee: NEC Corporation
    Inventors: Kazuyoshi Ueno, Kazuyuki Hirose
  • Patent number: 5086014
    Abstract: A schottky diode manufacturing process employing diamond film comprises forming a B-doped p-type polycrystalline diamond film on a low-resistance p-type Si substrate by CVD using a source gas consisting of CH.sub.4, H.sub.2 and B.sub.2 H.sub.6, forming an ohmic contact on the back of the p-type Si substrate, and forming a metal electrode of Al, Pt Au, Ti or W on the B-doped p-type polycrystalline diamond film. The B/C concentration ratio of the source gas is greater than 0.01 ppm and less than 20 ppm.
    Type: Grant
    Filed: September 18, 1990
    Date of Patent: February 4, 1992
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Koichi Miyata, Kazuo Kumagai, Koji Kobashi, Yuichi Matsui, Akimitsu Nakaue
  • Patent number: 5079175
    Abstract: Short circuits on the anode side of thyristors can be manufactured easily d inexpensively if a p-doped layer is first generated on the anode side. On it, after an oxide masking and structuring process, grooves (7) are produced, which extend into the base zone (1) of the thyristor on the anode side, in which the short-circuit areas are then generated. After the oxide has been removed, the anode electrode is applied, which contacts the p-doped layer and the short-circuit areas. As an alternative, the short-circuit areas may also be generated first through the openings of a structured oxide. Then, after removal of the oxide, the entire surface is p-doped, with the doping being less than that of the short-circuit areas. Then the anode electrode is applied.
    Type: Grant
    Filed: December 18, 1990
    Date of Patent: January 7, 1992
    Assignee: Eupec Europaeische Gesellsch. F. Liestungshalbleiter mbH+Co. KG
    Inventors: Gottfried Schuh, Hans-Joachim Schulze
  • Patent number: 5049525
    Abstract: A method is provided for forming multiple layers of interconnection adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: September 17, 1991
    Assignee: Texas Instruments Incorporated
    Inventor: Donald J. Coleman, Jr.
  • Patent number: 5045497
    Abstract: A semiconductor device includes a semiconductor body and a metal contact forming a Schottky barrier with said body, the metal contact including a layer of nickel disposed on the semiconductor body, an aluminum layer disposed on the nickel layer, and a nickel aluminum alloy disposed at the interface of the layers. The alloy is formed by heating the metal layers.
    Type: Grant
    Filed: October 25, 1989
    Date of Patent: September 3, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuo Hayashi, Takuji Sonoda
  • Patent number: 5043294
    Abstract: A method for manufacturing a field effect transistor having source and drain regions asymmetrically arranged relative to the gate region. A strip-shaped auxiliary layer is applied in the region of the gate. A first and second spacer are laterally fashioned along an auxillary layer, the first spacer is covered with a resist mask and the second spacer is subsequently etched away. The source metallization and the drain metallization are then applied, and a planarizing passivation layer is applied therebetween. This is followed by the application of connecting metallizations for the source, drain and gate regions.
    Type: Grant
    Filed: August 29, 1990
    Date of Patent: August 27, 1991
    Assignee: Siemens Aktiengesellschaft
    Inventors: Josef Willer, Guy Lefranc
  • Patent number: 5030583
    Abstract: A textured substrate is disclosed which is amenable to deposition thereon of epitaxial single crystal films of materials such as diamond, cubic boron nitride, boron phosphide, beta-silicon carbide, and gallium nitride. The textured substrate comprises a base having a generally planar main top surface from which upwardly extends a regular array of posts, the base being formed of single crystal material which is crystallographically compatible with epitaxial single crystal materials to be deposited thereon. The single crystal epitaxial layers are formed on top surfaces of the posts which preferably have a quardrilateral cross-section, e.g., a square cross-section whose sides are from about 0.5 to about 20 micrometers in length, to accommodate the formation of substantially defect-free, single crystal epitaxial layers thereon. The single crystal epitaxial layer may be selectively doped to provide for p-type and p.sup.
    Type: Grant
    Filed: November 1, 1990
    Date of Patent: July 9, 1991
    Assignee: Advanced Technolgy Materials, Inc.
    Inventor: Charles P. Beetz, Jr.
  • Patent number: 5030589
    Abstract: A production method of a semiconductor device includes a first process for producing a gate electrode pattern of double layer structure on a semiconductor substrate, which gate electrode pattern comprises a first layer and a second upper heat-resistant material layers each having different etching property, a second process for plating a resist film on the entire surface of the substrate and etching the same to expose the top portion of the second upper heat-resistant material layer, a third process for removing the second upper heat-resistant material layer, a fourth process for hardening the surface of the resist and conducting over development of the resist, and a fifth process for plating a low resistance metal material on the entire surface of the substrate and removing the low resistance metal material together with the resist film by lift-off method, thereby to produce a gate electrode comprising the first lower heat-resistant material layer and a low resistance metal layer which is produced thereon, w
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: July 9, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Minoru Noda
  • Patent number: 5019530
    Abstract: A method and structures are described for fabricating junctions having metal electrodes separated by polycrystalline barriers with arbitrarily-chosen but controlled barrier height and shape is accomplished by varying the composition and doping of polycrystalline multinary compound semiconductor materials in the barrier, hence varying the Fermi level pinning position such that the Fermi level is fixed and controlled at and everywhere in between the two metal-insulator interfaces. It is known that Schottky barrier heights at metal/compound semiconductor interfaces are determined by a Fermi level pinning mechanism rather than by the electronic properties of the applied metallurgy. The present invention exploits the knowledge that the same type of Fermi level pinning occurs at semiconductor dislocations and grain boundaries. The present invention uses polycrystalline compound semiconductor alloys in which the pinning position is varied over a large range in metal/semiconductor structures.
    Type: Grant
    Filed: April 20, 1990
    Date of Patent: May 28, 1991
    Assignee: International Business Machines Corporation
    Inventors: Alan W. Kleinsasser, Jerry M. Woodall
  • Patent number: 5006483
    Abstract: A gallium arsenide diode is disclosed which has a very thin resistive layer of a metal oxide, typically titanium oxide, formed annularly on a semiconductor substrate across the exposed annular periphery of a p-n junction. The titanium oxide layer has a sheet resistance of not less than 10 kilohms per square and creates a Schottky barrier between itself and the neighboring n type region of the substrate. The titanium oxide layer can be formed by first vacuum depositing titanium on the substrate and then heating the titanium layer.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: April 9, 1991
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Koji Ohtsuka, Hirokazu Goto
  • Patent number: 4963501
    Abstract: Methods for reducing linewidths of Field Effect Transistors (FETs) and making FETs with 0.5 to 0.15 .mu.m effective gate lengths are used separately or in a combined process sequence, that combines enhancement/depletion mode and microwave Metal-Semiconductors FETs (MESFETs) on the same GaAs chip. Photoresist linewidths are used to form dummy or substitutional gates using optical lithography with no deliberate overexposures. The dummy gate may be used as a mask for N+ implantation. The photoresist linewidth is then reduced in its lateral basewidth while preserving its height to basewidth aspect ratio in an isotropic oxygen plasma etch. A nonconformal dielectric film of silicon monoxide is deposited over the photoresist linewidth patterns. Dielectric reverse liftoff of the SiO pattern transfer dielectric provides a self-aligned stencil mask with respect to the N+/N- interfaces. The SiO stencil is also a dielectric spacer with respect to the N+/N- interfaces.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: October 16, 1990
    Assignee: Rockwell International Corporation
    Inventors: Frank J. Ryan, James W. Penney, Aditya K. Gupta
  • Patent number: 4946803
    Abstract: A Schottky-type diode is fabricated by a process that enables the diodes conductor-to-semiconductor barrier height .phi..sub.B to be controlled by adjusting the thickness of a metal silicide layer (22) which forms a rectifying junction (20) with an N-type semiconductor (24). In fabricating one version of the diode, a metallic layer (70) consisting of two or more metals such as platinum and nickel is deposited on an N-type silicon semiconductor (68) and heated to create a metal silicide layer (72) consisting of a lower layer (62) and an upper layer (74) of different average composition. A portion of the upper layer is then removed, allowing .phi..sub.B to be adjusted suitably.
    Type: Grant
    Filed: December 8, 1988
    Date of Patent: August 7, 1990
    Assignee: North American Philips Corp., Signetics Division
    Inventor: Russell C. Ellwanger
  • Patent number: 4923827
    Abstract: On a semiconductor substrate (38) T-type undercut electrical contact structure (12, 36) and methodology provides a diffusion barrier (26, 40) preventing migration therethrough from a gold layer (30, 48) along the sides of an undercut schottky metal lower layer (28, 44) into the active region of the semiconductor substrate. In one embodiment, the diffusion barrier (26) is provided at the base of the gold layer (30). In another embodiment, the gold layer (48) is encapsulated by the diffusion barrier (40) on the bottom (46) and sides (56). The diffusion barrier base layer is deposited. The diffusion barrier side layers are electroplated with the remaining portions of the contact structure being masked by selective oxidation.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: May 8, 1990
    Assignee: Eaton Corporation
    Inventors: Joseph A. Calviello, Paul R. Bie, David Ward
  • Patent number: 4889827
    Abstract: A method for the manufacture of a MESFET comprising a gate that is self-aligned both with respect to the source and drain regions as well as with respect to the appertaining metallizations, whereby a first metal layer (21), a first dielectric layer (31), and a first lacquer mask layer are applied following doping of the carrier substrate. A trench producing an outer recess in the doping layer (11) is formed by anisotropic etching. A second dielectric layer is isotropically deposited and is anisotropically re-etched except for spacers (51/52) whereby an inner recess (double recess) is produced in the doping layer and, finally, the gate metal (22) is applied.
    Type: Grant
    Filed: September 22, 1988
    Date of Patent: December 26, 1989
    Assignee: Siemens Aktiengesellschaft
    Inventor: Josef Willer
  • Patent number: 4855246
    Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region.
    Type: Grant
    Filed: September 21, 1988
    Date of Patent: August 8, 1989
    Assignee: International Business Machines Corporation
    Inventors: Christopher F. Codella, Seiki Ogura
  • Patent number: 4853339
    Abstract: In a process of preparing an infrared sensitive photodiode comprising the eps of(1) forming by vacuum deposition an epitaxial layer of a semiconductor alloy material selected from the group consisting of PbS, PbSe, PbTe, PbS.sub.x Se.sub.1-x, PbS.sub.x Te.sub.1-x, PbSe.sub.x Te.sub.1-x, Pb.sub.y Sn.sub.1-y S, Pb.sub.y Sn.sub.1-y Se, Pb.sub.y Sn.sub.1-y Te, Pb.sub.y Sn.sub.1-y S.sub.x, Pb.sub.y Sn.sub.1-y S.sub.x Te.sub.1-x, Pb.sub.y Sn.sub.1-y Se.sub.x Te.sub.1-x, Pb.sub.z Cd.sub.1-z S, Pb.sub.z Cd.sub.1-z Se, Pb.sub.z Cd.sub.1-z Te, Pb.sub.z Cd.sub.1-z S.sub.x Se.sub.1-x, Pb.sub.z Cd.sub.1-z S.sub.x Te.sub.1-x, and Pb.sub.z Cd.sub.1-z Se.sub.x Te.sub.
    Type: Grant
    Filed: July 27, 1988
    Date of Patent: August 1, 1989
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Tak-Kin Chu, Francisco Santiago
  • Patent number: 4833042
    Abstract: The invention is a layered nonalloyed ohmic contact structure for use on n type gallium arsenide including a layer of germanium or silicon of the order of 10 .ANG. thick evaporated onto the gallium arsenide; a diffusion barrier layer of material 100-200 .ANG. thick over the germanium or silicon selected from non-metallic conducting compounds, including metal compounds ofarsenidephosphidecarbideboridenitridesilicideand non-metallic conducting elements; with the diffusion barrier layer material characterized by resistivity of the order of 1 ohm cm or less; and a conducting metal overlayer on the diffusion barrier layer. The invention includes the method for manufacturing the contact structure.
    Type: Grant
    Filed: January 27, 1988
    Date of Patent: May 23, 1989
    Assignee: Rockwell International Corporation
    Inventors: James R. Waldrop, Ronald W. Grant
  • Patent number: 4792531
    Abstract: Disclosed is a process for producing a field effect transistor to provide a uniformity of spacing between the gate and drain as well as the gate and source.
    Type: Grant
    Filed: October 5, 1987
    Date of Patent: December 20, 1988
    Assignee: Menlo Industries, Inc.
    Inventor: Sanehiko Kakihana
  • Patent number: 4791031
    Abstract: In a lead frame for an IC which is provided on a wire bonding part of the inner lead unit thereof with an aluminum coating, possible detrimental diffusion of the component elements of the lead frame into the aluminum coating can be effectively precluded by having a layer of a high melting point metal interposed between the lead substrate and the aluminum coating in the wire bonding part without appreciably increasing the cost of production.
    Type: Grant
    Filed: October 28, 1987
    Date of Patent: December 13, 1988
    Assignee: Sumitomo Metal Mining Co. Ltd.
    Inventor: Hideyasu Nikaido
  • Patent number: 4783379
    Abstract: The present invention provides a film comprising alternate layers of a metal such as zirconium and silicon. The film has a critical temperature at which the film can undergo explosive crystallization. The film undergoes explosive crystallization upon subjecting the film to an energy impulse at temperature equal to or greater than the critical temperature.
    Type: Grant
    Filed: April 17, 1987
    Date of Patent: November 8, 1988
    Assignee: Tosoh SMD, Inc.
    Inventors: Charles E. Wickersham, John E. Poole
  • Patent number: 4774204
    Abstract: A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the step of first forming bipolar MOS regions and then forming gate electrodes in the MOS regions and poly emitters in the bipolar regions. The gate electrodes and bipolar regions have a layer of refractory metal formed on the upper surface thereof and covered by a protective cap. The extrinsic bases formed on either side of the emitter electrode and the source/drain regions are formed on either side of the gate electrode by forming a layer of silicide and implanting the layer of silicide with p-type impurities which are subsequently driven downward into the substrate. The protective cap prevents the p-type impurities from being introduced into the poly emitter.
    Type: Grant
    Filed: June 2, 1987
    Date of Patent: September 27, 1988
    Assignee: Texas Instruments Incorporated
    Inventor: Robert H. Havemann
  • Patent number: 4769337
    Abstract: A method of manufacturing a semiconductor device, comprises the process of forming first and second well regions, which are of N-type and P-type, respectively, in a silicon body, forming a base layer of P-type in the first well region, forming an emitter layer of N-type in the base layer, forming source and drain layers of N-type in the second well region, forming a polysilicon emitter electrode on the emitter layer, and ion-implanting impurities of N-type into an interface between the emitter layer and the emitter electrode, so as to break down an insulative layer at the interface.
    Type: Grant
    Filed: May 8, 1987
    Date of Patent: September 6, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Maeda
  • Patent number: 4753899
    Abstract: The invention relates to a process for the fabrication of a field-effect transistor as described in German Patent Application No. P 35 35 002.4, corresponding to U.S. application Ser. No. 06/914,540 comprises first covering a semiconductor member with a layer which forms the channel region and part of which is covered with a passivation layer. Impurities are implanted into the exposed regions of the semiconductor surface and form underneath the channel region highly doped source and drain regions. A surface layer of the passivation layer is then removed in a section adjacent to the source region and a gate electrode is formed on the thus exposed narrow area of the channel region.
    Type: Grant
    Filed: January 15, 1987
    Date of Patent: June 28, 1988
    Assignee: Telefunken electronic GmbH
    Inventor: Alexander Colquhoun
  • Patent number: 4745082
    Abstract: A process for producing a semiconductor device includes depositing a layer of insulator material onto a supporting substrate of the type having a surface which includes a channel region below the surface thereof containing a carrier concentration of a desired conductivity type, removing selected portions of the insulator material to form a substitutional gate on the substrate surface, forming side walls bounding substitutional gate to define an effective masking area in cooperation with the substitutional gate, ion implanting a dopant into the unmasked region of the substrate, removing the side walls, annealing the resultant device, removing the substitutional gate, depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate, and depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device.
    Type: Grant
    Filed: June 12, 1986
    Date of Patent: May 17, 1988
    Assignee: Ford Microelectronics, Inc.
    Inventor: Siang P. Kwok
  • Patent number: 4735913
    Abstract: A self-aligned process for fabricating a GaAs semiconductor MESFET by depositing a layer of tungsten over the GaAs substrate, and ion implanting the substrate to provide channel doping. A gate composed of a conductive refractory material is deposited and delineated on the tungsten layer, and source and drain regions are formed in the substrate using the gate as a mask. The resulting device is annealed and contacts are formed to the source and drain regions, and to the gate.
    Type: Grant
    Filed: May 6, 1986
    Date of Patent: April 5, 1988
    Assignee: Bell Communications Research, Inc.
    Inventor: John R. Hayes
  • Patent number: 4704367
    Abstract: A technique for suppressing hillock growth in metal films on integrated circuits through multiple thermal cycles by argon implantation. Although it was known that ion implantation of many species such as arsenic suppressed the growth of hillocks in metal films through one thermal cycle, it was discovered that only one of the proposed ions, argon, would suppress hillock formation for multiple subsequent thermal cycles. For the other species, hillock formation would reoccur after multiple cycles. This characteristic is important for double layer metal (DLM) processes to prevent interlayer shorting.
    Type: Grant
    Filed: April 21, 1986
    Date of Patent: November 3, 1987
    Inventors: John R. Alvis, Orin W. Holland
  • Patent number: 4700465
    Abstract: A semiconductor structure with ohmic contacts and variable resistance contacts has an interconnection pattern to the contacts including a first barrier metal in contact with the variable resistance contacts and a second metal contacting the barrier metal and the ohmic contacts. The barrier layer protects the amorphotized crystalline structure of the variable resistance contacts. Fabrication processes are described.
    Type: Grant
    Filed: February 25, 1986
    Date of Patent: October 20, 1987
    Assignee: Zoran Corporation
    Inventor: Eric R. Sirkin
  • Patent number: 4692991
    Abstract: During the deposition of a metallic layer on an N-type semiconductive region to form a Schottky diode in a structure placed in a highly evacuated chamber, at least one selected gas is introduced into the chamber to control the forward voltage across the diode.
    Type: Grant
    Filed: July 19, 1985
    Date of Patent: September 15, 1987
    Assignee: Signetics Corporation
    Inventor: Ronald C. Flowers
  • Patent number: 4692190
    Abstract: Semiconductor body is prepared and a film is formed on the semiconductor body, followed by forming an interconnection layer of aluminum alloy on the insulating film. A silicon oxide film is formed on the interconnection layer, followed by removing that portion of the silicon oxide film which is situated on a predetermined trimming area of the interconnection layer. A silicon nitride film is formed on the whole surface of the resultant structure. An energy beam is directed onto the predetermined trimming area of the interconnection layer, causing the interconnection layer to be locally heated to 400.degree. to 600.degree. C. whereby atoms in the interconnection layer migrate to permit the interconnection layer to be trimmed.
    Type: Grant
    Filed: December 24, 1985
    Date of Patent: September 8, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeru Komatsu