Abstract: In a metal oxide semiconductor field effect transistor fabrication process, refractory metal is deposited over designated source and drain areas within a silicon substrate. Refractory metal and silicon at the interface is then mixed by ion implantation of a heavy neutral ion species such as germanium. To minimize source/drain junction depth, the source and drain locations can be subjected to bombardment by a lighter ion such as silicon which amorphizes silicon to a predetermined depth under the designated source and drain regions and so substantially confines dopant diffusion to the silicon amorphized region. To render the source and drain of desired conductivity type, an ion implantation of a non-neutral ion is then performed.

Abstract: Particularly for use in MOS (metal-oxide-semiconductor) VLSI (very large scale integrated) circuits, an aluminum conductor coated with a layer of refractory metal or refractory metal silicide has the advantages of being resistant both to electromigration and to hillock growth. By this invention, to reduce the resistivity of this composite conductor and to eliminate hillock formation, the conductor is subjected to an ion implantation step to cause interface mixing between the aluminum and the adjacent refractory metal or refractory metal silicide.

Abstract: A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.

Abstract: An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to coupled the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a gate electrode on a silicon substrate of a p-conductivity type and source and in the drain regions of an n-conductivity type substrate so as to interpose the gate electrode therebetween; depositing silicon on the source and drain regions to form a polysilicon wiring layer; and ion-implanting an impurity to an interface between the source and drain regions and the polysilicon wiring layer at acceleration voltage of 40 keV and a dose of 5.times.10.sup.15 cm.sup.-2 to mechanically break down an oxide film formed at said interface.

Abstract: A method for generating an area of increased conductivity on the surface of a body of dielectric material, such as for the purpose of attaching electrodes or other electrical interconnections to the area includes the steps of enclosing the surface within a reducing atmosphere and irradiating the portion of the surface corresponding to the desired conductive area with laser radiation for a selected period of time. The atmosphere may be a hydrogen atmosphere at a pressure in the range of 0-1000 HPa. Additionally, the surface may be preheated prior to irradiation.

Abstract: A method of forming a semiconductor device having a non-alloyed contact layer. An active region is formed in a substrate and the non-alloyed contact layer is formed in the active region, the barrier height of source and drain electrodes for the non-alloyed contact layer being lower than the barrier height of the source and drain electrodes for the active region or the substrate. The preferred method of forming the non-alloyed contact layer is high dose implantation of an element selected in accordance with the substrate material. For example, if the substrate is GaAs the non-alloyed contact layer is formed by implanting In, and if the substrate is InP the non-alloyed contact layer is formed by implanting As or Sb.

Abstract: A method for manufacturing VLSI MOS-transistor circuits involving the production of transistors by means of a spacer layer technique and ohmic contacts from the gate interconnect to the diffused regions of the substrate (thus providing buried contacts) both being simultaneously generated. Contact holes are provided at the desired location in the substrate before the deposition of the spacer layer occurs across the surface of the substrate. The spacer layer is simultaneously structured at the side walls of the gates and at the side walls of the interconnects which serve as connections. The contact hole region is doped at the same time as the source/drain areas are provided by ion implantation. The combined manufacture of transistors using spacer technology and buried contacts makes it possible to manufacture MOS logic circuits and memory circuits with voltage stable transistors in high packing density.

Abstract: High transconductance is obtained in GaAs FET's by forming a channel layer having a carrier concentration monotonously decreasing from the interface of the channel layer and a control gate toward the interface of the channel layer and the substrate it is formed in. This is established by ion implantation of the channel layer through an insulating layer, preferably an AlN layer, on a GaAs substrate. An AlN layer is preferable since it has no adverse effects on the GaAs substrate during ion implantation and the following heat treatment, allowing higher uniformity of the threshold voltages of the FET's.

Abstract: A Schottky diode and method of making same in which a n+ doped layer, an n oped layer and an undoped layer of a semi-insulating material selected from the group consisting of gallium arsenide, aluminum gallium arsenide and indium phosphide is grown consecutively on a semi-insulating substrate made of the same material. A mesa with acute angled sides is etched on the undoped layer to such a depth that the n doped layer is exposed. A Schottky and ohmic contact are then deposited on opposite sides of the mesa. The exposed n layer is then bombarded with protons at normal incidence.

Abstract: An improved Schottky barrier device and method of manufacture is disclosed. The device has a semiconductor layer of first conductivity type; an insulating layer covering one face of the semiconductor layer, and has an opening therein. A conductor layer covers the semiconductor layer where the semiconductor layer is exposed by the opening and there forms a recitifying junction with the semiconductor layer. A first region of opposite conductivity type is at the one face of semiconductor layer and extends from where the conductor layer meets the insulating layer and below the conductor layer. A second region of opposite conductivity type is at the one face of semiconductor layer and begins where the conductor layer meets the insulating layer and extending below the insulating layer.

Abstract: A method of improving film adhesion during the fabrication of thin film integrated circuits is disclosed. The method includes the steps of depositing a metallic silicide on a substrate and then implanting selected ions at predetermined doses and energies into the silicide layer, whereby tensile stress generated during fabrication processes is reduced. In one embodiment of the invention, the substrate is provided with a polycrystalline silicon layer and the silicide is of the structure MSi.sub.x, where M is a refractory metal and x is greater than 2. Preferred doses range from 10.sup.15 to 10.sup.17 cm.sup.-2, while preferred energies range from 40 to 150 keV.

Abstract: A method of producing a bipolar transistor which includes forming a base region, forming a high-melting-point metal layer of a base electrode on the base region, forming a first insulating layer on the metal layer, and selectively etching the first insulating layer and the metal layer to form an opening. The method further includes forming a second insulating layer on the sides of the first insulating layer and the metal layer within the opening, the second insulating layer defining an emitter-providing region. Impurities are introduced into the base region by using the second insulating layer as a mask to form an emitter region. An emitter electrode and the base electrode are arranged in a similar multilayer structure.

Abstract: A method of fabricating a Schottky barrier MOSFET wherein a polysilicon gate chip is disposed adjacent the drain and source regions of a single crystal silicon substrate surface, and a metal is deposited on the top surface of the gate chip and the drain and source regions of the substrate surface by direct reaction of the silicon of the surfaces with a compound of a tungsten or molybdenum. Preferably, the sidewalls of the gate chip are masked during the deposition of metal to avoid the formation of a metal bridge between the gate and drain or the gate and source.

Abstract: An electrode structure for use in semiconductor devices comprising: a semiconductive layer; a conductive layer disposed on one surface of the semiconductive layer; first regions which intervene between the layers and serve as passages for transmitting minority carriers from the semiconductive layer to said conductive layer; and second regions which intervene between said layers and serve as passages for conveying majority carriers between the semiconductive layer and conductive layer, the first and second regions being selectively formed on the semiconductive layer so as to be adjacent to one another.

Abstract: A silicide layer or silicon alloy layer is formed within a surface region of an impurity-doped region on the surface of a semiconductor substrate by implanting and heating any of those metals which can form silicides or silicon alloys with silicon upon heating.The peel of a metallic electrode or wiring can thus be prevented, and the electrode or wiring can be directly formed on the semiconductor substrate.

Abstract: A method of manufacturing a GaAs compound semiconductor device is disclosed. The method comprises steps of applying a Ge film on an n+ region for forming ohmic electrode thereon, injecting impurity ion into the Ge film with high concentration, applying metal of high melting point overall surface of the semiconductor body to an annealing treatment after final ion implantation step.

Abstract: A TUNNETT (tunneling transit time) electronic device comprising a very thin injector uniformly doped at a high concentration, a thin drift region of lower doping of the same semiconductivity type, and a collector of high doping of the same semiconductivity type. A Schottky barrier is formed by placing a metal electrode on the injector and an ohmic contact may be made on the collector. In a preferred embodiment the injector is made of Ge grown on the drift region by vacuum epitaxy. The drift region is preferably GaAs grown by epitaxy on a GaAs collector.