Silicon Carbide Patents (Class 148/DIG148)
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Patent number: 5980265Abstract: Stable, high temperature electrical contacts to silicon carbide formed using a unique silicide formation process that employs a sacrificial silicon layer between the silicon carbide and the contacting metal, which forms a metal silicide interlayer providing the resulting contact with low specific contact resistance and high electrical and structural stability. The contact interface is formed by reaction below the semiconductor surface, and thus the in-situ silicide formation process is insensitive to surface impurities and oxides and permits the controlled formation of silicides without the formation of excess carbon and carbides at the contact interface. The silicon layer may optionally be doped in situ during growth or implanted with dopants after growth, to lower the contact resistance and enhance its operational stability.Type: GrantFiled: May 23, 1995Date of Patent: November 9, 1999Assignee: Advanced Technology Materials, Inc.Inventor: Michael A. Tischler
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Patent number: 5958132Abstract: A method for the growth of a SiC single crystal comprisingintroducing a seed crystal of SiC single crystal having an exposed face deviating from the {0001} plane by an angle .alpha..sub.1 of about 60.degree. to about 120.degree., typically about 90.degree. and SiC powder as a raw material into a graphite crucible,elevating the temperature of the SiC powder in an atmosphere of inert gas to a level sufficient for sublimation, meanwhileelevating the temperature of the exposed face of the seed crystal to a level slightly lower than the temperature of the SiC powder, andkeeping the SiC powder and the seed crystal at the specific temperatures for a period enough for a SiC single crystal of the same polytype as the seed crystal to grow to a desired height on the exposed face of the seed crystal.Type: GrantFiled: May 14, 1997Date of Patent: September 28, 1999Assignee: Nippon Steel CorporationInventors: Jun Takahashi, Masatoshi Kanaya, Yuichiro Fujiwara, Noboru Ohtani
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Patent number: 5869390Abstract: Disclosed is a method of forming electrodes on diamond comprising the steps of: forming a mask pattern on diamond or diamond film; performing a treatment of the diamond surface by a plasma of inert gases; forming an electrode film on the whole surface of the specimen; and removing the mask, thereby forming a specified pattern of the electrodes. By this method, it is possible to form electrodes having high adhesion to diamond and diamond film for electronic devices.Type: GrantFiled: June 9, 1997Date of Patent: February 9, 1999Assignee: Kabushiki Kaisha Kobe Seiko ShoInventors: Kozo Nishimura, Koji Kobashi, Shigeaki Miyauchi, Rie Kato, Hisashi Koyama, Kimitsugu Saito
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Patent number: 5846859Abstract: A capacitor in a semiconductor device having a dielectric film formed of high dielectric material and a manufacturing method therefor are provided. The capacitor consists of electrodes including a dielectric film and an amorphous SiC layer. Thus, the diffusion of oxygen atoms through a grain boundary into an underlayer and the formation of an oxide layer on the surface of the SiC layer can both be prevented, providing for a highly reliable capacitor electrode and an equivalent oxide thickness which is no thicker than required.Type: GrantFiled: February 23, 1996Date of Patent: December 8, 1998Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-in Lee
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Patent number: 5814546Abstract: A method for producing a bipolar semiconductor device having a first layer doped according to a first doping type, the first layer being adapted to have minority charge carriers injected thereinto from a second layer of the device of a doping type opposite to that of the first layer in a forward conducting state of the device, comprises the steps of a) epitaxially growing the first layer and b) providing at least one region of the first layer with the minority charge carriers having a lifetime lower than in other parts of the first layer, the lower lifetime region of the first layer being formed directly during the epitaxial growth of this region by changing composition of substances fed to the first layer for the growth thereof when the region is grown.Type: GrantFiled: November 1, 1996Date of Patent: September 29, 1998Assignee: ABB Research Ltd.Inventor: Willy Hermansson
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Patent number: 5759908Abstract: A method is disclosed for forming crystalline silicon carbide (SiC) semiconductors on a semiconductor-on-insulator (SOI) structure. In this method, the thin silicon layer of an SOI substrate is converted to silicon carbide using a carbonization reaction. The SiC layer is then, optionally, further increased in thickness using a vapor deposition reaction, preferably using a silicon-containing cyclobutane gas. Rather than increasing the thickness of the SiC layer, the vapor deposition process can also be used to deposit a layer of another semiconductor (e.g., a III-N or III-P semiconductor) on the thin SiC layer. The products made by this process are also claimed.Type: GrantFiled: May 16, 1995Date of Patent: June 2, 1998Assignee: University of CincinnatiInventors: Andrew J. Steckl, Chong Yuan
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Patent number: 5670414Abstract: The present invention relates to a graded-gap process for forming a SiC/Si heterojunction electrical element and includes steps of a) provide a Si substrate; b) introduce a hydrogen containing gas stream to the Si substrate; c) introduce a silane-containing gas stream of a constant flow rate to the Si substrate for reacting with the hydrogen-containing gas stream for a first period of time; d) introduce an alkanes-containing gas stream of a gradually changing flow rate to the Si substrate for reacting with the hydrogen- containing gas stream and the silane-containing gas stream to grow a SiC layer on the Si substrate for a second period of time; and e) introduce the alkanes-containing gas stream at a constant flow rate for reacting with the hydrogen-containing gas stream and the silane-containing gas stream for a third period of time. Such process can grow an excellent graded band-gap SiC/Si heterojunction diode with low cost.Type: GrantFiled: February 6, 1996Date of Patent: September 23, 1997Assignee: National Science CouncilInventors: Y. K. Fang, J. D. Hwang
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Patent number: 5612260Abstract: A method of obtaining high quality passivation layers on silicon carbide surfaces by oxidizing a sacrificial layer of a silicon-containing material on a silicon carbide portion of a device structure to substantially consume the sacrificial layer to produce an oxide passivation layer on the silicon carbide portion that is substantially free of dopants that would otherwise degrade the electrical integrity of the oxide layer.Type: GrantFiled: December 9, 1994Date of Patent: March 18, 1997Assignee: Cree Research, Inc.Inventor: John W. Palmour
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Patent number: 5611955Abstract: A substrate for use in semiconductor devices, fabricated of silicon carbide and having a resistivity of greater than 1500 Ohm-cm. The substrate being characterized as having deep level impurities incorporated therein, wherein the deep level elemental impurity comprises one of a selected heavy metal, hydrogen, chlorine and fluorine. The selected heavy metal being a metal found in periodic groups IIIB, IVB, VB, VIB, VIIB, VIIIB, IB and IIB.Type: GrantFiled: October 18, 1993Date of Patent: March 18, 1997Assignee: Northrop Grumman Corp.Inventors: Donovan L. Barrett, Hudson M. Hobgood, James P. McHugh, Richard H. Hopkins
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Patent number: 5604135Abstract: A light emitting diode is disclosed that emits in the green portion of the visible spectrum, along with a method of producing the diode. The light emitting diode comprises a 6H silicon carbide substrate having a planar surface inclined more than one degree off axis toward one of the <11 20> directions; an ohmic contact to the substrate; a first epitaxial layer of 6H silicon carbide on the inclined surface of the substrate and having a first conductivity type; a second epitaxial layer of 6H silicon carbide on the first layer and having the opposite conductivity type for forming a p-n junction between the first and second layers; and an ohmic contact to the second epitaxial layer. The diode produces a peak wavelength of between about 525 and 535 nanometers with a spectral half width of no more than about 90 nanometers.Type: GrantFiled: August 12, 1994Date of Patent: February 18, 1997Assignee: Cree Research, Inc.Inventors: John A. Edmond, Alexander V. Suvorov
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Patent number: 5597744Abstract: Electrodes 16a and 16b composed of metal nitride made of either one of TiN, ZrN, HfN, VN and TaN are formed on an N-type source region 12 and drain region 13 of a P-type SiC substrate 11, respectively, Nitrogen-rich layers 12a and 13a are formed in surface layer portions of the regions 12 and 13 which the electrodes composed of metal nitride 16a and 16b contact respectively. The nitrogen-rich layer allows the contact resistivity of the electrode to be made small, A metal nitride composed of either one of TiN, ZrN, HfN, VN and TaN is interposed between a gate electrode 15 of Mo and an interconnection of Al 17c to prevent the reaction of the gate electrode and the interconnection.Type: GrantFiled: August 17, 1995Date of Patent: January 28, 1997Assignees: Mitsubishi Materials Corporation, Research Institute of Innovative Technology for the EarthInventors: Eiji Kamiyama, Kazuhiro Fusegawa, Nosho Toyama
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Patent number: 5585304Abstract: A semiconductor wafer is comprised of a transparent layer interposed between a thin silicon layer and a thick silicon layer. Silicon islands are formed from the thin silicon layer on the transparent layer. Device elements are formed in the silicon islands. Thereafter, the thick silicon layer which is a support layer is etched away to form a transparent region on the wafer. The wafer is constructed to avoid elimination or destruction of the transparent layer during the course of formation of the silicon islands and during the course of etching of the rear thick silicon plate. The transparent layer is comprised of a silicon nitride film or a silicon carbide film. Alternatively, the transparent layer is comprised of a silicon oxide film covered by a silicon nitride film or a silicon carbide film on one or both of the upper and lower faces of the silicon oxide film.Type: GrantFiled: August 2, 1994Date of Patent: December 17, 1996Assignees: Agency Industrial Science, Seiko Instruments Inc.Inventors: Yutaka Hayashi, Kunihiro Takahashi, Hiroaki Takasu, Yoshikazu Kojima, Hitoshi Niwa, Nobuyoshi Matsuyama, Yomoyuki Yoshino, Masaaki Kamiya
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Patent number: 5529949Abstract: Thin films of 2H .alpha.-silicon carbide are produced by pulsed laser ablation.Type: GrantFiled: March 17, 1994Date of Patent: June 25, 1996Assignee: Kent State UniversityInventors: Mark A. Stan, Martin O. Patton, Joseph D. Warner
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Patent number: 5501173Abstract: A method for epitaxially growing a-axis .alpha.-SiC on an a-axis substrate is provided. A section is formed from the SiC crystal by making a pair of parallel cuts in the crystal. Each of these cuts is parallel to the c-axis of the crystal. The resulting section formed from the crystal has opposing a-face surfaces parallel to the c-axis of the crystal. A gas mixture having hydrocarbon and silane is passed over one of the a-face surfaces of the section. The hydrocarbon and silane react on this a-face surface to form an epitaxial layer of SiC. Preferably, the SiC is grown at a temperature of approximately 1450.degree. C.Type: GrantFiled: October 18, 1993Date of Patent: March 26, 1996Assignee: Westinghouse Electric CorporationInventors: Albert A. Burk, Jr., Donovan L. Barrett, Hudson M. Hobgood, Rowland C. Clarke, Graeme W. Eldridge, Charles D. Brandt
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Patent number: 5441011Abstract: A method of growing a first SiC single crystal on a seed crystal including a second SiC single crystal, comprises the steps of setting a SiC source material at an initial temperature, growing the first SiC single crystal on the seed crystal including the second SiC single crystal at a temperature lower than the initial temperature of the source material and gradually decreasing the source material temperature from the initial temperature during at least a predetermined period during the growing step.Type: GrantFiled: March 15, 1994Date of Patent: August 15, 1995Assignee: Nippon Steel CorporationInventors: Jun Takahaski, Masatoshi Kanaya
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Patent number: 5441911Abstract: A silicon carbide structure (10) and method capable of using existing silicon wafer fabrication facilities. A silicon wafer (20) is provided which has a first diameter. At least one silicon carbide wafer (30) is provided which has a given width and length (or diameter). The width and length (or diameter) of the silicon carbide wafer (30) are smaller than the diameter of the silicon wafer (20). The silicon wafer (20) and the silicon carbide wafer (30) are then bonded together. The bonding layer (58) may comprise silicon germanium, silicon dioxide, silicate glass or other materials. Structures such as MOSFET (62) may be then formed in silicon carbide wafer (30).Type: GrantFiled: June 21, 1994Date of Patent: August 15, 1995Assignee: Texas Instruments IncorporatedInventor: Satwinder Malhi
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Patent number: 5436174Abstract: A trench is formed in a monocrystalline silicon carbide substrate by amorphizing a portion of the monocrystalline silicon carbide substrate to define an amorphous silicon carbide region therein. The amorphous silicon carbide region is then removed, to produce a trench in the monocrystalline silicon carbide substrate corresponding to the removed amorphous silicon carbide region. The substrate may be amorphized by implanting ions into a masked substrate so that the implanted ions convert the unmasked portions of the substrate into amorphous silicon carbide. The amorphous silicon carbide may be etched using at least one etchant which etches amorphous silicon carbide relatively quickly and etches monocrystalline silicon carbide relatively slowly, such as hydrofluoric acid and nitric acid. The amorphizing and removing steps may be repeatedly performed to form deep trenches.Type: GrantFiled: January 25, 1993Date of Patent: July 25, 1995Assignee: North Carolina State UniversityInventors: Bantval J. Baliga, Dev Alok
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Patent number: 5409859Abstract: A method and resulting ohmic contact structure between a high work function metal and a wide bandgap semiconductor for which the work function of the metal would ordinarily be insufficient to form an ohmic contact between the metal and the semiconductor. The structure can withstand annealing while retaining ohmic characteristics. The ohmic contact structure comprises a portion of single crystal wide bandgap semiconductor material; a contact formed of a high work function metal on the semiconductor portion; and a layer of doped p-type semiconductor material between the single crystal portion and the metal contact. The doped layer has a sufficient concentration of p-type dopant to provide ohmic behavior between the metal and the semiconductor material.Type: GrantFiled: April 22, 1994Date of Patent: April 25, 1995Assignees: Cree Research, Inc., North Carolina State UniversityInventors: Robert C. Glass, John W. Palmour, Robert F. Davis, Lisa S. Porter
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Patent number: 5397717Abstract: A silicon carbide vertical MOSFET formed on a silicon carbide substrate with portions of epitaxial layers defining the various transistor electrodes, rather than defining the electrodes with implants and diffusion. An opening is formed in some of the epitaxial layers and a conductive layer is formed therein to electrically connect a drain contact on the rear of the substrate to the components on the front of the substrate.Type: GrantFiled: July 12, 1993Date of Patent: March 14, 1995Assignee: Motorola, Inc.Inventors: Kenneth L. Davis, Charles E. Weitzel, Neal J. Mellen
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Patent number: 5385855Abstract: A depletion mode MOSFET and resistor are fabricated as a silicon carbide (SiC) integrated circuit (IC). The SiC IC includes a first SiC layer doped to a first conductivity type and a second SiC layer overlaid on the first SiC layer and doped to a second conductivity type. The second SiC layer includes at least four more heavily doped regions of the second conductivity type, with two of such regions comprising MOSFET source and drain electrodes and two other of such regions comprising resistor electrodes. The second SiC layer includes an isolation trench between the MOSFET electrodes and the resistor electrodes. At least two electrically conductive contacts are provided as MOSFET electrode contacts, each being positioned over at least a portion of a respective MOSFET electrode and two other electrically conductive contacts are provided as resistor electrode contacts, each being positioned over at least a portion of a respective resistor electrode.Type: GrantFiled: February 24, 1994Date of Patent: January 31, 1995Assignee: General Electric CompanyInventors: Dale M. Brown, Gerald J. Michon, Vikram B. Krishnamurthy, James W. Kretchmer
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Patent number: 5384270Abstract: In a method of producing a silicon carbide MOSFET, a predetermined conductivity type region having a predetermined depth is formed in an SiC layer through ion injection and heat treatment activation by utilizing the fact that the range of impurity ions at the time of ion injection can be controlled by an acceleration voltage to thereby avoid a disadvantage of an SiC crystal in which diffusion of impurity is hardly generated. For example, ions are injected into an n-type SiC semiconductor layer by using, as a mask, a gate electrode having an inclined surface at its end surface to thereby form a p-type region having a curved surface in an interface. Alternatively, a part of a p-type SiC epitaxial layer on an n-type SiC substrate is left as a p-type base layer, and an n-type region is formed through ion injection and connected to a substrate portion under the n-type region to thereby form an n-type base region.Type: GrantFiled: November 10, 1993Date of Patent: January 24, 1995Assignee: Fuji Electric Co., Ltd.Inventor: Katsunori Ueno
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Patent number: 5363800Abstract: This invention is a method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.Type: GrantFiled: November 9, 1992Date of Patent: November 15, 1994Assignee: The United States of America as represented by the United States National Aeronautics and Space AdministrationInventors: David J. Larkin, Powell, J. Anthony
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Patent number: 5350699Abstract: A hetero-junction bi-polar transistor provided with a collector composed of a .beta. - SiC substrate and a base area composed of a .beta. - SiC layer and an emitter area composed of an .alpha. - SiC layer, thereby forming a hetero-junction bi-polar transistor having superior heat resistance.Type: GrantFiled: May 11, 1993Date of Patent: September 27, 1994Assignee: Rohm Co., Ltd.Inventor: Keita Nii
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Patent number: 5322802Abstract: A silicon carbide field effect transfer of the present invention includes a base and source region each formed by a series of amorphizing, implanting and recrystallizing steps. Moreover, the drain, base and source regions extend to a face of a monocrystalline silicon carbide substrate and the source and base regions comprise substantially monocrystalline silicon carbide formed from recrystallized amorphous silicon carbide. The source and base regions also have vertical sidewalls defining the p-n junction between the source/base and base/drain regions, respectively. The vertical orientation of the sidewalls arises from the respective implantation of electrically inactive ions into the substrate during the amorphizing steps for forming the base region in the drain and for forming the source region in the base region. The electrically inactive ions are selected from the group consisting of silicon, hydrogen, neon, helium, carbon and argon.Type: GrantFiled: January 25, 1993Date of Patent: June 21, 1994Assignee: North Carolina State University at RaleighInventors: Bantval J. Baliga, Mohit Bhatnagar
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Patent number: 5279701Abstract: A method for the growth of silicon carbide single crystals is disclosed which includes the step of growing silicon carbide single crystals on a silicon single-crystal substrate. The silicon single-crystal substrate has growth areas with a crystal orientation inclined by an angle .theta. from the [100] direction toward at least one of the [011] and [011] directions and with a lateral dimension d taken along the direction of such inclination toward the [011] or [011] direction. The angle .theta. is set to be in the range of zero to tan.sup.-1 (.sqroot.2/8) degrees (with the proviso that the angle .theta. is not equal to tan.sup.-1 (.sqroot.2/2) degrees). The lateral dimension d is set to be in the range of 0.1 to 100 .mu.m. In this method, the silicon carbide single crystals are grown to a thickness t approximately equal to or greater than (.sqroot.2+tan.theta.)d/.vertline.1-.sqroot.2tan.theta..vertline., so that these silicon carbide single crystals are substantially free of defects such as stacking faults.Type: GrantFiled: August 24, 1992Date of Patent: January 18, 1994Assignee: Sharp Kabushiki KaishaInventors: Mitsuhiro Shigeta, Akira Suzuki, Katsuki Furukawa, Yoshihisa Fujii
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Patent number: 5272096Abstract: A layer of silicon carbide (33, 38, 41) is utilized in forming a bipolar transistor (30, 40). The transistor (30, 40) is formed on a substrate (31, 32) that has a single crystal silicon surface. The layer of silicon carbide (33, 38, 41) is epitaxially formed on the single crystal silicon surface. Thereafter, a layer of silicon (34) is epitaxially formed on the layer of silicon carbide (33, 38, 41). The silicon carbide (33, 38, 41) functions as an active transistor layer or alternately is within the transistor's depletion region.Type: GrantFiled: September 29, 1992Date of Patent: December 21, 1993Assignee: Motorola, Inc.Inventors: Edouard D. de Fresart, Hang M. Liaw
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Patent number: 5270244Abstract: A method for forming an oxide-filled trench in silicon carbide includes the steps of amorphizing a portion of a monocrystalline silicon carbide substrate to thereby define an amorphous silicon carbide region in the substrate and then oxidizing the amorphous region to thereby form an oxide-filled trench in the substrate. Because of the enhanced rate of oxidation in the amorphous region as compared to the rate of oxidation of the surrounding monocrystalline silicon carbide regions at relatively low temperatures, the oxide-filled trench is generally defined by the lateral and vertical dimensions of the amorphous silicon carbide region. The amorphizing step includes the steps of masking an area on the face on the monocrystalline silicon carbide substrate to thereby expose a portion of the substrate wherein the amorphous region is to be formed and then directing ions to the face, such that the ions implant into the exposed portion of the substrate and create an amorphous silicon carbide region therein.Type: GrantFiled: January 25, 1993Date of Patent: December 14, 1993Assignee: North Carolina State University at RaleighInventor: Bantval J. Baliga
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Patent number: 5270252Abstract: Platinum Schottky contacts remaining stable up to 800.degree. C. have been produced. The adhesion of the platinum deposited at slightly elevated temperatures is good. Platinum provides a metallization that is physically rugged and thermally stable. The Schottky contacts are made on B-Silicon carbide.Type: GrantFiled: July 28, 1992Date of Patent: December 14, 1993Assignee: United States of America as represented by the Secretary of the NavyInventor: Nicolas A. Papanicolaou
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Patent number: 5248385Abstract: The invention is a method for growing homoepitaxial films of SiC on low-tilt-angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of (1) preparing the growth surface of SiC wafers slightly off-axis (from less than 0.1.degree. to 6.degree.) from the (0001) plane, (2) subjecting the growth surface to a suitable etch, and then (3) growing the homoepitaxial film using conventional SiC growth techniques.Type: GrantFiled: June 12, 1991Date of Patent: September 28, 1993Assignee: The United States of America, as represented by the Administrator, National Aeronautics and Space AdministrationInventor: J. Anthony Powell
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Patent number: 5230768Abstract: There is provided a method for the production of a silicon carbide single crystal, which includes the steps of: providing a silicon single-crystal substrate having a growth plane with a crystal orientation inclined from the [100] direction toward an off-direction, wherein the crystal orientation is defined by a deviation angle .theta. of 5 to 40 degrees, as measured from the [011] direction toward the [011] direction, and a tilt angle .phi. of 1 to 7 degrees, as measured from the [100] direction toward the off-direction; and growing a silicon carbide single crystal on the substrate.Type: GrantFiled: February 28, 1992Date of Patent: July 27, 1993Assignee: Sharp Kabushiki KaishaInventors: Katsuki Furukawa, Akira Suzuki, Yoshihisa Fujii
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Patent number: 5225032Abstract: Single crystalline, epitaxial, stoichiometric SiC films are deposited on single crystalline silicon substrates by a procedure which involves first treating the surface of the silicon substrate to remove any surface layer of SiO.sub.2, followed by heating the substrate to temperature within the range of from about 600.degree. to about 1000.degree.0 C. and flowing a stream including a gaseous compound of Si, H and C--free of halogen and containing Si and C in 1:1 atomic ratio--over the heated substrate.Type: GrantFiled: August 9, 1991Date of Patent: July 6, 1993Assignee: Allied-Signal Inc.Inventor: Ilan Golecki
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Patent number: 5210051Abstract: The invention is a method of growing intrinsic, substantially undoped single crystal gallium nitride with a donor concentration of 7.times.10.sup.17 cm.sup.-3 or less. The method comprises introducing a source of nitrogen into a reaction chamber containing a growth surface while introducing a source of gallium into the same reaction chamber and while directing nitrogen atoms and gallium atoms to a growth surface upon which gallium nitride will grow.Type: GrantFiled: June 5, 1991Date of Patent: May 11, 1993Assignee: Cree Research, Inc.Inventor: Calvin H. Carter, Jr.
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Patent number: 5200022Type: GrantFiled: October 3, 1990Date of Patent: April 6, 1993Assignee: Cree Research, Inc.Inventors: Hua-Shuang Kong, Calvin H. Carter, Jr.
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Patent number: 5162255Abstract: A protection layer for protecting a silicon dioxide layer formed on a silicon substrate of a semiconductor device. The protection layer protects the silicon dioxide layer from being reacting with a reactant gas used in a chemical vapor deposition method performed for forming a silicon carbide layer. The silicon carbide layer is to be a wide energy band gap emitter layer of the semiconductor device. The protection layer is formed on the silicon dioxide layer, and the silicon carbide layer is formed in an active region formed on the silicon substrate in an aperture provided by etching the protection layer and the silicon dioxide layer. The protection layer is made of material which is non-reactive with the reactant gas consisting of, for example, trichlorosilane and methane. The protection layer is, for example, titanium nitride formed by a sputtering method, or nitrided silicon oxide formed by heating the silicon dioxide layer.Type: GrantFiled: April 27, 1990Date of Patent: November 10, 1992Assignee: Fujitsu LimitedInventors: Takashi Ito, Toshihiro Sugii
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Patent number: 5155062Abstract: A method and apparatus for substantially preventing undesired residual dopants or other impurities from becoming incorporated in growing epitaxial layers of silicon carbide during CVD by avoiding the use of a susceptor for CVD epitaxial growth is disclosed. During the CVD process, the substrate is suspended substantially out of physical contact with any other solid object while a suitable surface of the semiconductor substrate is contacted with source gases that will form epitaxial layers of silicon carbide thereon. Heating during the CVD process is performed, according to the present invention, by inductively heating the substrate using an induction frequency to which the substrate material is sufficiently responsive to heat the substrate to the temperatures required for CVD of silicon carbide.Type: GrantFiled: December 20, 1990Date of Patent: October 13, 1992Assignee: Cree Research, Inc.Inventor: Thomas G. Coleman
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Patent number: 5021103Abstract: A microcrystalline silicon-containing silicon carbide semiconductor film has an optical energy gap of not less than 2.0 eV, and a dark electric conductivity of less than 10.sup.-6 Scm.sup.-1. The Raman scattering light of the microcrystalline silicon-containing silicon carbide semiconductor film, which shows the presence of silicon crystal phase, has a peak in the vicinity of 530 cm.sup.-1. This microcrystalline silicon-containing silicon carbide semiconductor film is formed on a substrate by preparing a mixture gas having a hydrogen dilution rate .gamma., which is the ratio of the partial pressure of hydrogen gas to the sum of the partial pressure of a silicon-containing gas and the partial pressure of a carbon-containing gas, of 30, transmitting microwave of a frequency of not less than 100 MHz into the mixture gas near a substrate with an electric power density of not less than 4.4.times.10.sup.-2, and generating plasma at a temperature of the substrate of not less than 200.degree. C.Type: GrantFiled: May 2, 1990Date of Patent: June 4, 1991Assignees: Nippon Soken, Inc., Nippondenso Co., Ltd., Yoshihiro HamakawaInventors: Yoshihiro Hamakawa, Hiroaki Okamoto, Yutaka Hattori
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Patent number: 5011549Abstract: Device quality monocrystalline Alpha-SiC thin films are epitaxially grown by chemical vapor deposition on Alpha-SiC [0001] substrates prepared off axis.Type: GrantFiled: October 16, 1989Date of Patent: April 30, 1991Assignee: North Carolina State UniversityInventors: Hua-Shuang Kong, Jeffrey T. Glass, Robert F. Davis
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Patent number: 5010035Abstract: A semiconductor device wafer base wherein devices may be fabricated in silicon carbide, the base having a compatible substrate and a beta silicon carbide overlay layer epitaxially related to the substrate, the beta silicon carbide layer being unpolytyped, single crystal, uncracked, without twins, and having integrated circuit quality surface morphology. Preferably, the substrate is a single crystal of titanium carbide, which is the same cubic lattice-type as beta silicon carbide with a lattice parameter different from that of beta silicon carbide by less than about 1%. Additionally, the thermal expansion coefficients of beta silicon carbide and titanium carbide are nearly the same, minimizing the creation of thermal stresses during cooling and heating. The beta silicon carbide is useful in fabricating semi-conductor devices for use at much higher temperatures than is silicon, and for use at high power levels, at high frequencies, and in radiation hardened applications.Type: GrantFiled: May 13, 1988Date of Patent: April 23, 1991Assignee: The Regents of the University of CaliforniaInventors: Rointan F. Bunshah, James D. Parsons, Oscar M. Stafsudd
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Patent number: 4994413Abstract: A method of forming a semiconductor device on a silicon carbide layer comprises steps of introducing an impurity into selected parts of the silicon carbide layer, and oxidizing the silicon carbide layer by annealing in an atmosphere containing oxygen.Type: GrantFiled: October 12, 1989Date of Patent: February 19, 1991Assignee: Fujitsu LimitedInventor: Takashi Eshita
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Patent number: 4983538Abstract: Two methods for fabricating semiconductor substrate having a SOI structure by .beta.-SiC, that is .beta.-SiC on insulator structure, are disclosed. In the first method, two substrates are prepared, the first substrate is silicon coated by SiO.sub.2, the second substrate is silicon on which .beta.-SiC is hereto-epitaxially grown. These substrates are bonded to each other by heating. During the heating process, anodic bonding may be applied. Then, the bonded substrate is ethced or mechanically polished off from the side of the second substrate, to expose the .beta.-SiC layer. In the second method, .beta.-SiC is grown on a silicon substrate. The surface of the substrate is coated with SiO.sub.2, and then, polysilicon or poly-SiC is deposited on the surface of the .beta.-SiC side. The substrate is then etched or mechanically polished from the side of the silicon substrate to expose the .beta.-SiC.Type: GrantFiled: November 16, 1988Date of Patent: January 8, 1991Assignee: Fujitsu LimitedInventor: Hiroshi Gotou
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Patent number: 4980303Abstract: With a trend toward higher operation speed and higher gain of a Bi-MIS semiconductor device, wherein a bipolar transistor and a MIS FET are formed on the same silicon substrate, a wide bandgap material such as silicon carbide or micro-crystalline silicon is utilized as an emitter material of the bipolar transistor and further a gate electrode of the MIS FET is simultaneously formed using the same wide bandgap material. By applying the above method in the manufacturing of the Bi-MIS semiconductor device, a high amplification factor of the bipolar transistor and a high cutoff frequency of the MIS FET thereof can be easily obtained without additional processes.Type: GrantFiled: August 18, 1988Date of Patent: December 25, 1990Assignee: Fujitsu LimitedInventor: Tunenori Yamauchi
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Patent number: 4961165Abstract: A semiconductor memory device includes a semiconductor substrate having source and drain regions each having a conduction type opposite to that of the semiconductor substrate, an insulation film formed on a main surface of the semiconductor substrate having first and second contact windows, and a gate electrode formed on the insulation film so as to be located between the source and drain regions. The semiconductor substrate has a charge barrier layer which has the same conduction type as the semiconductor substrate and which has an impurity concentration higher than that of the semiconductor substrate. The charge barrier layer is formed so that a depth (d.sub.1) of the charge barrier layer located under the gate electrode measured from the main surface of the semiconductor substrate is smaller than a depth (d.sub.2) of the charge barrier layer located under the source and drain regions measured from the main surface of the semiconductor substrate.Type: GrantFiled: November 10, 1988Date of Patent: October 2, 1990Assignee: Fujitsu LimitedInventor: Taiji Ema
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Patent number: 4912063Abstract: Device quality thin films of Beta-SiC are epitaxially grown on substrates of Alpha-Sic.Type: GrantFiled: October 26, 1987Date of Patent: March 27, 1990Assignee: North Carolina State UniversityInventors: Robert F. Davis, Hua-Shuang Kong, Jeffrey T. Glass, Calvin H. Carter, Jr.
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Patent number: 4912064Abstract: Device quality monocrystalline Alpha-SiC thin films are epitaxially grown by chemical vapor deposition on Alpha-SiC [0001] substrates prepared off axis.Type: GrantFiled: October 26, 1987Date of Patent: March 27, 1990Assignee: North Carolina State UniversityInventors: Hua-Shuang Kong, Jeffrey T. Glass, Robert F. Davis
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Patent number: 4865659Abstract: A heteroepitaxial growth method comprising growing a semiconductor single-crystal film on a semiconductor single-crystal substrate with a lattice constant different from that of the semiconductor single-crystal film by chemical vapor deposition, the epitaxial orientation of the semiconductor single-crystal film being inclined at a certain angle with respect to the semiconductor single-crystal substrate.Type: GrantFiled: November 24, 1987Date of Patent: September 12, 1989Assignee: Sharp Kabushiki KaishaInventors: Mitsuhiro Shigeta, Akira Suzuki, Katsuki Furukawa, Yoshihisa Fujii, Akitsugu Hatano, Atsuko Uemoto, Kenji Nakanishi
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Patent number: 4866005Abstract: The present invention is a method of forming large device quality single crystals of silicon carbide. The sublimation process is enhanced by maintaining a constant polytype composition in the source materials, selected size distribution in the source materials, by specific preparation of the growth surface of seed crystals, and by controlling the thermal gradient between the source materials and the seed crystal.Type: GrantFiled: October 26, 1987Date of Patent: September 12, 1989Assignee: North Carolina State UniversityInventors: Robert F. Davis, Calvin H. Carter, Jr., Charles E. Hunter
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Patent number: 4863529Abstract: A thin film single crystal diamond substrate which comprises a base substrate selected from the group consisting of a single crystal silicon substrate and a single crystal GaAs substrate, an intermediate layer consisting of single crystal silicon carbide formed on the base substrate and a thin film of single crystal diamond which is epitaxially grown on the intermediate layer, which can have a large area and be easily and economically produced.Type: GrantFiled: March 8, 1988Date of Patent: September 5, 1989Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takahiro Imai, Naoji Fujimori
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Patent number: 4855254Abstract: A single crystalline silicon carbide (.beta.-SiC) layer having a thickness greater than 1 .mu.m is grown on a silicon substrate by the following method of the present invention. The silicon substrate is provided in a reactor chamber, and the reactor chamber is evacuated and maintained at a reduced atmospheric pressure during the growing processes. While flowing a mixed gas containing acetylene into the reactor chamber, the substrate is heated up at a temperature range from 800.degree. to 1000.degree. C., preferable in a range from 810.degree. to 850.degree. C., whereby a buffer layer of carbonized silicon having a thickness of 60 to 100 .ANG. is grown on the substrate. Thereafter, the flowing gas is changed to a mixed gas containing hydrocarbon and chlorosilane, and the substrate temperature is raised to a temperature from 850.degree. to 950.degree. C. In this process, a single crystalline .beta.-SiC layer can be grown on the buffer layer, and a thickness of a few .mu.m for the grown .beta.Type: GrantFiled: December 13, 1988Date of Patent: August 8, 1989Assignee: Fujitsu LimitedInventors: Takashi Eshita, Fumitake Mieno, Yuji Furumura, Kikuo Itoh
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Patent number: 4847215Abstract: A method for forming a SiC film having a wide optical energy gap and a high conductivity, which is capable of being stacked on a substrate of a large area uniformly. The SiC film is formed by supplying a material gas composed of monosilane gas, methane gas, diboran gas and hydrogen gas and having a hydrogen dilution ratio of about 144 and carbon mixing ratio of about 0.35, to the substrate, and supplying rf power of 60 to 270W(rf power density=80 to 350mW/cm.sup.2) under a gas pressure of 0.2 torr at a substrate temperature of 220.degree. C. The obtained film exhibits high dark-conductivity of 10.sup.-6 Scm.sup.-1 or more, and a Raman spectrum light thereof peaks at around 520 cm.sup.-1.Type: GrantFiled: October 31, 1988Date of Patent: July 11, 1989Assignee: Nippon Soken, Inc.Inventors: Kenichi Hanaki, Hitomi Kitagawa, Takayuki Tominaga, Tadashi Hattori
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Patent number: 4762807Abstract: An insulated-gate field effect transistor (IGFET) having the structure of the source and drain disposed in the longitudinal direction, i.e., the laminating direction, so that the channel region extends in the lateral direction when a high voltage is applied. This structure prevents a high current density at the interface of the channel region and the gate insulation film, allowing the fabrication of a large-current power transistor or the integration of such transistors.Type: GrantFiled: August 13, 1986Date of Patent: August 9, 1988Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki