Deposition Multi-step Patents (Class 148/DIG25)
  • Patent number: 4664743
    Abstract: A method for the growth of a semi-conductor material on a substrate by vapour phase epitaxy, comprises establishing a gas flow in each of a plurality of ducts, and moving the substrate, in a single plane of movement, from one duct to another. Suitable apparatus for use in the method comprises a plurality of ducts; apparatus for establishing a gas flow along each duct; a substrate support member, on which there may be a groove for the location of a substrate; and apparatus for moving, e.g. rotating, the support member. In use, the substrate is exposed sequentially to at least two of the gas flows, e.g. to grow GaInAs on InP.
    Type: Grant
    Filed: November 16, 1984
    Date of Patent: May 12, 1987
    Assignee: British Telecommunications plc
    Inventors: Rodney H. Moss, Paul C. Spurdens
  • Patent number: 4631804
    Abstract: A technique is disclosed for the artificial introduction of a localized subsurface strained layer within a thick polysilicon layer to minimize the large change in warpage (defined as springback) which occurs in a (100) Si substrate thinning operation during the mechanical processing of dielectrically isolated (DI) wafers. This novel technique is capable of favorably altering the state of stress and the stress profile in the multicomponent "polysilicon/SiO.sub.2 /(100) Si" DI structure so as to reduce the natural springback in warpage that occurs when the stiffening member, the (100) Si substrate, is removed. This subsurface disturbed layer is retained within the polysilicon layer during subsequent processing to maintain the favorable stress profile with a minimum of wafer warpage. In one embodiment of the present invention, the subsurface strained layer is generated by growing an interface layer (SiO.sub.2 or Si.sub.3 N.sub.
    Type: Grant
    Filed: December 10, 1984
    Date of Patent: December 30, 1986
    Assignee: AT&T Bell Laboratories
    Inventor: Pradip K. Roy
  • Patent number: 4632712
    Abstract: Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.
    Type: Grant
    Filed: December 4, 1984
    Date of Patent: December 30, 1986
    Assignee: Massachusetts Institute of Technology
    Inventors: John C. C. Fan, Bor-Yeu Tsaur, Ronald P. Gale, Frances M. Davis
  • Patent number: 4599792
    Abstract: A method for fabrication of a buried field shield in a semiconductor substrate. A seed substrate is prepared by depositing an epitaxial layer or a seed wafer and then depositing a heavily doped layer and a thin dielectric. The thin dielectric is patterned for contact holes and then a conductive field shield is deposited and patterned. A thick quartz layer is deposited over the field shield and dielectric. A mechanical substrate is anodically bonded to the quartz of the seed substrate and the original seed wafer is etched back to expose the epitaxial layer for further fabrication.
    Type: Grant
    Filed: June 15, 1984
    Date of Patent: July 15, 1986
    Assignee: International Business Machines Corporation
    Inventors: Paul E. Cade, Badih El-Kareh, Ick W. Kim
  • Patent number: 4592792
    Abstract: Monocrystalline silicon is deposited on first and second portions of a substrate, the first and second portions having substantially unequal dimensions. The method comprises subjecting the substrate to a silicon-source gas and a predetermined concentration of chloride at a predetermined temperature. The chloride concentration is selected so as to create a substantially equally thick monocrystalline silicon deposit on each of the substrate portions.
    Type: Grant
    Filed: January 23, 1985
    Date of Patent: June 3, 1986
    Assignee: RCA Corporation
    Inventors: John F. Corboy, Jr., Lubomir L. Jastrzebski
  • Patent number: 4588451
    Abstract: Expitaxial composite comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) on single crystal silicon substrates are disclosed. Also disclosed is a process for manufacturing, by chemical deposition from the vapor phase, epitaxial composites as above described, and to semiconductor devices based on such epitaxial composites. The composites have particular utility for use in making light sensitive solid state solar cells.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: May 13, 1986
    Assignee: Advanced Energy Fund Limited Partnership
    Inventor: Stanley M. Vernon
  • Patent number: 4578127
    Abstract: Single GaAs quantum well or single GaAs active layer or single reverse interface structures with Al.sub.x Ga.sub.1-x As barrier layers have improved qualities when one or more narrow bandgap GaAs getter-smoothing layers, which are thin, are grown and are incorporated in the barrier layer before and in close proximity to the active layer.
    Type: Grant
    Filed: August 13, 1982
    Date of Patent: March 25, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Arthur C. Gossard, Robert C. Miller, Pierre M. Petroff
  • Patent number: 4561916
    Abstract: A method for the growth of a compound semiconductor comprises growing on a silicon substrate a polycrystalline layer of a desired Group III-V compound semiconductor or a crystal layer of the desired Group III-V compound semiconductor having inferior crystallinity, growing on the formed layer at least one layer of the same semiconductor as the desired Group III-V compound semiconductor and at least one layer of a Group III-V compound semiconductor having a lattice constant approximating the lattice constant of the desired Group III-V compound semiconductor, which layers are alternately disposed, and growing on the alternately disposed layers a layer of the desired Group III-V compound semiconductor.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: December 31, 1985
    Assignees: Agency of Industrial Science and Technology, Ministry of International Trade and Industry
    Inventors: Masahiro Akiyama, Yoshihiro Akiyama
  • Patent number: 4554030
    Abstract: A monocrystalline layer of one semiconductor material is grown onto a surface of a monocrystalline semiconductor body by means of molecular beam epitaxy. During such growth, the semiconductor body is kept at such a low temperature that a non-monocrystalline layer is obtained. The non-monocrystalline layer is then converted by a heat treatment into a monocrystalline form. Accordingly, an abrupt junction between the two semiconductor materials is obtained.
    Type: Grant
    Filed: March 2, 1984
    Date of Patent: November 19, 1985
    Inventors: Jan Haisma, Poul K. Larsen, Tim De Jong, Johannes F. Van der Veen, Willem A. S. Douma, Frans W. Saris
  • Patent number: 4529455
    Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described.
    Type: Grant
    Filed: October 28, 1983
    Date of Patent: July 16, 1985
    Assignee: AT&T Bell Laboratories
    Inventors: John C. Bean, Leonard C. Feldman, Anthony T. Fiory
  • Patent number: 4528047
    Abstract: A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer.
    Type: Grant
    Filed: June 25, 1984
    Date of Patent: July 9, 1985
    Assignee: International Business Machines Corporation
    Inventors: Klaus D. Beyer, Victor J. Silvestri
  • Patent number: 4522662
    Abstract: A method for growing Silicon On Insulator (SOI) films using only conventional very large scale integration (VLSI) techniques is provided. By sequentially varying the flow of HCL gas during the vertical-growth, lateral-overgrowth, coalescence, and planarization stages of the epitaxial deposition process allows the formation of high-quality SOI films on wider oxide stripes suitable for general transistor applications.
    Type: Grant
    Filed: August 12, 1983
    Date of Patent: June 11, 1985
    Assignee: Hewlett-Packard Company
    Inventors: Donald R. Bradbury, Chi-Wing Tsao, Theodore I. Kamins