Fuse Patents (Class 148/DIG55)
  • Patent number: 6074940
    Abstract: The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: June 13, 2000
    Assignee: Samsung Eletronics Co., Ltd.
    Inventors: Dong-Hun Lee, Jong-Hyon Ahn
  • Patent number: 5970346
    Abstract: The present invention provides a structure and method for forming a moisture barrier guard ring structure 38 44 48 52 54 for around a fuse window 30 in a semiconductor device. The invention begins by forming a fuse structure 32 33 34 over the isolation regions cross the fuse window area. A cap layer 38 and an interlevel dielectric layer (ILD) 40 are formed over the fuse structure. A first annular ring 44 (e.g., contact w-plug) is formed over the isolation region 20 surrounding the fuse window area 30 and over the fuse structure 32 33 34. A key feature is that the first annular ring 44 and the cap layer 38 form a moisture proof seal over the fuse structure. A first conductive wiring line 48 is formed over the first annular ring 44. Next, an inter metal dielectric (IMD) layer 50 is formed over the interlevel dielectric layer 40. A second annular ring 52 is formed through the inter metal dielectric layer 50 on the first conductive wiring line 48.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: October 19, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 5879966
    Abstract: An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.
    Type: Grant
    Filed: September 6, 1994
    Date of Patent: March 9, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Jin-Yuan Lee, Chue-San Yoo, Hsien Wei Chin
  • Patent number: 5856233
    Abstract: A method is provided for forming a field programmable device of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed. A first, fusible, dielectric layer is formed over the first conductive layer. The dielectric layer is patterned and etched to form a plurality of dielectric regions exposing portions of the first conductive layer. A second dielectric layer is then formed over the dielectric regions and the exposed portions of the first conductive layer. A plurality of contact openings through the second dielectric layer are formed to expose portions of the first conductive layer and portions of the dielectric regions. A second conductive layer is then formed over the second dielectric layer and in the contact openings.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: January 5, 1999
    Assignee: STMicroelectronics, Inc.
    Inventors: Frank Randolph Bryant, Fusen E. Chen, Girish Anant Dixit
  • Patent number: 5834331
    Abstract: A p-i-n structure for use in photoconductors and diodes is disclosed, being formed of an Al.sub.x Ga.sub.1-x N alloy (X=0.fwdarw.1) with In.sub.y Ga.sub.1-Y N (Y=0.fwdarw.1) which as grown by MOCVD procedure with the p-type layer adjacent the substrate. In the method of the subject invention, buffer layers of p-type material are grown on a substrate and then doped. The active, confinement and cap layers of n-type material are next grown and doped. The structure is masked and etched as required to expose a surface which is ion implanted and annealed. A p-type surface contact is formed on this ion-implanted surface which is of sufficiently low resistance as to provide good quality performance for use in a device.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: November 10, 1998
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 5827759
    Abstract: A programmable fuse element disposed between integrated circuit elements that may be selectively joined during the manufacture or programming of an integrated circuit. The fuse element is a normally open fuse that electrically isolates the integrated circuit elements. The fuse element is comprised of a central area of conductive material insulated from the integrated circuit elements by areas of dielectric material. The integrated circuit elements and the fuse element are disposed on a thin oxide layer covering a semiconductor substrate to prevent those elements from shorting to the semiconductor substrate or to each other via the semiconductor substrate. A protective dielectric layer may be deposited over both the fuse element and the integrated circuit elements during the manufacture of the overall integrated circuit. A laser beam is used to burn through the protective layer and melts both the conductive material and the dielectric material that form the fuse element.
    Type: Grant
    Filed: January 9, 1997
    Date of Patent: October 27, 1998
    Assignee: Siemens Microelectronics, Inc.
    Inventor: Karl-Heinz Froehner
  • Patent number: 5786268
    Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.
    Type: Grant
    Filed: August 1, 1997
    Date of Patent: July 28, 1998
    Assignee: QuickLogic Corporation
    Inventors: Kathryn E. Gordon, Richard J. Wong
  • Patent number: 5786240
    Abstract: An over-etched (OE) antifuse includes a lower electrode, an antifuse layer contacting the lower electrode by an over-etched via, and a second conductive layer formed on the antifuse layer. This over-etched via forms a trench in the lower electrode, wherein in one embodiment the depth of the trench approximates the thickness of the antifuse layer. The trench narrows the programming voltage distribution of the antifuses on the device, irrespective of topology. Because active circuits can be placed underneath the OE antifuses, the present invention dramatically reduces chip size in comparison to conventional devices.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: July 28, 1998
    Assignee: Xilinx, Inc.
    Inventors: Kevin T. Look, Yakov Karpovich, Michael J. Hart
  • Patent number: 5756393
    Abstract: A method of jointly forming stacked capacitors and antifuses includes, a) providing a common layer of electrically conductive material to form both a capacitor storage node and an inner antifuse plate; b) providing a common layer of dielectric material over the capacitor storage node and the inner antifuse plate, the common layer of dielectric material comprising both an intervening capacitor dielectric element and an intervening antifuse dielectric element, the common layer of dielectric material having a first breakdown voltage per unit length value for a given current per unit area; c) providing a common layer of electrically conductive material over the common layer of dielectric material to form both a capacitor cell layer and an outer antifuse plate; d) providing a lateral edge of the outer antifuse plate and a lateral edge of the intervening antifuse dielectric element; and e) depositing an antifuse breakdown layer of dielectric material over the lateral edges of the outer antifuse plate and the interv
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: May 26, 1998
    Assignee: Micron Technology, Inc.
    Inventor: Charles H. Dennison
  • Patent number: 5721144
    Abstract: An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: February 24, 1998
    Assignee: International Business Machines Corporation
    Inventors: Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Shao-Fu Sanford Chu, Louis Lu-chen Hsu
  • Patent number: 5712206
    Abstract: The structure and method is provided which prevents moisture and contamination from diffusing through openings (e.g., fuse windows) in insulating layers to product devices. Three moisture barrier layers form a moisture impervious boundary system to prevent moisture from diffusing from a fuse window into other overlying layers and into product devices. First and second barrier layers are formed insulation layers below the fuse. A third barrier layer is formed over an uppermost insulation layer, the sidewalls of a fuse window and over the fuse. The first and third barrier layers form a seal in the fuse area. The method comprises forming an insulating layer 52 54 over portions of said substrate 50 including in said fuse window area 63. A first barrier layer 56, a first interlevel dielectric layer 58 are formed over the insulating layer. A second barrier layer 60 is formed over said first interlevel dielectric layer 58.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: January 27, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Chung-Zen Chen
  • Patent number: 5663091
    Abstract: A method for fabricating the antifuse of the present invention comprises the steps of forming a lower antifuse electrode; forming a relatively thick interlayer dielectric layer over the surface of the lower antifuse electrode; forming a masking layer, preferably a photoresist, including an aperture therein having a first area over the interlayer dielectric layer; performing a first vertical etching step on the interlayer dielectric layer to a first selected depth; enlarging the aperture in the masking layer until it has a second area; performing a final vertical etching step on the interlayer dielectric layer to expose the upper surface of the lower electrode. Depending on the thickness of the interlayer dielectric, additional enlarging steps and vertical etching steps may be performed prior to the final vertical etching step which exposes the upper surface of the lower electrode.
    Type: Grant
    Filed: May 9, 1996
    Date of Patent: September 2, 1997
    Assignee: Actel Corporation
    Inventors: Yeouchung Yen, Shih-Oh Chen, Hung-Kwei Hu
  • Patent number: 5652169
    Abstract: A programmable semiconductor element having an antifuse structure and a method for fabricating the same is disclosed. The fabrication method for a programmable semiconductor element having an antifuse structure includes processes for forming a first insulation film on a silicon substrate, forming a conductive material having a fixed width on the first insulation film, forming a second insulation film on the conductive material, forming a recess by etching a part of the second insulation film, forming a conductive link at corners of the recess in the second insulation film, forming a contact hole by etching the second insulation film in the recess thereof having no conductive link formed thereon, exposing the conductive material at a lower part, forming two separated conductors by etching the exposed conductive material, and forming a capping insulation film on the overall surface of the substrate and covering the conductive link.
    Type: Grant
    Filed: June 16, 1995
    Date of Patent: July 29, 1997
    Assignee: LG Semicon Co., Ltd.
    Inventor: Young Kwon Jun
  • Patent number: 5652175
    Abstract: A fuse structure is described in which a metallic frame is inserted between the insulation layers, through which the fuse window passes, and the final passivation layer. This frame is used as a mask during fuse window formation so alignment is simplified and problems arising from the presence of insulating residues on the surface of the fuse window layer are avoided.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: July 29, 1997
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Der-Cheng Chen, Peng-Cheng Chou
  • Patent number: 5650355
    Abstract: A fuse link 16 is formed of a portion of a top level of patterned metal conductor in a multilevel conductor integrated circuit 10. A deposited layer of oxide material 26 covers the fuse link. Radiant energy from such as a laser 36 is directed through the oxide material 26 to heat and open the fuse link 16. Layers of deposited protective oxide 28 and PIX 30 then cover the fuse link and layer of oxide material. One photoprocessing step is avoided by locating the fuse link 16 and bond pad 22, both made from the top layer of conductive material, at different levels. The blanket etch then exposes the bond pad 22 while leaving the fuse link 16 covered. The fuse link can be formed down in a step 38 or the bond pad 22 can be formed above such as a group of memory cells 80. The bond pad 22 and fuse link 16 also can be formed at the same level with other process procedures.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 22, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Hideyuki Fukuhara, Shigeo Ashigaki
  • Patent number: 5618750
    Abstract: A fuse for a semiconductor integrated circuit is provided wherein a strip of corrosive material (82), such as aluminum, has one end thereof connected to a conductive strip (84) of a non-corrosive material and the other end thereof connected to a strip (94) of non-corrosive conductive material. The one end of the conductive strip (82) connected to the conductive strip (84) is connected through a contact (88). Similarly, the other end of the strip (82) is connected through a contact (96) to the non-corrosive conductive strip (94). The strips 84 and 94 provide a barrier to corrosion. This occurs whenever a break (104) is formed in the fuse to expose the ends of the fuse (82) at the break to a corrosive atmosphere. Alternatively, the fuse could be connected to corrosive underlying layers with contacts (118) and (124) of non-corrosive material such as a polysilicon or a polyside, or the active region of the substrate itself.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: April 8, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Hideyuki Fukuhara, Yoichi Miyai
  • Patent number: 5614440
    Abstract: A method of fabricating a noise immune fuse having sub-micron dimensions which can be programmed by an electrically and thermally synchronized event. The fuse includes a pair of fuse links in close proximity of each other, a layer of thermally conductive and electrically insulating material thermally coupling the two links forming the pair, and means for programming the first link by prompting the second link to gate the energy transfer between the links via the coupling layer. By combining thermal and electrical pulses to perform the programming function, the reliability of the fuse structure is greatly enhanced when compared to that of a single element fuse.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: March 25, 1997
    Assignee: International Business Machines Corporation
    Inventors: Raschid J. Bezama, Dominic J. Schepis, Krishna Seshan
  • Patent number: 5578517
    Abstract: An integrated circuit includes a conductive fusible link that may be blown by heating with laser irradiation. The integrate circuit comprises: a silicon substrate; a first insulating layer; a fusible link on the first layer; a second insulating layer overlying the first layer and the fusible link; an opening through the second layer exposing the fuse; and a protective layer over the surfaces of the opening. A laser beam is irradiated through the opening and the protective layer to melt the fusible link. The protective layer is highly transparent to a laser beam and does not interfere with the laser melting (trimming) operation. Moreover, the protective layer prevents contaminates from diffusing in through the opening to harm adjacent semiconductor devices.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: November 26, 1996
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chue-San Yoo, Jin-Yuan Lee
  • Patent number: 5573970
    Abstract: An anti-fuse structure formed in accordance with the present invention includes a conductive layer base. A layer of anti-fuse material overlies the conductive base layer. On top of the anti-fuse layer is an insulating layer, in which a via hole is formed to the anti-fuse layer. The lateral dimension of the via hole is less than about 0.8 microns. Provided in the via hole is a conductive non-Al plug which overlies a layer of a a conductive barrier material such as TiN or TiW that contacts the anti-fuse material and overlies the insulating layer. Tungsten is effectively used as the non-Al plug. An electrically conductive layer is formed over the plug and is separated from the conductive barrier material overlying the anti-fuse layer by the plug. The structure is then programmable by application of a programming voltage and readable by application of a sensing voltage, which is lower than the programming voltage.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: November 12, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Dipankar Pramanik, Subhash R. Nariani
  • Patent number: 5552338
    Abstract: A method for blowing a fuse in an IC device using the current generated by latchup. A fuse comprising a conductive material is caused to electrically open by directing a latchup current through the conductive material. The latchup current is generated by properly biasing parasitic bipolar transistors formed within the semiconductor substrate of the IC device, causing these parasitic transistors to latch up.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: September 3, 1996
    Assignee: Intel Corporation
    Inventor: Wonjae L. Kang
  • Patent number: 5538924
    Abstract: An improved structure and method for forming an integrated circuit guard ring which prevents contamination/moisture from diffusing through a fuse opening, in the insulating layer(s), to device areas, is described. A first insulating layer is formed over portions of the substrate. A gate insulating layer is formed surrounding the first insulating layer. The first ring surrounds a fuse area--including the area where the fuse will be cut by a laser or burned by a current. A first dielectric layer is formed over the substrate surface. A first passivation layer is then formed over the first insulating layer. A first opening is formed through the first passivation layer and first dielectric layer over the first ring. A fuse is formed over the first passivation layer over the fuse area and a second ring of water impervious material is formed on the first ring through the first opening. The first and second rings form a moisture impervious seal.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: July 23, 1996
    Assignee: Vanguard International Semiconductor Co.
    Inventor: Chung-zen Chen
  • Patent number: 5521116
    Abstract: A method for fabricating and for blowing top lead fuses (41 and 42) includes the steps of: (a) forming a conductive top lead fuse (41) on a layer of insulator (45); (b) depositing a layer of top insulator (47) over the top lead fuse at a top to sidewall thickness ratio of approximately 2:1; (c) anisotropically etching the top insulator back universally to a top to sidewall thickness ratio of approximately 1:2. The resulting top lead fuses (30 and 31) are selectively blown explosively out (24) of the top surface of the top insulator.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: May 28, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Katsushi Boku
  • Patent number: 5508220
    Abstract: Antifuses having minimum areas are formed by a process including the steps of forming doped regions in a semiconductor substrate, forming a dielectric layer over the surface of the substrate, performing masking and etching steps to form apertures in the dielectric layer over portions of the doped regions where antifuses are to be formed, depositing a second dielectric layer over the first dielectric layer and the apertures, the second dielectric layer having a faster etch rate than the first dielectric layer, etching the second dielectric layer to leave spacers at the edges of the apertures, forming the antifuse dielectric in the apertures, and forming upper antifuse electrodes over the antifuse dielectric.
    Type: Grant
    Filed: June 1, 1993
    Date of Patent: April 16, 1996
    Assignee: Actel Corporation
    Inventors: Abdelshafy A. Eltoukhy, Gregory W. Bakker
  • Patent number: 5502000
    Abstract: An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.
    Type: Grant
    Filed: May 8, 1995
    Date of Patent: March 26, 1996
    Assignee: Xilinx, Inc.
    Inventors: Kevin T. Look, Evert A. Wolsheimer
  • Patent number: 5482884
    Abstract: A process for fabricating the metal-to-metal antifuse of the present invention includes the steps of forming a first metal layer on a semiconductor or other microcircuit structure; forming a first barrier layer over the first metal layer; forming a thick insulating layer over the barrier layer; forming an antifuse aperture in the thick insulating layer; forming a first heavily doped amorphous silicon layer in the aperture over the first barrier layer; forming a dielectric antifuse material layer over the first amorphous silicon layer; forming a second heavily doped amorphous silicon layer over the first dielectric antifuse material layer; forming a second barrier layer over the second amorphous silicon layer; and forming a second metal layer over the second barrier layer.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: January 9, 1996
    Assignee: Actel Corporation
    Inventors: John L. McCollum, Abdul R. Forouhi
  • Patent number: 5472901
    Abstract: A process and resulting product are described for forming an integrated circuit structure with horizontal fuses on an insulation layer formed over other portions of the integrated circuit structure by forming rectangular recesses in the insulation layer which are subsequently filled during a subsequent metal deposition step which also serves to fill with the same metal vias or contact openings which have been etched through the insulation layer. Subsequent planarization of the deposited metal layer down to the vias or contact openings, i.e. to remove the portions of the metal layer over the insulation layer, leaves the metal in the vias or contact openings and also leaves metal stringers on the sidewalls of the rectangular recess which then serve as fusible links (fuses) which are then connected to one or more metal lines thereafter formed on the insulation layer.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: December 5, 1995
    Assignee: LSI Logic Corporation
    Inventor: Ashok K. Kapoor
  • Patent number: 5468680
    Abstract: A device and a method for interrupting the continuity of a conductor and linking a pair of conductors are disclosed. The device is a three-terminal fuse having first and second terminals initially connected by a conductor and a third terminal separated from the conductor at a breakpoint of the conductor by an insulator. By applying a voltage across the third terminal or control terminal and the conductor, a transient conductive link is formed between the conductor and the control terminal. If sufficient current is provided through the transient link, heating of the link causes the metal of the conductor to melt and boil away, thus interrupting the continuity of the conductor.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: November 21, 1995
    Assignee: Massachusetts Institute of Technology
    Inventor: Simon S. Cohen
  • Patent number: 5457059
    Abstract: A method for providing programmable devices in which an insulation layer, such as an oxide (20), TEOS, or the like, is formed during a BiCMOS integrated circuit fabrication process includes forming a first conductor fuse layer (22), for example of TiW or the like, on the insulation layer (20). The fuse layer (22) may then be patterned, and a second insulation layer (23) formed over it. Alternatively, the fuse layer (53) may be left unpatterned and one or more conductor layers (35,36) may be formed over the fuse layer (53). The conductor layer (35,36) is patterned, and the fuse layer (53) thereafter patterned using the conductor layer (35,36) as an etch mask. In either case, contact holes (26) are formed in the insulation layer (20) to regions (14,15) to which contact is desired under the insulation layer (20).
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: October 10, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Stephen A. Keller, Rajiv R. Shah
  • Patent number: 5444012
    Abstract: In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.
    Type: Grant
    Filed: July 20, 1994
    Date of Patent: August 22, 1995
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Keiichi Yoshizumi, Kazushi Fukuda, Seiichi Ariga, Shuji Ikeda, Makoto Saeki, Kiyoshi Nagai, Soichiro Hashiba, Shinji Nishihara, Fumiyuki Kanai
  • Patent number: 5436196
    Abstract: In a method of fabricating a semiconductor laser, a laminated layer structure including a double heterojunction, having an active layer sandwiched by an upper and a lower cladding layer, is formed on a semiconductor wafer. An insulating film is formed with a pattern including a first to-be-processed region corresponding to respective chip regions including a ridge formation region and a second to-be-processed region corresponding to edge regions of the respective chip regions. Apertures are formed in the insulating film at both sides of the ridge formation region of the laser element at the first to-be-processed region having a large insulating film aperture ratio and at the light emitting facet formation region of the laser element at the second to-be-processed region having a small insulating film aperture ratio. The semiconductor layers exposed through the insulating film apertures are etched with a chemically reactive gas having an increased etching speed at a smaller insulating film aperture ratio.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: July 25, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Motoharu Miyashita
  • Patent number: 5411917
    Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first electrode, a first dielectric layer disposed over the lower first electrode, a layer of amorphous silicon disposed above the first dielectric layer, a second dielectric layer disposed above the amorphous silicon layer, and an upper second electrode disposed above the second dielectric layer.
    Type: Grant
    Filed: January 19, 1993
    Date of Patent: May 2, 1995
    Assignee: Actel Corporation
    Inventors: Abdul R. Forouhi, John L. McCollum, Shih-Oh Chen
  • Patent number: 5395797
    Abstract: An antifuse structure (20) and method of fabrication are provided. A first conductive layer (A) is etched according to a first mask (62a) having a first pattern and according to a second mask (64a) having a second pattern. A first insulative layer (30) is disposed over the first conductive layer (A) and etched according to a third mask (40a) having a third pattern to expose at least one section of the first conductive layer (A). A second insulative layer (26) is disposed adjacent at least one exposed section of the first conductive layer (A). A second conductive layer (1) is disposed over the second insulative layer (26) so that the antifuse structure (20) includes at least one antifuse region (A1) where a section of the second insulative layer (26) is adjacent the first (A) and second (1) conductive layers. The antifuse region (A1) has a sublithographic vertical dimension (t) according to a thickness of the first conductive layer (A).
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: March 7, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Kueing-Long Chen, Ashwin H. Shah, David K. Liu
  • Patent number: 5391513
    Abstract: An improved method for forming vias in an anti-fuse semiconductor device through an oxide layer to an underlying metallic layer. A wet etch is performed on the oxide layer at selected regions where vias are to be formed. The wet etch is controlled such that a first recessed area is formed in the oxide layer at the selected regions. The first recessed area formed by the wet etch extends only partially through the oxide layer towards the underlying metallic layer. Additionally, the first recessed area is formed having a smoothly shaped contour. Next, a dry etch is performed on the oxide layer at the selected regions where the vias are to be formed. The dry etch is performed within the first recessed area. The second recessed area has a smaller cross sectional area than the first recessed area such that the second recessed area is peripherally bordered by the first recessed area.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: February 21, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Miguel A. Delgado, Stacy W. Hall
  • Patent number: 5387311
    Abstract: A method for removing excess spacer material in the link vias and open areas of an anti-fuse structure without thinning the anti-fuse layer in the vias by overetching. In an anti-fuse structure, a spacer layer is deposited on an anti-fuse layer where vias in the structure cause a thinner layer of spacer material to be deposited in the vias. A first etch of the spacer layer is accomplished to provide protective spacers in the vias. The etch completely removes the thinner section of the spacer material between the spacers in the vias without overetch, while some spacer material portions remain on the other, open areas of the anti-fuse structure. Designated fuse vias are masked and a second etch of the leftover spacer material is accomplished. This method removes excess spacer material from link vias and other areas around the fuse vias and prevents the anti-fuse layer in the fuse vias from thinning from overetching procedures.
    Type: Grant
    Filed: February 16, 1993
    Date of Patent: February 7, 1995
    Assignee: VLSI Technology, Inc.
    Inventors: Stacy W. Hall, Miguel A. Delgado
  • Patent number: 5340775
    Abstract: A SiCr microfuse, deletable either by electrical voltage pulses or by laser pulses, for rerouting the various components in an integrated circuit, as where redundancy in array structures is implemented, and the method of fabricating same, at any wiring level of the chip, by utilizing a direct resist masking of the SiCr fuse layer to eliminate problems of mask damage and residual metal adjacent the fuse.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: August 23, 1994
    Assignee: International Business Machines Corporation
    Inventors: Roy A. Carruthers, Fernand J. Dorleans, John A. Fitzsimmons, Richard Flitsch, James A. Jubinsky, Gerald R. Larsen, Geraldine C. Schwartz, Paul J. Tsang, Robert W. Zielinski
  • Patent number: 5308795
    Abstract: A method for fabricating a metal-to-metal antifuse comprises the steps of (1) forming and defining a first metal interconnect layer; (2) forming an interlayer dielectric layer; (3) forming an antifuse via in the interlayer dielectric layer to expose the first metal interconnect layer; (4) depositing a via metal layer into a portion of the volume defining the antifuse via; (5) forming a planarizing layer of an insulating material in the antifuse via sufficient to fill a remaining portion of the volume defining the antifuse via; (6) etching the planarizing layer to expose an upper surface of the via metal layer and an upper surface of the interlayer dielectric layer so as to form a substantially planar surface comprising the upper surface of the interlayer dielectric layer, the planarizing layer, and the upper surface of the via metal layer; (7) forming an antifuse material layer over the substantially planar surface; (8) forming a metal capping layer over the antifuse material layer; and (9) defining the antif
    Type: Grant
    Filed: November 4, 1992
    Date of Patent: May 3, 1994
    Assignee: Actel Corporation
    Inventors: Frank W. Hawley, Yen Yeouchung
  • Patent number: 5300456
    Abstract: A method of forming a metal-to-metal antifuse. An antifuse stack 32 is formed comprising a first metal layer 16, an antifuse dielectric layer, and an etchstop layer. The etchstop layer may, for example, comprise an oxide layer 24 and an amorphous silicon layer 28. An antifuse via 44 is etched through an interlevel dielectric layer 36 to the antifuse stack 32. Next, a portion of the etchstop layer at the bottom of via 44 is removed. Finally, a second layer of metal 48 is deposited to fill antifuse via 44 and etched to form the desired interconnections.
    Type: Grant
    Filed: June 17, 1993
    Date of Patent: April 5, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Howard L. Tigelaar, George Misium
  • Patent number: 5290734
    Abstract: An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: March 1, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: William J. Boardman, David P. Chan, Kuang-Yeh Chang, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani
  • Patent number: 5284794
    Abstract: A semiconductor device has a thin-film resistor trimmed by laser. The semiconductor device comprises a semiconductor substrate having an element region that covers at least part of the surface of the semiconductor substrate, a first insulation film disposed on the surface of the semiconductor substrate, and a second insulation film disposed on the surface of the semiconductor substrate through an opening of the first insulation film. The opening is formed by selectively removing at least part of the first insulation film at a location on the surface of the semiconductor substrate where the element region is not involved. The thin-film resistor is formed on the second insulation film.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: February 8, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yoshihiko Isobe, Makio Iida, Shoji Miura, Keizou Kajiura, Mikimasa Suzuki, Masami Saito
  • Patent number: 5284788
    Abstract: A device (10) for controlling current through a circuit has an antifuse material (18) separating a first conductor (12) and a second conductor (20). An insulating element (14) and another insulating element (16) further separate the first conductor (12) from the second conductor (20). The antifuse material (18) includes a dopant which raises the band gap and seals off paths in grain boundaries of the antifuse material (18) in order to limit leakage current from flowing between the first conductor (12) and the second conductor (20). When an interconnection is desired, a high voltage pulse is applied across the first conductor (12) and the second conductor (20) to initially break down the antifuse material (18). The breakdown of the antifuse material (18) causes a filament (22) to form between the first conductor (12) and the second conductor (20). The filament (22) creates a conduction path connecting the first conductor (12) and the second conductor (20) electrically together.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: February 8, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: David B. Spratt, Kueing-Long Chen
  • Patent number: 5250464
    Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.
    Type: Grant
    Filed: March 11, 1992
    Date of Patent: October 5, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Man Wong, David K. Liu
  • Patent number: 5248632
    Abstract: An antifuse (42) is formed by forming a layer of titanium tungsten (34) overlying a portion of a first metal layer (28). The titanium tungsten layer (34) is oxidized to form a film of oxide (36) on its surface. Insulating regions (30) are formed adjacent the titanium tungsten layer (34) and overlying the first metal layer (28). A second metal layer (40) is formed overlying the titanium tungsten layer (34). Applying a break down voltage across the first and second metal layers (28), (40) will break down the oxide film (36), thereby causing a connection between the first and second metal layers (28), (40).
    Type: Grant
    Filed: September 29, 1992
    Date of Patent: September 28, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Yingsheng Tung, Scott Montgomery
  • Patent number: 5185291
    Abstract: Integrated-circuit devices are provided with conductive paths or links which, by laser irradiation or electric current pulsing, can be severed or fused. In the interest of ease of fusing, preferred links have locally reduced thickness as achieved, e.g., by employing two steps of layer deposition and etching as follows: first, a layer of conductor material is deposited on a dielectric surface, and locally reduced in thickness by etching at one or several points selected for fusing, and, second, a further layer of conductor material is deposited, and then etched to produce a desired conductive path passing through such points.
    Type: Grant
    Filed: September 6, 1991
    Date of Patent: February 9, 1993
    Assignee: AT&T Bell Laboratories
    Inventors: Frederick H. Fischer, Kuo-hua Lee, William J. Nagy, Nur Selamoglu
  • Patent number: 5171715
    Abstract: An antifuse according to the present invention includes a lower electrode formed from a first metal interconnect layer in an integrated circuit or the like. The lower electrode is disposed on an insulating surface. An inter-metal dielectric including an antifuse aperture disposed there lies over the inter-metal dielectric layer. The antifuse aperture extends through the inter-metal dielectric layer and also extends completely through the lower electrode. An antifuse material is disposed in the antifuse aperture. An upper electrode formed from a first metal interconnect layer is disposed over the antifuse material.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: December 15, 1992
    Assignee: Actel Corporation
    Inventors: John D. Husher, Abdul R. Forouhi
  • Patent number: 5126282
    Abstract: An already- programmed anti-fuse is DC soaked by passing DC current through the anti-fuse from a DC voltage source applied across the electrodes of the anti-fuse. The anti-fuse resistance is lower when the DC voltage being applied such that the positive end of the voltage source is applied to the electrode having the higher arsenic concentration.An already programmed anti-fuse is AC soaked, by passing alternating current pulses through the anti-fuse from an AC voltage source applied across the anti-fuse electrodes. This AC soak may even be applied following the controlled polarity DC soak disclosed herein. The AC soaked anti-fuse resistance is even lower than DC soaked anti-fuse under the same soak current level.
    Type: Grant
    Filed: May 16, 1990
    Date of Patent: June 30, 1992
    Assignee: Actel Corporation
    Inventors: Steve S. Chiang, Esam Elashmawi, Theodore M. Speers, LeRoy Winemberg
  • Patent number: 5120679
    Abstract: An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: June 9, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: William J. Boardman, David P. Chan, Kuang-Yeh Chang, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani
  • Patent number: 5100827
    Abstract: An integrated circuit having one or more antifuses which connect electrical components through a dielectric layer. The antifuse is formed before the thick dielectric is deposited and patterned to form windows which expose the antifuse.
    Type: Grant
    Filed: February 27, 1991
    Date of Patent: March 31, 1992
    Assignee: AT&T Bell Laboratories
    Inventor: Steven A. Lytle
  • Patent number: 5057451
    Abstract: A minimum sized aperture for a reduced capacitance anti-fuse or other structure may be formed by birds beak encroachment of thick oxide under a masking layer or by isotropic etching of a masking layer followed by birds beak encroachment of thick oxide.
    Type: Grant
    Filed: April 12, 1990
    Date of Patent: October 15, 1991
    Assignee: Actel Corporation
    Inventor: John L. McCollum
  • Patent number: 5019532
    Abstract: A method for forming a fuse for integrated circuits and a fuse produced therefrom is disclosed. The fuse (10) includes a substrate (12) having thick oxide layers (14) with a gap (16) formed therebetween. A second oxide layers (20), (14) is grown onto an N+ region (18). At the intersection between oxide layer (20), a sublithographic area is exposed and a dielectric layer (24) is formed therein. This structure is capable of reducing the capacitance between a polysilicon layer (26) formed thereon and the N+ diffusion region (18).
    Type: Grant
    Filed: September 21, 1990
    Date of Patent: May 28, 1991
    Assignee: Texas Instruments Incorporated
    Inventor: Cetin Kaya
  • Patent number: 5017510
    Abstract: A fuse link (50) is formed using a method which offers greater scalability of the general conductor system used to wire the device. An oxide mask (36) having the shape of a desired fuse link is formed over a thin metallization layer (34). A barrier layer (38) is formed over the thin metallization layer (34). A conductive layer (40) is formed over the barrier layer (38). A photoresist mask (42) supplied to the conductive layer (40), and the conductive layer is etched to formed interconnects (44, 46). Subsequently, the barrier layer (38) and thin metallization layer (34) are etched, thus rendering a fuse link (50) between interconnects (44, 46) under the oxide mask (36).
    Type: Grant
    Filed: May 25, 1989
    Date of Patent: May 21, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Michael T. Welch, Ronald E. McMann, Manuel L. Torreno, Jr., Evaristo Garcia, Jr.