Abstract: The present invention privides a method for manufacturing an ISRC MOSFET, comprising steps of forming an isolating layer through the LOCOS process, depositing a mask oxide layer, exposing only the part of silicon substrate for forming the channel and shallow junction of source/drain layers, depositing the first nitride layer over the resultant substrate, dry-etching the first nitride layer to form a nitride side-wall, forming an oxide layer being recessed into the channel, wet-etching the nitride side-wall, forming two doped layers for the shallow source/drain by an N.sup.+ or P.sup.+ ion-implantation, depositing the second nitride layer, dry-etching for forming a nitride side-wall, forming a P.sup.- or N.sup.- doped layer between the two doped layers, forming a gate oxide layer on the P.sup.- or N.sup.

Abstract: A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned for formation of an NMOS transistor, a second gate line being positioned for formation of a PMOS transistor; b) providing a layer of polysilicon to define a first and second pairs of polysilicon outward projections extending from the semiconductor substrate adjacent the first and second gate lines, respectively; c) masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; d) masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; e) out-diffusing conductivity enhancing dopant impurit

Abstract: A method of fabricating a high-voltage metal-gate CMOS device is disclosed. First, a semiconductor substrate of a first conductivity type having a well region of a second conductivity type is provided. Next, a barrier layer is formed and patterned to form openings for prospective source/drain regions. Then, through the openings, low concentrations of impurities of the first conductivity type and the second conductivity type are implanted into the well region and the semiconductor substrate, respectively. After performing a first thermal treatment, lightly doped source/drain regions of the first conductivity type and the second conductivity type are formed respectively, wherein an oxide layer is also formed within the openings. A sidewall spacer is formed on the sidewalls of the openings.

Abstract: A process for fabricating a high-voltage metal-gate CMOS transistor is disclosed. The CMOS transistor comprises a pair of complementary NMOS and PMOS transistors. The CMOS transistor is fabricated on an semiconductor substrate of a first conductivity type, which has a well region of a second conductivity type therein; therefore, the PMOS and NMOS are fabricated onto the substrate or well region, separately. It can be understood that use of the opening prepared in the initial, and, the only primary shielding layer for the location of the source/drain regions of both the NMOS and PMOS transistors, comprises the key to the precision alignment, and to the dimensional symmetry of the transistors fabricated. This is because that the subsequent fabrication procedural steps after the formation of the shielding layer with the set openings, including all the deposition, the ion implantation, and the etching, etc.

Abstract: In a CMOS semiconductor device, low-dose ion implant of p-type impurity and n-type impurity is successively conducted to both n-MOSFET and p-MOSFET after formation of gate electrodes. Thereafter, when source/drain regions are formed at each MOSFET, p.sup.- regions function as local punch through stoppers in the n-MOSFET and n.sup.- regions function as the local punch through stoppers in the p-MOSFET. At this time, respective doses of n-type and p-type impurities are adjusted so that lowerings of threshold values of the channel regions are almost equal to each other. Thus, short channel effect is prevented, while reducing the step of forming two resist masks. With side walls, the CMOS semiconductor device with less short channel effect and high durability to hot carrier is manufactured without increase in the step of forming the resist masks.

Abstract: A method for fabricating CMOS chips, using a SRAM cell composed of, both NFET and PFET devices, or only NFETs, as well as incorporating NFET and PFET peripheral devices, is described. This process features an NFET, used in the SRAM cell, where a lightly doped arsenic source and drain region is used to achieve maximum device performance, in terms of saturation current, as well as gate to diffusion overlap capacitance. However the NFET used for the peripheral device is fabricated using a lightly doped phosphorous source and drain region, to allow for more protection against the deleterious hot carrier injection phenomena.

Abstract: A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation.

Abstract: In a method for fabricating a CMOS device with NMOS and PMOS transistors, patterned nitride films are employed in the source/drain ion implantation procedure to reduce the required number of photolithography steps.

Abstract: A CMOS device is provided with a deep collector guard ring. The guard ring is formed by thermally deep diffusing impurities from a poly layer into the surface of a well beneath the poly layer. The guard ring can thus be easily manufactured using CMOS compatible fabrication processes to a depth which is greater than the source and drain regions of the CMOS device.

Abstract: A process of forming complementary insulated gate field effect transistors includes forming first and second well regions of first and second conductivity types in a planar semiconductor layer so that the well regions have an impurity retrograde impurity distribution profile. An insulator layer is then selectively formed with a first relatively thick insulator portion and thin gate portions. The first and second gates are formed on the relatively thin portions of the insulator layer. Insulator spacers are formed so as to extend laterally from the gates and from the relatively thick insulator portion. First impurities are introduced using the first gate and spacers as a mask to form first source and drain regions. Second impurities of an opposite conductivity type are introduced using the second gate and spacers as a mask to form source and drain regions of a complementary device.

Abstract: A high withstanding voltage MIS transistor, including an offset region and a double offset region in a region of a semiconductor substrate. The region of the semiconductor substrate has a first conductivity type. The offset region connects to a drain region, and has a second conductivity type. An impurity concentration of the offset region is lower than that of the drain region. The double offset region has the first conductivity type. At least a portion of the double offset region overlaps with the offset region. An impurity concentration of the double offset region is higher than that of the region of the semiconductor substrate. The disclosed structure has an improved current gain of the MIS transistor is improved.A method of manufacturing a CMOS having such a MIS transistor decreases the number of the manufacturing steps because the double offset region of a first conductivity type channel MIS transistor and the offset region of a second conductivity type channel MIS transistor are simultaneously formed.

Abstract: A method for fabricating complementary enhancement and depletion mode field ffect transistors on a single substrate comprises the steps of: a) patterning a structure of a layer of silicon formed on an insulating substrate to form first, second, third, and fourth silicon islands; b) doping the second island with a p-type dopant; c) doping the third island with a p-type dopant; d) doping the fourth island with an n-type dopant; e) forming a first electrically insulating gate layer on the third and fourth islands; f) forming a second electrically insulating gate on the first and second islands; g) forming an electrically conductive gate over the first and second electrically insulating gate layers; h) doping the second island with an n-type dopant; i) doping the fourth island with an n-type dopant; j) doping the first and third islands with a p-type dopant; and k) doping the first and third islands with a p-type dopant to transform the first island into a p-type enhancement mode field effect transistor, the seco

Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

Abstract: A new IC wafer fabrication process provides an improved CMOS active strip mask, etch, V.sub.T adjust, and gate oxide grow sequence particularly applicable for preparation of CMOS transistors in BICMOS wafers. The new gate oxide process reduces the number of process steps and thermal cycles, increases the reliability of the gate oxide layer, and substantially reduces differential stress and thermal stress related structural silicon defects in the epitaxial silicon. The process proceeds by forming a photoresist CMOS active strip mask exposing CMOS transistor active areas, etching and removing the CVD nitride layer over the CMOS transistor active areas, and leaving the EPIOX layer. Further steps include introducing dopant material through the EPIOX layer into the EPI layer of CMOS transistor active areas with the photoresist active strip mask in place and adjusting the threshold voltage V.sub.T of the CMOS transistors.

Abstract: According to the present invention, in the ion implantation step in manufacturing a semiconductor device, a resist of a resist pattern formed on a portion of a semiconductor wafer is removed from the outer peripheral portion of the semiconductor wafer, and ion implantation is performed through the resist pattern.Since the resist is removed from the outer peripheral portion, a contact portion between a semiconductor wafer fixing portion of an ion implantation unit and the semiconductor wafer is conductive. Therefore, charges generated by the ion implantation escape from the wafer fixing portion, and the semiconductor wafer is not charged, thereby preventing electrostatic breakdown.

Abstract: A field effect transistor (FET) has a gate electrode, a source electrode and a drain electrode formed on a GaInAs/GaAs quantum well layer structure having an undoped GaAs layer, an impurity doped GaInAs layer, and an undoped GaAs cap layer. The FET further has low resistivity regions formed by ion-implantation in a source region and the drain region of the GaInAs/GaAs quantum well layer structure, and has the impurity doped GaInAs layer as a channel, and further has an undoped GaAs cap layer with a 30-50 nm thickness. An annealing temperature for activating the low resistivity region is not higher than a temperature at which the GaInAs/GaAs quantum well structure substantially breaks and not lower than a temperature at which the sheet resistivity of the low resistivity region sufficiently reduces. The FET thus manufactured has desired characteristics for the GaInAs/GaAs quantum well structure and the low resistivity region, and attains low noise and high speed operation.

Abstract: An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.

Abstract: In the fabrication of an MIS transistor, the distribution characteristic of the impurity density with respect to the depth of the first region exhibited when the amount of ions implanted for channel doping is varied is first determined. The swing value is calculated from the gate voltage - drain current characteristic on the basis of the distribution characteristic obtained. Ions are implanted to the channel portion at a dose which is selected in accordance with the impurity density of the first region so that the swing value takes the minimum value or a value as small as possible, thereby producing an MIS type semiconductor device having a channel doping structure in a first region between a source and a drain.

Abstract: A process is disclosed for making CMOS devices with enhanced performance PMOS FETS by integrating germanium technology into a silicon-based fabrication method. Silicon-germanium layers are selectively grown on the surfaces of oxide-isolated PFET pockets of a silicon substrate previously prepared by a conventional silicon CMOS process. A silicon cap is deposited over each Si--Ge layer and gate insulator is formed over the cap provide gate dielectric for the PFETS. Gate insulator is formed over the NFET pockets to provide gate dielectric for the NFETS. Gate structures are completed along with source and drain junctions in accordance with normal practice. Provision also is made for the additional selective growth of a second silicon-germanium layer on the surfaces of oxide-isolated NFET pockets on the same CMOS substrate to enhance the performance of the NFETS as well as that of the PFETS.

Abstract: A method for implanting diffusion regions during production of MOS transistors involves first patterning and etching a gate to produce a resist overhang covering at least one edge of the gate. Primary dopant is then implanted in the substrate to produce a first diffusion region having at least one boundary partially defined by the resist overhang covering the gate. By isotropically etching the resist on the gate, the gate itself is used as a mask during subsequent implantation of a halo diffusion region. The size of both the first diffusion region and the halo diffusion region is subsequently adjusted by annealing.

Abstract: A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a first polycrystalline silicon layer on the insulating film, forming a second polycrystalline silicon layer on the frist polycrystalline silicon layer, patterning the first and second polycrystalline silicon layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, starting etching the masking layer, detecting a natural oxide film on the gate electrode, stopping the etching, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region.

Abstract: A semiconductor device composed of: a semiconductor substrate of a first conductivity type having a first impurity concentration; a belt-shaped impurity layer of the first conductivity type which is formed in the substrate so as to be spaced apart from a surface of the substrate and which has a second impurity concentration which is higher than the first concentration at a first depth from the surface of the substrate; a gate electrode formed on the substrate via a first insulating film; a second impurity layer of a second conductive type which is formed in the substrate on both sides of the gate electrode such as to be spaced apart from each other and has a third impurity concentration at a second depth from the surface of the semiconductor substrate, whose lower surface abuts against the first impurity layer or is present thereabove, the second impurity layer having a configuration projecting downward of the gate electrode at a portion thereof adjacent to the first impurity layer; side wall insulating films

Abstract: A polysilicon layer of approximately 500.ANG. in thickness and a PSG layer approximately 3000.ANG. in thickness are sequentially layered on a silicon wafer on which a gate insulating layer is formed; an opening having been formed in the PSG layer. After forming a side wall layer made of PSG of predetermined thickness in the opening, a second polysilicon layer for a leg portion of an inverse-T gate is embedded in the opening and both PSG layers are removed. Then, n.sup.- impurities are doped by ion implantation by using the second polysilicon layer as a mask, forming a LDD region. Another side wall layer is formed on the second polysilicon layer, and then, the first polysilicon layer, exposed outside of the second polysilicon layer and the side wall layer, is etched. Under the side wall layer, that polysilicon layer constituting a top of the inverse-T gate remains. Ion implantation is implemented by using the second polysilicon layer and the side wall layer as masks, such that a n.sup.+ source and n.sup.

Abstract: A process for preparing a semiconductor device, which includes; forming on a semiconductive silicon substrate a gate oxide film and a gate electrode constituting a MOS transistor, a semiconductor element protective film on the gate electrode and a wiring layer on the protective film; forming, above the gate electrode, a first photoresist film having an opening correspondingly in position to a point that a channel region is to be provided, a silicon oxide film provided by spin-on-glass method and a second photoresist film having the same pattern as the first photoresist film in this order; etching by use of the second photoresist film as a mask to form a mask pattern which comprises three layers of the first and second photoresist films and the intervening silicon oxide film sandwiched therebetween and has an opening above the gate electrode correspondingly in position to that point for provision of the channel region; applying an impurity ion with high energy from above and through which mask pattern to be im

Abstract: An improved method for manufacturing high density CMOS integrated circuits which minimizes counterdoping of the N and P well structures includes providing a composite masking layer which has layers of silicon oxide, polycrystalline silicon and silicon nitride over a silicon monocrystalline substrate. A mask layer pattern is formed from the composite masking layer by lithography and anisotropic etching which removes the silicon nitride and the portion of the thickness of the polycrystalline silicon over areas designated to be the N well structure. The mask layer pattern is subjected to isotropic etching of the polycrystalline silicon to remove the remaining exposed thickness of polycrystalline silicon and to undercut etch the polycrystalline silicon under the silicon nitride portion of the mask layer pattern. The N well structure is ion implanted and formed by using the silicon nitride layer portion of the mask layer pattern as the mask.

Abstract: For formation of the LDD structure with stable impurity profiles, a first ion-implantation using a gate electrode as a mask is carried out through a gate oxide film for doping the semiconductor substrate with impurity atoms, covering the entire surface of the structure with a doped polysilicon film overlain by a protective oxide film, covering the protective oxide film with an intentionally undoped polysilicon film, anisotropically etching the intentionally undoped polysilicon film for forming a side wall on both sides of the side wall, removing exposed portions of the protective oxide film, carrying out a second ion-implantation using the gate electrode and the side wall as a mask for doping the semiconductor substrate with impurity atoms again, thereby forming heavily doped impurity regions partially overlapped with lightly doped impurity regions.

Abstract: In a semiconductor device according to the present invention, a pair of element regions of a second conductivity type are formed so as to be electrically isolated from each other on a semiconductor substrate of a first conductivity type, a complementary MOS transistor is formed in one of the element regions of the second conductivity type, and a double-diffused MOS transistor is formed in the other element region of the second conductivity type. The complementary MOS transistor is of a surface channel type in which N- and P-channel MOS transistors are respectively formed in a pair of well diffusion layers of the first and second conductivity types formed in the element region of the second conductivity type, and conductivity types of the respective gate electrodes of the N- and P-channel MOS transistors are different from those of the respective well diffusion layers.

Abstract: The present method uses a one block out mask method for forming both the N channel and P channel MOS field effect transistors by providing a special oxidizing method that grows sufficient silicon oxide upon the already formed N+ source/drain regions which is sufficient to block the P+ ion implantation which forms the P channel device from the N channel device area.

Abstract: Hot-carrier suppression in a sub-micron MISFET structure is achieved by providing a drain region which includes a steeply profiled N+ (or P+) doped region in the surface of a semiconductor body with a first epitaxial layer formed thereover having N- (or P-) dopant concentration. A second N+ (or P+) epitaxial layer is formed over the first epitaxial layer and functions as a low ohmic contact to the drain region. In a preferred embodiment both the source and drain regions have dopant concentrations provided by N+ (or P+) doped regions in the surface of a substrate with epitaxial layers thereover. The dopant profile reduces the voltage drop across the more highly doped region of the drain and thereby reduces the electric field therein. Further, the reduction in dopant concentration reduces the electric field due to energy band bending associate with the change in doping level from the N+ (P+) region to the N- (P-) epitaxial layer. The resulting sub-micron device has better long-term reliability.

Abstract: Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are constructed by providing one or more lightly doped P regions in a semiconductor wafer in which intrinsic and long channel NMOS devices may be constructed, and one or more N wells in the wafer where PMOS devices can be constructed; forming isolation oxide on the wafer before implanting the wafer to inhibit field inversion in N channel (NMOS) devices; masking N regions of the wafer except where long channel PMOS devices will be formed and portions of P regions of the wafer where long channel NMOS devices will be constructed, and optionally masking P regions where either intrinsic NMOS devices or short channel NMOS devices will be formed; and then implanting the wafer to simultaneously provide a field implant below the isolation oxide, adjacent regions where NMOS devices will be formed, as well as optionally providing a deep imp

Abstract: There are disclosed a structure and a manufacturing method of a MOS-type thin-film field effect transistor composed of a substrate having an insulating main surface, a gate electrode formed on the insulating main surface to have an upper surface and a side surface at its edge, an insulating film covering at least the upper and side surfaces of the gate electrode, a semiconductor film having three continuous first, second and third portions, the first portion positioned above the upper surface of the gate electrode, the second portion being formed in contact with the insulator film at the side surface of the gate electrode and the third portion positioned above the substrate without interposing the gate electrode, a side-wall insulator formed on a part of the third portion of the semiconductor film and having a side surface contacting the second portion of the semiconductor film, and source and drain regions formed by introducing impurity atoms into the first portion and another part of the third portion of th

Abstract: A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, forming a masking layer on the polycrystalline silicon layer, patterning the polycrystalline silicon and masking layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, removing the masking layer, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region. In this method, after the source and drain regions are formed, the impurity of the second conductivity type is ion-implanted in the substrate through the thin gate electrode to form the channel-doped region.

Abstract: A single mask method for providing multiple masking patterns, using excess etching techniques, which is usable for developing a semiconductor substrate for a semiconductor device which results in an increased current being required before latchup occurs in the semiconductor device.

Abstract: A GaAs JFET according to the present invention is formed as follows. First, an n type active layer is formed on a GaAs substrate. Then, a gate electrode containing a group II element is formed on the n type active layer. With the gate electrode being used as a mask, an n type impurity is ion-implanted in the GaAs substrate with a high concentration in a self-aligned fashion with respect to the gate electrode. Heat-treatment is then performed on the resultant structure to diffuse the group II element in the gate electrode into the n type active layer, forming a p type gate region. At the same time, the ion-implanted n type impurity is activated, forming source and drain regions.

Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used a mask for a second implantation.

Abstract: A method for producing a compound semiconductor device includes covering all but the top part of an electrode comprising a refractory metal or refractory metal silicide disposed on a compound semiconductor substrate with an insulating film, producing a photoresist which completely covers the insulating film at a first side of the electrode, the top part of the electrode, and at part of a second side of the electrode using the photoresist as a mask and removing the insulating film at the second side of the electrode, removing the photoresist, and ion implanting using the insulating film remaining at the first side of the electrode and the electrode as masks.

Abstract: A process for fabricating integrated circuits containing bipolar transistors in semiconductor wafers comprising the following steps:forming a well and an upper insulating layer on a semiconductor wafer;selectively patterning and doping a bipolar transistor base implant region into the well;selectively patterning a layer of conductive material atop the insulating layer, the conductive material layer selectively exposing a first area of the base implant region and covering other areas of the base implant region, the conductive material layer having at least one first edge which at least in part defines the exposed first area;doping through the exposed first area to form an emitter implant region within the base implant region, the conductive material layer masking without photoresist the other covered areas of the base implant region during doping of the exposed first area; then patterning the layer of conductive material to expose a second area of the base implant region and to form gates of MOS transistors el

Abstract: An improved masking stack (63) comprises a pad oxide (58), polysilicon (60) and nitride (62). After forming a photoresist pattern (64) over the stack (63), an anisotropic etch is performed to remove the nitride (62) and a portion of the polysilicon (60) not covered by the pattern (64). Another etch is performed to remove the remaining polysilicon (60) to leave at least a portion of the pad oxide (58). A boron implant (66) is conducted to form implant areas (68 and 70) within the unmasked silicon active device layer (56). A portion of the implant areas (68 and 70) is masked with nitride (72), and the unmasked silicon layer (56) is then etched. The masking stack (63) and the nitride (72) is removed and unprotected silicon layer (56) and implant areas (68 and 70) are covered with an oxide forming the silicon dioxide mesa (78).

Abstract: A process for manufacturing CMOS devices is described, wherein two separate masks are used for the production of the gate regions of the two complementary transistors of the CMOS device, each of said masks allowing the formation of the gate region of only one of the two complementary transistors and being also used for the implantation of ions adapted to form the source and drain regions of said transistor. Accordingly only two masking steps are sufficient for the production of the gate, drain and source regions of the CMOS devices, with a reduction of the costs related to the production of integrated circuits executed in CMOS technology.

Abstract: Disclosed is a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, a step of forming an ion implanted layer by implanting nitrogen ions into the polysilicon conductor film, and a step of forming a low resistance conductor film of titanium on the non-monocyrstalline conductor film. When a field effect transistor is formed by this method, using titanium nitride and/or TiSi.sub.2 alloy of the polysilicon conductor and low resistance conductor of titanium by heat treatment as a gate electrode material, the thickness of the alloyed layer is uniform, and breakdown of the gate insulating film due to local diffusion of low resistance conductor is not induced. In other embodiments, oxygen ions and silicon ions are also employed to form thin layers of tunnel oxide and amorphous silicon, respectively.

Abstract: A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self-aligned implantation is made possible by the process and structure using self-aligned etch. Programming of the memory cell uses standard EPROM programming, and erasing is accomplished by Fowler-Nordheim tunneling or photoemission. The memory cell can be made with a reduced cell size and read current uniformity is obtained.

Abstract: Disclosed is a self-aligned GaAs, lightly doped drain metal-semiconductor field effect transistor. In one embodiment, the device consists of a shallow n.sup.- active channel region formed on a GaAs substrate, a Schottky gate overlying the n.sup.- region and highly doped and deep n.sup.+ source and drain regions formed on either side of the gate. In the channel region between the gate edges and the source/drain are positioned n-type source/drain extensions which have an intermediate depth and doping concentration to minimize the device series resistance, suppress short channel effects and permit channel length reduction to submicron levels.In a second embodiment, p-type pockets are provided under the source/drain extensions to better control the device threshold voltage and further reduce the channel length.In terms of the method of fabrication of the first embodiment, starting with a GaAs substrate an n.sup.- semiconductor layer is formed in the device active region.

Abstract: The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N drain electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N Layer. The ohmic contacts for the source and drain N layers are defined several microns away from the schottky junction, resulting in a considerable improvement in device reliability.

Abstract: A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode of the field effect transistor and a collector electrode of the bipolar transistor are formed from a common electrode layer of a high impurity concentration, and in which the collector region of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type the same as that of the collector region of the bipolar transistor.

Abstract: A process for forming graded source/drain regions in semiconductor devices involves two ion implantation steps and an optional drive-in step. The first implantation is a low dose implant with high energy and/or low mass ions to form the deeper grading region. The second implant is a high does implant with low energy and/or high mass ions to form the shallower, lower resistivity source/drain region. Without the optional drive-in step, virtually no lateral grading takes place, resulting in little encroachment of the grading region under the gate. The use of a drive-in step between the two implant steps causes diffusion of the grading dopant, which increases the grading both laterally and vertically, resulting in better breakdown and capacitance characteristics, but increased encroachment under the gate. The present invention allows control over the lateral and vertical grading separately to optimize the trade-offs for a particular application.

Abstract: A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.

Abstract: A method of improving the integrity of silicon dioxide is disclosed. As applicable, for example, to the formation of oxide regions in an integrated circuit (such as thin, gate oxides) an implantation of nitrogen ions is performed prior to high temperature processing steps of the circuit fabrication. High temperature steps then result in silicon-nitrogen compounds being formed at the interfaces of the silicon dioxide regions with subjacent and superjacent regions of the integrated circuit structure. These compounds prevent the incursion of impurities into the silicon dioxide which would degrade its quality.

Abstract: The present invention relates to a CMOS structure, and method for forming the same, which prevents latchup in MOS devices. The method is directed to the CMOS structure and functions to reduce the lateral resistance of the n-tub, where the presence of a large lateral resistance in the n-tubs of prior art arrangements, has been found to cause latchup. A retrograde n.sup.+ region is formed at a predetermined location in the n-tub using proton bombardment to increase the n-type donor concentration at this predetermined location in the n-tub and thus significantly reduce the lateral resistance associated with the n-tub. By reducing this resistance, the parasistic SCR action between the two types of bipolar devices will be lessened, since the lower resistance of the n-tub reduces the IR drop associated with the parasitic device located in the n-tub. A beam of hydrogen ions, or doubly ionized helium, is used as the proton source. The n.sup.

Abstract: A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up hardness of the n-channel and p-channel field effect transistors while retaining good transistor properties by incorporating a further epitaxial layer and highly doped implantation regions into a lower epitaxial layer from which the wells are generated by out-diffusion into the upper epitaxial layer. In addition to achieving optimum transistor properties, the reduced lateral diffusion provided enables a lower n.sup.+ /p.sup.+ spacing, and thus achieves a higher packing density with improved latch-up hardness.