Abstract: A process of manufacturing a semiconductor device by which a through hole such as contact hole with an obtuse opening edge can be formed in an insulation or passivation layer. At least two silicon oxynitride layers in which the nitrogen to oxygen ratio differs from each other are formed on a semiconductor substrate. The etching rate of the top layer is greater than that of the second layer from the top. The stacked silicon oxynitride layers are then selectively etched to form a through hole with an obtuse opening edge.

Abstract: The combined use of an angularly deposited mask with a subsequent angular conductivity conversion operation extending partially under the mask permits both shorter dimensions and the ability to accommodate the straggle location change when subsequent processing steps occur. The mask is deposited at a low angle with respect to a planar surface, a subsequent conductivity conversion, such as ion implantation, extends under the mask, the mask is removed and a smaller gate is positioned in its location, the gate being smaller than the distance from the source to the point where the conversion extended under the mask, providing thereby an ultra-short gate FET.

Abstract: A method for manufacturing a CMOS circuit wherein a process sequence matched to an n-tub manufacture is carried out. Short-channel properties of n-channel transistors are improved by performing double boron implantations of the channel regions. A single channel implantation is executed for both transistor types. Compared to traditional CMOS processes in n-tub structure, this eliminates involved masking steps. Also, the polysilicon gate is shielded from the boron ion implantation by means of a masking re-oxidation step and the under-diffusion given n-channel and p-channel transistors is greatly reduced by means of pull-back of the boron source/drain implantation. This contributes significantly to a symmetrical U.sub.T behavior of the transistors and to the attainment of high switching speeds. The method is used in the manufacture of VLSI CMOS circuits in VLSI technology.

Abstract: An improved method for forming complementary wells in a substrate is disclosed. A polysilicon layer is applied to the substrate, and the polysilicon layer is doped. An oxidation barrier layer is applied over the doped polysilicon layer. A portion of the doped polysilicon and oxidation layers are removed to expose a well region of one conductivity type in the substrate, and the well is then implanted in the exposed region. The surface of the well, and the polysilicon layer proximate the well beneath the oxidation barrier layer, are then steam oxidized until the lateral desired oxide penetration into the polysilicon layer beneath the oxidation barrier layer has been reached. This forms an oxide masking layer covering and extending beyond the formed well. The remaining oxide barrier layer is then removed to expose a well region of the other conductivity type. This second well region is spaced from the well region already formed by the extended oxide masking layer. The second well is then implanted.