With Cooling Means Patents (Class 174/252)
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Patent number: 12211629Abstract: A contact system includes a support body, a heat sink configured to contact the support body in an electrically insulated and/or heat-conducting manner, and an electrically insulating layer arranged between the heat sink and the support body. The heat sink has a first surface which is embodied substantially as a flat area and formed with a recess in a region intended for contacting a periphery of a contact area of the support body. The recess forms an unbroken track on the first surface of the heat sink. The contact area of the support body is located on the heat sink in such a way that the recess extends completely along the periphery of the contact area. The insulating layer between the heat sink and the support body is configured to cover the recess in such a way that a closed channel is formed by the recess and the insulating layer.Type: GrantFiled: July 14, 2021Date of Patent: January 28, 2025Assignee: Siemens AktiengesellschaftInventors: Volker Müller, Stephan Neugebauer
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Patent number: 12177966Abstract: Provided are a light board, a method for manufacturing the same, a light-emitting diode (LED) backlight module and an LED backlight device. The light board includes a substrate and a LED device. The substrate includes a first surface and a second surface disposed opposite to each other. The first surface and the second surface are each provided with a wiring area and a non-wiring area. A first heat sink assembly and multiple first reinforcement ribs are disposed in the non-wiring area of the first surface. The multiple first reinforcement ribs intersect to form a first encircled area. The first heat sink assembly is disposed in the first encircled area. The LED device is disposed in the wiring area of the second surface.Type: GrantFiled: December 30, 2022Date of Patent: December 24, 2024Assignee: FOSHAN NATIONSTAR OPTOELECTRONICS CO., LTD.Inventors: Xinghan He, Danlei Gong, Zhonghai Yan, Hua Fan, Fabo Liu, Youwei Zhan, Weineng Chen, Taotao Song
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Patent number: 12165950Abstract: A power semiconductor component includes at least one power semiconductor device disposed within a housing and a heat sink having an area a exposed on a first surface of the housing. A wiring substrate has a first main surface and a second main surface. A heat dissipation region with increased thermal conductivity is disposed on the second main surface. The heat dissipation region has an area A on the second main surface, and a<A. The housing with the power semiconductor device is disposed on the second main surface of the wiring substrate in such a way that the heat sink is disposed completely on the heat dissipation region and is connected thereto by way of a solder layer. A method for producing a power semiconductor component is also provided.Type: GrantFiled: October 6, 2020Date of Patent: December 10, 2024Assignee: Vitesco Technologies GmbHInventors: Christina Quest-Matt, Detlev Bagung, Daniela Wolf
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Patent number: 11935813Abstract: A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates.Type: GrantFiled: July 1, 2021Date of Patent: March 19, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventors: Ryoichi Kato, Tatsuhiko Asai, Kento Shirata
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Patent number: 11882646Abstract: A wiring module according to an embodiment of the present technology includes: a wiring board and a heat dissipation member. The wiring board includes a body portion and one or more heat dissipation vias, the body portion including a front surface layer to which a device package is connected and a rear surface layer opposite to the front surface layer, the one or more heat dissipation vias penetrating the body portion from the front surface layer to the rear surface layer. The heat dissipation member is connected to the rear surface layer so as to thermally bond with the one or more heat dissipation vias.Type: GrantFiled: July 2, 2020Date of Patent: January 23, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Yutaro Yamashita
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Patent number: 11792924Abstract: Provided is a printed circuit board using thermally and electrically conductive layer, and a manufacturing method thereof. The manufacturing method for mounting a plurality of elements includes forming an electrode layer on a substrate of a PCB, forming a photo solder resist (PSR) layer in a patterned manner on a first area of the electrode layer; forming a conductive layer on the PSR layer in the patterned manner, the conductive layer being configured to conduct heat and static electricity; and mounting a plurality of elements on a second area of the side of the PCB, the second area being different from the first area.Type: GrantFiled: May 13, 2021Date of Patent: October 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taehyeun Ha, Taeje Park
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Patent number: 11665813Abstract: A power electronics module includes a heat sink structurally configured to dissipate thermal energy, an electrically-insulating layer directly contacting the heat sink, a conductive substrate positioned on and in direct contact with the electrically-insulating layer, a power electronics device positioned on and in direct contact with the conductive substrate, a printed circuit board layer that at least partially encapsulates the conductive substrate and the power electronics device, and a driver circuit component positioned on a surface of the printed circuit board layer.Type: GrantFiled: August 14, 2020Date of Patent: May 30, 2023Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Feng Zhou, Shohei Nagai
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Patent number: 11611014Abstract: A light-emitting module includes (i) a board provided with: a circuit pattern and a plurality of bottomed holes in each of a set of wiring pads continuous with the circuit pattern on a first surface; electrically conductive paste extending over two or more of the bottomed holes; and an insulating resin covering the electrically conductive paste at a side close to the first surface, and (ii) a plurality of light-emitting segments connected to a second surface of the board with an adhesive sheet interposed therebetween. The light-emitting segments each include a plurality of light-emitting devices that are aligned. The electrically conductive paste includes a portion disposed on a portion of a surface of the wiring pad extending over two or more of the bottomed holes.Type: GrantFiled: January 20, 2022Date of Patent: March 21, 2023Assignee: NICHIA CORPORATIONInventors: Eiko Minato, Koji Taguchi, Yumiko Kameshima, Masaaki Katsumata
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Patent number: 11503698Abstract: A flexible circuit board includes a flexible substrate, an electronic component and a heat spreader. The electronic component and the heat spreader are disposed on a top surface and a bottom surface of the flexible substrate, respectively. The heat spreader includes a copper layer which contains more than or equal to 50% copper grains by volume with (1,0,0) crystallographic orientation.Type: GrantFiled: October 5, 2021Date of Patent: November 15, 2022Assignee: Chipbond Technology CorporationInventors: Yi-Ling Hsieh, Pei-Ying Lee, Dong-Sheng Li
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Patent number: 11398447Abstract: A semiconductor device includes an insulating substrate formed by integrating a ceramic base plate and a cooling fin; a multiple of plate interconnection members; and a plurality of semiconductor elements. The one faces of the semiconductor elements are bonded to the ceramic base plate of the insulating substrate with a chip-bottom solder, and the other faces thereof are bonded to the plate-interconnection members with a chip-top solder so that plate interconnection members correspond respectively to the semiconductor elements. The chip-bottom solder and the chip-top solder both contain mainly Sn and 0.3-3 wt. % Ag and 0.5-1 wt. % Cu. This allows the semiconductor device to be reduced in size without impairing heat dissipation.Type: GrantFiled: November 29, 2018Date of Patent: July 26, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shohei Ogawa, Junji Fujino, Satoru Ishikawa, Takumi Shigemoto, Yusuke Ishiyama
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Patent number: 11393737Abstract: A heatsink (21) is disposed on a lower surface of a circuit board (10). The circuit board (10) has through holes (h1) that penetrate the circuit board (10) in an area (A) where an integrated circuit apparatus (5) is disposed. Heat conduction paths (11) are provided in the through holes (h1). The heat conduction paths (11) connect the integrated circuit apparatus 5 and the heatsink (21). This structure allows for disposition of a component different from the heatsink (21) on the same side as the integrated circuit apparatus (5), thus ensuring a higher degree of freedom in a component layout.Type: GrantFiled: May 18, 2018Date of Patent: July 19, 2022Assignee: Sony Interactive Entertainment Inc.Inventors: Kazuyuki Shikama, Morio Usami
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Patent number: 11365490Abstract: A method of manufacturing a thermal cutting element for a surgical instrument includes manufacturing a substrate, coating at least a portion of the substrate via Plasma Electrolytic Oxidation (PEO), and disposing a heating element on at least a portion of the PEO-coated substrate. The method may further include attaching the thermal cutting element to a jaw member of a surgical instrument.Type: GrantFiled: November 23, 2020Date of Patent: June 21, 2022Assignee: Covidien LPInventors: William Robinson, James D. Allen, IV, Mark A. Johnston, Brendan J. Heinig, Hector A. MacPherson
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Patent number: 11310912Abstract: High-current circuit having a printed circuit board comprising a non-conductive substrate 2, a conductor layer 4 applied to the substrate 2 and an insulation layer 6 applied to the conductor layer, contact pads 8, 10, 12, 20, 22, 24 in each case interrupting the insulation layer 6 being arranged on both sides of the conductor plate, and the contact pads 8, 10, 12, 20, 22, 24 making contact with one another via vias 14 through the substrate 2, and the vias 14 being arranged in the area of the contact pads 8, 10, 12, 20, 22, 24, 10, 12, 20, 22, 24, characterized in that at least a first one of the contact pads 8 is arranged on a first side of the printed circuit board and a first semiconductor switch 28 is connected directly to at least a second one of the contact pads 20 on a second side of the printed circuit board, and in that the semiconductor switch 28 is connected to the first contact pad 8 directly via the vias 14 and the second contact pad 20, without further conductor tracks.Type: GrantFiled: October 1, 2019Date of Patent: April 19, 2022Assignee: Auto-Kabel Management GmbHInventors: Udo Kratzer, David Cacciatore
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Patent number: 11284502Abstract: A multi-layer printed circuit board (PCB) has a bonding surface disposed on a first surface and a first thermal relief pad disposed on the first surface and surrounding the bonding surface. A first conductive plane on the first surface partially surrounds the first thermal relief pad. The first conductive plane is connected to the bonding surface by one or more first spokes. A second thermal relief pad is disposed on the first surface and partially surrounds the first conductive plane. A second conductive plane is disposed on the first surface and surrounds the second thermal relief pad. The second conductive plane is connected to the first conductive plane by one or more second spokes. A through hole is located in the bonding surface for receiving an electrical connector of an electronic component.Type: GrantFiled: February 11, 2020Date of Patent: March 22, 2022Assignee: Western Digital Technologies, Inc.Inventors: Chun Sean Lau, Choon Kuai Lee, Ing Chyuan Ooi
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Patent number: 11234343Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device, and at least one unidirectional heat transfer device between the first integrated circuit device and the second integrated circuit device. In one embodiment, the unidirectional heat transfer device may be oriented such that it has a higher conductivity in the direction of heat transfer from the first integrated circuit device to the second integrated circuit device than it does in the opposite direction. When the temperature of the second integrated circuit device rises above the temperature of the first integrated circuit device, the unidirectional heat transfer device will act as a thermal insulator, and when the temperature of the first integrated circuit device rises above the temperature of the second integrated circuit device, the unidirectional heat transfer device will act as a thermal conductor.Type: GrantFiled: May 3, 2018Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Feras Eid, Adel Elsherbini, Johanna Swan
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Patent number: 11206747Abstract: A heat release device includes a housing, a substrate located within the housing, a heat source disposed on the substrate, a first member provided between the housing and the substrate and between the housing and the heat source, and a plurality of second members that support the first member from the substrate. The first member is disposed to have a gap with the heat source and so as to have a gap with the housing. Among the plurality of second members, a second member far from the heat source is larger in area in contact with the substrate and the first member than a second member close to the heat source.Type: GrantFiled: September 25, 2020Date of Patent: December 21, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Taku Ueno
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Patent number: 11171071Abstract: A power module includes: a plate-shaped thick copper substrate, a conductive stress relaxation metal layer disposed on the thick copper substrate, a semiconductor device disposed on the stress relaxation metal layer, and a plated layer disposed on the stress relaxation metal layer, wherein the semiconductor device is bonded to the stress relaxation metal layer via the plated layer. The thick copper substrate includes a first thick copper layer and a second thick copper layer disposed on the first thick copper layer, and the stress relaxation metal layer is disposed on the second thick copper layer. A part of the semiconductor device is embedded to be fixed to the stress relaxation metal layer. A bonded surface between the semiconductor device and the stress relaxation metal layer are integrated to each other by means of diffusion bonding or solid phase diffusion bonding.Type: GrantFiled: August 15, 2019Date of Patent: November 9, 2021Assignee: ROHM CO., LTD.Inventors: Maiko Hatano, Takukazu Otsuka
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Patent number: 11166396Abstract: Provided is a box-type vehicle-mounted control device that effectively increases the amount of heat transfer from electronic components and a circuit board to a casing (base and cover) and that accordingly has achieved excellent heat dissipation property. The box-type vehicle-mounted control device includes a circuit board 12, a base 13, and a cover 14. In addition, a first heat radiating coating layer 31 is formed on at least one surface of the circuit board 12, and a second heat radiating coating layer 32 is formed on an inner surface of one or both of the base 13 and the cover 14 facing the first heat radiating coating layer 31.Type: GrantFiled: May 12, 2014Date of Patent: November 2, 2021Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Maki Ito, Toshiaki Ishii, Masaru Kamoshida, Hideto Yoshinari, Masato Saito, Akitoyo Konno
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Patent number: 11160197Abstract: A heat dissipation unit includes a main body having a first and a second plate member, which are closed to each other to together define an airtight chamber in between them. A working fluid is filled in the airtight chamber, and a first wick structure layer and a holding-down thin layer are provided between the first and the second plate member and superimposed in the airtight chamber. With the holding-down thin layer and the first wick structure layer being superimposed in the airtight chamber, the first wick structure layer is closely and flatly attached to the second plate member without warping.Type: GrantFiled: August 5, 2018Date of Patent: October 26, 2021Assignee: ASIA VITAL COMPONENTS CO., LTD.Inventors: Kuo-Chun Hsieh, Wei-Te Wu
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Patent number: 11160168Abstract: A wiring board for a built-in electronic component includes a first insulating layer, a second insulating layer formed under the first insulating layer, and a conductor layer formed on an upper surface of the second insulating layer such that a cavity is formed to penetrate through the first insulating layer and the conductor layer and expose the second insulating layer at a bottom of the cavity and is formed to accommodate an electronic component therein. The first insulating layer and the conductor layer are formed such that the cavity has a first inner side surface extending from an upper opening edge to a position closer to the second insulating layer, and a lateral expansion part formed between a lower edge of the first inner side surface and the second insulating layer and extending outward from the lower edge of the first inner side surface.Type: GrantFiled: May 11, 2020Date of Patent: October 26, 2021Assignee: IBIDEN CO., LTD.Inventors: Yusuke Tanaka, Tomohiro Futatsugi, Yuichi Nakamura, Yoshiki Matsui
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Patent number: 11152280Abstract: A semiconductor device includes a power module unit, a fin base, and a plurality of radiator fins. The power module unit and the fin base are integrated together, with a recess-projection portion formed on the power module unit being fitted to a recess-projection portion formed on the fin base. The plurality of radiator fins are integrally fitted on a heat radiation diffusion portion of the fin base.Type: GrantFiled: November 16, 2017Date of Patent: October 19, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasuyuki Sanda, Dai Nakajima, Haruna Tada, Hodaka Rokubuichi, Kiyofumi Kitai
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Patent number: 11140780Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a networking card arrangement with increased thermal performance. An example arrangement includes a primary network card that defines a first card-to-board connection and a networking chipset supported by the primary network card. The arrangement also includes an auxiliary network card that defines a second card-to-board connection and networking cable connectors supported by the auxiliary network card that receive networking cables therein. The arrangement further includes a card connection element that operably connects the primary network card and the auxiliary network card. In an operational configuration in which the primary network card and the auxiliary network card are received by a server board via the first card-to-board connection and the second card-to-board connection, the primary network card is spaced from the auxiliary network card such that air may pass therebetween.Type: GrantFiled: June 8, 2020Date of Patent: October 5, 2021Assignee: Mellanox Technologies, Ltd.Inventors: Avraham Ganor, Ariel Naftali Cohen, Assad Khamaisee, Andrey Blyahman, Doron Fael, Sergey Savich
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Patent number: 11128062Abstract: A folded outer tab comprises a first outer dielectric layer and a second outer dielectric layer that contact or overlie an outer terminal, where the outer terminal is associated with a first polarity of the DC bus. A bent inner tab comprises a first inner dielectric layer and a second inner dielectric layer that contact or overlie an inner terminal, where the inner terminal is associated with a second polarity of the DC bus that is opposite the first polarity. The folded outer tab and the bent inner tab comprise electrically conductive faces, of opposite polarities, formed of exposed portions of the outer terminal and the inner terminal.Type: GrantFiled: December 5, 2019Date of Patent: September 21, 2021Inventor: Christopher J. Schmit
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Patent number: 11110549Abstract: A recess or through-hole forming method for forming a substrate with a recess or a through-hole along a thickness direction of the substrate, the method including: a modified region forming step of applying a laser beam of such a wavelength as to be transmitted through the substrate to the substrate, with a focal region of the laser beam positioned inside the substrate, to form a column-shaped modified region which is exposed to a surface of the substrate and extends along the thickness direction of the substrate; and an etching step of etching the modified region to form the substrate with the recess or the through-hole, after the modified region forming step is performed.Type: GrantFiled: December 11, 2018Date of Patent: September 7, 2021Assignee: DISCO CORPORATIONInventors: Kazuma Sekiya, Naoki Murazawa
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Patent number: 11114361Abstract: Electronics assemblies and methods of manufacturing electronics assemblies having improved thermal performance. One example of these electronics assemblies includes a printed circuit board (PCB), an integrated circuit package mounted to the PCB, the integrated circuit packing having a heat generating component, and a heat spreader soldered to the PCB such that the heat spreader is thermally coupled to the heat generating component of the integrated circuit package to dissipate heat generated by the heat generating component.Type: GrantFiled: August 7, 2019Date of Patent: September 7, 2021Assignee: INTELLIGENT PLATFORMS, LLCInventor: Bernd Sporer
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Patent number: 11107745Abstract: A semiconductor device includes a power module unit, a fin base, and a plurality of radiator fins. The power module unit and the fin base are integrated together, with a recess-projection portion formed on the power module unit being fitted to a recess-projection portion formed on the fin base. The plurality of radiator fins are integrally fitted on a heat radiation diffusion portion of the fin base.Type: GrantFiled: November 16, 2017Date of Patent: August 31, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yasuyuki Sanda, Dai Nakajima, Haruna Tada, Hodaka Rokubuichi, Kiyofumi Kitai
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Patent number: 11043440Abstract: A semiconductor package includes a semiconductor chip having an active surface, on which a connection pad is disposed, and an inactive surface disposed to oppose the active surface, a heat dissipation member, disposed on the inactive surface of the semiconductor chip, having a plurality of holes and including a graphite-based material, an encapsulant covering at least a portion of each of the semiconductor chip and the heat dissipation member, and a connection member, disposed on the active surface of the semiconductor chip, including a redistribution layer electrically connected to the connection pad. 0<b<0.6a, in which “a” denotes a planar area of the heat dissipation member and “b” denotes a sum of planar areas of the plurality of holes on a plane.Type: GrantFiled: September 11, 2019Date of Patent: June 22, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyung Kyu Kim, Seong Chan Park, Sang Hyun Kwon, Han Kim, Seung On Kang
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Patent number: 11037860Abstract: A multi-layer thermal interface material including two or more thermal interface materials laminated together, where each of the two or more thermal interface materials comprise different mechanical properties.Type: GrantFiled: June 27, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Mark K. Hoffmeyer, Eric J. Campbell, Phillip V. Mann, Sarah K. Czaplewski-Campbell
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Patent number: 11013102Abstract: A printed circuit board includes a printed wiring board, an electronic element provided on a mounting surface of the printed wiring board, and a heat radiation member provided on an opposite side of a side on which the printed wiring board is positioned with respect to the electronic element, the heat radiation member thermally connected to the electronic element. An end portion of the heat radiation member is disposed closer to the printed wiring board than a connection portion with the electronic element in the heat radiation member, in a state where a space is provided between the end portion and the printed wiring board.Type: GrantFiled: August 13, 2020Date of Patent: May 18, 2021Assignee: SEIKO EPSON CORPORATIONInventor: Naoki Suematsu
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Patent number: 11004826Abstract: A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.Type: GrantFiled: July 16, 2018Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen
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Patent number: 11004792Abstract: Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.Type: GrantFiled: September 28, 2018Date of Patent: May 11, 2021Assignee: Intel CorporationInventor: Sri Chaitra Jyotsna Chavali
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Patent number: 10993347Abstract: An electronic device used for coupling to another electronic device in a side by side manner is disclosed, which includes: a first substrate having a first top surface and a first side surface connecting to the first top surface; a first signal line formed on the first top surface; a plurality of first electronic elements electrically connected to the first signal line; and a first conductive pattern formed on the first top surface and the first side surface, and electrically connected to the first signal line. In addition, a tiled electronic system includes the aforesaid electronic device is also disclosed.Type: GrantFiled: November 20, 2018Date of Patent: April 27, 2021Assignee: Innolux CorporationInventors: Jui-Jen Yueh, Kuan-Feng Lee
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Patent number: 10984966Abstract: A micro-electro-mechanical system (MEMS) transfer switch is disclosed. The transfer switch comprises a single-pole, N-throw switch section having N selectable switches. Each selectable switch of the N selectable switches has an input, a control terminal and an output. An electrically conductive line is coupled to each of the selectable switches of the N selectable switches. The transfer switch includes a single-pole, M-throw switch section having M selectable switches coupled to the conductive line, each selectable switch of the M selectable switches having an output, a control terminal and an input. The single-pole, N-throw switch section and the single-pole, M-throw switch section are packaged in a single micro-electro-mechanical system (MEMS) die. The N and M are numbers between two and eight and the N selectable switches and the M selectable switches are different switches.Type: GrantFiled: April 2, 2020Date of Patent: April 20, 2021Assignee: LOCKHEED MARTIN CORPORATIONInventors: Lowell Kent Sherman, Bryan Charles Gundrum, Steve Todd Nicholas
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Patent number: 10978369Abstract: A device for absorbing energy from an electronic component includes a low melting alloy layer including a first side and a second side opposing the first side, and coating layers substantially covering the first side and the second side of the low melting alloy layer. In some embodiments, the low melting alloy layer includes a polymer mixture and a plurality of low melting alloy particulates dispersed in the polymer mixture. Other example devices are also disclosed.Type: GrantFiled: October 21, 2019Date of Patent: April 13, 2021Assignee: Laird Technologies, Inc.Inventors: Jason L. Strader, Eugene Anthony Pruss
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Patent number: 10980129Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.Type: GrantFiled: March 16, 2020Date of Patent: April 13, 2021Assignee: Intel CorporationInventors: Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur, Wei-Lun Kane Jen, Sriram Srinivasan
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Patent number: 10973153Abstract: The present disclosure provides a power module including a circuit board, a first heat-generating component and a second heat-generating component. The circuit board includes a first side and a second side opposite to each other and includes a first plane and second plane disposed on the first side. A first height difference is formed between the first plane and the second plane. The first heat-generating component and the second heat-generating component are disposed on the first plane and the second plane, respectively. The first heat-generating component and the second heat-generating component include a first contact surface and a second contact surface, respectively. The first contact surface and the second contact surface are located at a first collaborative plane of the power module. It benefits to reduce the design complexity of a heat sink, and enhance the heat dissipation capability and the overall power density of the power module simultaneously.Type: GrantFiled: November 21, 2019Date of Patent: April 6, 2021Assignee: DELTA ELECTRONICS, INC.Inventors: Wenhua Li, Xueliang Chang, Yahong Xiong, Qinghua Su
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Patent number: 10958055Abstract: A circuit assembly includes a busbar substrate with busbars and a resin part that is in intimate contact with the busbars, a press-fit member that is made of metal with a thickness greater than the thickness of the busbars, and is press-fitted in the busbar substrate, an electronic component connected to the press-fit member, solder that connects the busbars and the press-fit member, and a solder accumulating portion that is formed with the resin part, and in which the solder is accumulated.Type: GrantFiled: December 13, 2017Date of Patent: March 23, 2021Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.Inventors: Koki Uchida, Yukinori Kita
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Patent number: 10955881Abstract: An electronic memory module can be cooled by a cooling assembly that consists of at least a printed circuit board connected to at least one data storage component. The memory module may be housed within, and in physical contact with, a cooling frame that surrounds a periphery of the printed circuit board. The cooling frame can have a seating tab that is separated from the memory module, spans the memory module, and supports a heatsink in contact with the at least one data storage component.Type: GrantFiled: May 2, 2017Date of Patent: March 23, 2021Assignee: Seagate Technology LLCInventors: Shankar Gopalakrishna, Vivekananda Avvaru, Saju Cheeran Verhgese Francis
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Patent number: 10950547Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.Type: GrantFiled: March 2, 2020Date of Patent: March 16, 2021Assignee: Xcelsis CorporationInventors: Ilyas Mohammed, Steven L. Teig, Javier DeLaCruz
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Patent number: 10945332Abstract: The invention refers to a component carrier realized as a printed circuit board, an intermediate printed circuit board product or an IC-substrate, comprising at least one heat-passage component, said at least one heat-passage component being realized in form of a heat-generating or a heat-absorbing component that is mounted on an outside surface layer or is embedded within at least one inner layer of the component carrier, and further comprising at least one latent-heat storage unit with a phase-change material. The phase-change material is arranged within at least one cavity and integrated within a laminated build-up of the component carrier and is directly thermoconductively coupled with the at least one heat-passage component. The invention also refers to a method for producing said component carrier.Type: GrantFiled: April 27, 2017Date of Patent: March 9, 2021Assignee: AT&S Austria Technologie & Systemtechnik AktiengesellschaftInventor: Jonathan Silvano De Sousa
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Patent number: 10925148Abstract: A printed circuit board assembly is provided. A printed circuit board assembly includes a printed circuit board; an electronic component mounted on the printed circuit board; a heat radiating member which contacts the electronic component and is configured to receive and conduct heat generated by the electronic component; and at least one connection part connecting the printed circuit board and the heat radiating member to each other and configured to transfer the heat conducted through the heat radiating member to the printed circuit board.Type: GrantFiled: July 31, 2017Date of Patent: February 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-hun Kang, In-beom Kim, Bo-ram Kim, Soo-hong Kim
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Patent number: 10917962Abstract: The reliability of an electronic device is improved. An electronic device has a wiring substrate and a housing made of a metal for supporting the wiring substrate. A semiconductor device having a switching power transistor is mounted at the wiring substrate. A ground pattern of a conductive film and a heat radiation pattern of a conductive film are formed at the wiring substrate. The heat radiation pattern is not electrically coupled with any electronic component mounted at the wiring substrate, and is also not electrically coupled with the ground pattern. The ground pattern overlaps the semiconductor device in the thickness direction of the wiring substrate. The heat radiation pattern overlaps the ground pattern in the thickness direction of the wiring substrate, and overlaps a region where the housing and the wiring substrate are in contact with each other.Type: GrantFiled: July 9, 2018Date of Patent: February 9, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Norikazu Motohashi, Shinji Nishizono
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Patent number: 10912186Abstract: A printed board includes an insulating layer, and radiation vias penetrating printed board are formed in both a first region overlapping electronic component and a second region outside the first region. A plurality of conductor layers included in printed board are cross-connected to a plurality of radiation vias. Diffusion radiator includes a thermal diffusion plate, a radiation member, and a cooling body. Radiation member is in close contact with one of main surfaces of cooling body, and thermal diffusion plate is in close contact with one of main surfaces of radiation member on the opposite side to cooling body. One of main surfaces of thermal diffusion plate on the opposite side to radiation member is bonded to a conductor layer on the other main surface of printed board so as to close the plurality of radiation vias.Type: GrantFiled: November 28, 2016Date of Patent: February 2, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shota Sato, Tsuneo Hamaguchi, Yuji Shirakata, Kenta Fujii
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Patent number: 10892252Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.Type: GrantFiled: March 2, 2020Date of Patent: January 12, 2021Assignee: XCELSIS CORPORATIONInventors: Eric M. Nequist, Steven L. Teig, Javier DeLaCruz, Ilyas Mohammed, Laura Mirkarimi
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Patent number: 10880992Abstract: A circuit board structure including a dielectric substrate having a plurality of vias, a first conductor layer, a second conductor layer, an insulating layer, and a third conductor layer. The first and the second conductor layers are disposed at opposite surfaces of the dielectric substrate. The first conductor layer forms a plurality of traces including at least one high-speed differential pair and a plurality of ground traces, wherein the vias are located on the ground traces. The electric insulated layer is disposed on the dielectric substrate and covers the first conductor layer, and the third conductor layer is disposed on the insulating layer.Type: GrantFiled: July 26, 2019Date of Patent: December 29, 2020Assignee: Advanced Connectek Inc.Inventors: Min-Lung Chien, Mao-Sheng Chen, Wen-Yu Wang
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Patent number: 10842045Abstract: A heat dissipation device comprises a generally rectangular metal cooling plate; the metal plate comprises, on its upper face, first attachment means for attaching a first printed circuit board, which means are provided for bringing at least one heat-generating zone of the first printed circuit board to bear with the upper face of the plate; the metal plate comprises, on its lower face, second attachment means for attaching a second printed circuit board, which means are provided for bringing at least one heat-generating zone of the second printed circuit board to bear with the lower face of the plate.Type: GrantFiled: December 7, 2017Date of Patent: November 17, 2020Assignee: Aptiv Technologies LimitedInventors: Grzegorz Szostek, Marcin Hyrlicki, Krzysztof Adamczyk, Pawel Brache
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Patent number: 10840425Abstract: Methods and systems for thermal management of one or more LEDs are disclosed. One or more LEDs may be coupled with an external layer of a thermal ground plane according to some embodiments described herein. For example, the one or more LEDs may be electrically coupled with a circuit carrier with one or more electrically conductive traces etched therein prior to coupling with the thermal ground plane. The thermal ground plane may be charged with a working fluid and/or hermetically sealed after being coupled with the LED.Type: GrantFiled: September 21, 2017Date of Patent: November 17, 2020Assignee: Roccor, LLCInventors: William Francis, Michael Hulse
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Patent number: 10782749Abstract: A circuit assembly is provided which makes efficient us of space provided on a main board having a CPU and a supporting board which is designed to have a network interface chip (NIC). The circuit assembly further has a cooling plate situated between the two boards, which is optimized to provide efficient cooling operations. The circuit assembly is part of a blade, which includes a housing to contain and support all necessary components. The space within the blade housing is efficiently used, so that processing, communication and cooling operations are all optimized.Type: GrantFiled: October 10, 2018Date of Patent: September 22, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Wendell Lengefeld, Abhishek Mehta, William Mark Megarity, Mark E. Steinke, Benjamin Colin Heshmat
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Patent number: 10784198Abstract: A semiconductor integrated circuit including a substrate, a series of metal layers, and a series of insulating layers. The metal layers and the insulating layers are alternately arranged in a stack on the substrate. The semiconductor integrated circuit also includes at least two standard cells in the substrate and at least one power rail crossing over boundaries of the at least two standard cells. The power rail includes a vertical section of conductive material extending continuously through at least two vertical levels of the stack. The two vertical levels of the stack include one metal layer and one insulating layer. The insulating layer is above the metal layer.Type: GrantFiled: August 18, 2017Date of Patent: September 22, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Rwik Sengupta, Andrew Paul Hoover, Matthew Berzins, Sam Tower, Mark S. Rodder
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Patent number: 10772205Abstract: A structure, a semiconductor device and a manufacturing method thereof are provided. The structure includes a core layer and a build-up stack disposed on the core layer. The core layer includes a first core dielectric layer, a second core dielectric layer, through vias, and a patterned conductive plate. The second core dielectric layer is disposed on the first core dielectric layer. The through vias cross the first core dielectric layer and the second core dielectric layer. The patterned conductive plate is disposed on the first core dielectric layer and is electrically insulated from the through vias. The build-up stack includes interconnected conductive patterns electrically connected to the through vias. A bottom surface of the patterned conductive plate is coplanar with an interface of the first core dielectric layer and the second core dielectric layer.Type: GrantFiled: February 26, 2019Date of Patent: September 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiun-Yi Wu, Chien-Hsun Lee, Chen-Hua Yu, Chung-Shi Liu