Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
  • Patent number: 11026334
    Abstract: A method for producing a wired circuit board including an insulating layer and a conductive pattern, including (1), providing the insulating layer having an inclination face; (2), providing a metal thin film at least on the surface of the insulating layer; (3), providing a photoresist on the surface of the metal thin film; (4), disposing a photomask so that a first portion, where the conductive pattern is provided in the photoresist, is shielded from light, and the photoresist is exposed to light through the photomask; (5), removing the first portion to expose the metal thin film corresponding to the first portion; and (6), providing the conductive pattern on the surface of the metal thin film exposed from the photoresist. The inclination face has a second portion that allows the light reflected at the metal thin film to reach the first portion.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: June 1, 2021
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Hiroyuki Tanabe, Yoshito Fujimura
  • Patent number: 11026356
    Abstract: An electrical device comprises a printed circuit board, a first contact portion, a second contact portion, a first conductive wall and a second conductive wall. The printed circuit board has a first surface and a second surface, on which the first contact portion and the second contact portion are disposed, respectively. The first conductive wall and the second conductive wall are in electrical contact with the first contact portion and the second contact portion, respectively. The first contact portion and the second contact portion are offset from one another in a direction parallel to at least one of the first surface and the second surface.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 1, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Marc Soler, Javier Gonzalez, Jordi Oriol
  • Patent number: 11015740
    Abstract: A support member-attached wire harness includes a wire harness including an electrical wire and a support member that includes a fitting portion formed in a partially cylindrical shape that is opened partially in a circumferential direction so as to be capable of being fitted to an outer peripheral portion of a bar-shaped member. On at least one of the wire harness and the support member, a support portion for supporting the wire harness disposed along an outer periphery of the fitting portion at a fixed position with respect to the fitting portion is formed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: May 25, 2021
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Haruka Nakano, Shigeki Ikeda, Daisuke Fukai, Tetsuya Nishimura, Motohiro Yokoi, Housei Mizuno, Takashi Ide, Daiki Nagayasu, Daisuke Ebata
  • Patent number: 11016620
    Abstract: A touchscreen panel includes a substrate, a conductive layer disposed in a predetermined pattern on the substrate, and an insulating layer disposed on the conductive layer. The insulating layer includes grooves recessed in a surface of the insulating layer. The grooves include first grooves and the second grooves. The first grooves extend in a first direction. The second grooves are arranged in line in a second direction intersecting the first direction. The second grooves are recessed to the conductive layer. The first and the second grooves are filled with conductive materials. The conductive materials in the first grooves form first lines. The conductive materials in the second grooves form second lines. The first lines are configured for detection of a position of touch in the second direction. The second lines are configured for detection of a position of the touch in the first direction.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 25, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takatoshi Kira, Mikihiro Noma
  • Patent number: 11019729
    Abstract: The device intended to be thermoformed comprises a substrate capable of being thermoformed and an electrically conductive member integral with the said substrate. The electrically conductive member comprises: electrically conductive particles, an electrically conductive material, electrically conductive elements of elongated shape. The electrically conductive material has a melting point which is strictly less than the melting point of the electrically conductive particles and than the melting point of the elements of elongated shape.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 25, 2021
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Mohammed Benwadih
  • Patent number: 11013160
    Abstract: There is provided a component mounting method for mounting an electronic component provided with a connecting pin on a board having a through-hole, including inserting the pin of the electronic component into an inner hole filled with solder paste at a first electrode provided in the through-hole to execute a component mounting operation of lowering the pin to a predetermined mounting height position and pulling up the pin once inserted and lowered into the inner hole in the component mounting operation to a preset intermediate height position.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 18, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tetsuya Tanaka, Masahiko Akasaka, Koji Sakurai, Toshihiko Nagaya
  • Patent number: 10991669
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: April 27, 2021
    Assignee: MediaTek Inc.
    Inventors: Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Patent number: 10959337
    Abstract: A method for manufacturing connection structure, the method includes arranging a first composite on a first surface of a first member where a first electrode is located and arranging conductive particles on the first electrode, arranging a second composite on a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: March 23, 2021
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 10959327
    Abstract: A plate-shaped multilayer wiring substrate includes at least two resin layers stacked on top of each other and each including an insulating base and a conductive pattern provided on the insulating base, and a front surface layer joined onto the resin layers stacked. The front surface layer has a higher elastic modulus than an elastic modulus of the insulating bases. A joint interface between the resin layers and the front surface layer includes projections and depressions. Also, a method for manufacturing the plate-shaped multilayer wiring substrate includes a step of stacking, on top of resin layers, a front surface layer having a higher elastic modulus than an elastic modulus of the resin layers, and a step of performing pressing under pressure from above the front surface layer by using a flat surface in a heated state to join the resin layers and the front surface layer.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 23, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinichi Araki, Hideyuki Taguchi, Hayato Noma, Ryosuke Takada
  • Patent number: 10950517
    Abstract: A printed circuit board (PCB) includes an insulating layer with an upper surface and a lower surface opposite to the upper surface; a first conductive pattern on the upper surface of the insulating layer; a second conductive pattern on the lower surface of the insulating layer; an aluminum pattern that covers at least a portion of an upper surface of the first conductive pattern; and a first passivation layer that covers at least a portion of sides of the first conductive pattern and that prevents diffusion into the first conductive pattern.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Soo-Jae Park
  • Patent number: 10950668
    Abstract: The present application provides a display substrate, a manufacturing method thereof, and a display apparatus. The display substrate of the present invention includes a base substrate, a display unit provided on the base substrate, a color filter layer provided on the display unit, a planarization layer provided on a surface of the color filter layer distal to the display unit, and a plurality of first electrodes and a plurality of second electrodes provided in the planarization layer. The planarization layer includes a first planarization layer and a second planarization layer, the plurality of first electrode are embedded in the first planarization layer, and the plurality of second electrodes are embedded in the second planarization layer.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Huang
  • Patent number: 10949045
    Abstract: A flexible touch substrate and a touch device including the flexible touch substrate are provided. The flexible touch substrate includes a plurality of sides. Each of at least one of the plurality of sides has notches at its both ends. Each of the notches has two edges whose extension directions cross each other, and the two edges of each of the notches have a same length.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 16, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qingpu Wang, Dacheng Deng, Haitao Liu, Taofeng Xie
  • Patent number: 10943945
    Abstract: A flexible printed circuit board and method of fabrication are disclosed. The flexible printed circuit board has a flexible body with multiple segments. Each segment has multiple body contacts that are electrically isolated from body contacts of each other segment. The flexible printed circuit further has multiple flexible legs in which each leg extends from a different segment and contains multiple leg contacts disposed proximate to a distal end of the leg from the body. Each leg contact is connected with a different body contact of the leg. The flexible printed circuit board is formed from a multilayer structure that includes: a dielectric layer, a metal layer adjacent to the dielectric layer, and a solder mask layer adjacent to the metal layer, the solder mask layer exposing portions of the metal layer to form the body contacts.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 9, 2021
    Assignee: Lumileds LLC
    Inventors: Frederic Stephane Diana, Yifeng Qiu, Michael Wasilko, Nazila Soleimani, Jeroen Den Breejen, Alan Andrew McReynolds, Gregory Donald Guth
  • Patent number: 10945334
    Abstract: A wiring substrate includes a core layer, first conductor layers including first inner, outer and intermediate conductor layers, second conductor layers including second inner, outer and intermediate conductor layers, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer, and the first and second laminated structures are formed such that a surface of the second laminated structure on a side away from the core layer has unevenness smaller than unevenness of a surface of the first laminated structure on a side away from the core layer.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 9, 2021
    Assignee: IBIDEN CO., LTD.
    Inventors: Takenobu Nakamura, Takahiro Yamazaki, Takashi Yamauchi, Toshihide Makino
  • Patent number: 10939543
    Abstract: An apparatus is provided including a transformer including a first printed circuit board having one or more conducting layers, the one or more conducting layers forming, at least in part, a transformer coil; at least one inductor; and at least one continuous piece of conducting material external to the printed circuit board, where the at least one continuous piece of conducting material forms a connection between the transformer and the at least one inductor. A method is also provided for assembling a switched-mode power supply.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Paul W Coteus, Andrew Ferencz, Todd Takken, Yuan Yao, Xin Zhang
  • Patent number: 10912201
    Abstract: Provided is an electronic device capable of supplying large current to a circuit pattern, without employing a thick film structure for the circuit pattern. The electronic device includes a substrate, a wiring layer placed on the upper surface of the substrate, an electronic component mounted above the wiring layer, and a bonding layer placed between the electronic component and the wiring layer. The wiring layer and the bonding layer are porous layers containing pores. The bonding layer has higher volume density than the wiring layer except underneath the electronic component.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: February 2, 2021
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Akihiko Hanya, Tsukasa Imura
  • Patent number: 10902974
    Abstract: A transparent conductive film is disclosed. The transparent conductive film includes a substrate and a first silver nanowire layer. The transparent conductive film has a first absorption peak at 340 nm to 400 nm and a second absorption peak at 500 nm-650 nm, and a ratio of a maximum peak intensity of the first absorption peak to a maximum peak intensity of the second absorption peak is in a range of 2 to 5.5.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: January 26, 2021
    Assignee: Cambrios Film Solutions Corporation
    Inventors: Yung-Cheng Chang, Min-Yu Chen, Yu-Wei Hou, Chung-Chin Hsiao
  • Patent number: 10891011
    Abstract: A touch sensor includes a substrate layer, sensing electrodes on the substrate layer, and optical compensation patterns. The sensing electrodes include electrode lines therein which extend in different directions to cross each other. The sensing electrodes are defined by separation regions at which portions of the electrode lines are cut. The optical compensation patterns are disposed at a different level or a different plane from that of the sensing electrodes. The optical compensation pattern at least partially fills the separation regions in a planar view. Optical properties of the touch sensor are improved by the optical compensation pattern, and visibility of electrodes is prevented.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: January 12, 2021
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Sang Jin Park, Do Hyoung Kwon, Sung Jin Noh, Han Tae Ryu, Jun Gu Lee
  • Patent number: 10879204
    Abstract: A method of forming bump structures for interconnecting components includes applying an insulating layer over a device substrate, coating the insulating layer with a dielectric material layer, forming a pattern with photolithography on the dielectric material layer, etching the dielectric material layer to transfer the pattern to the insulating layer, etching the insulating layer to form pockets in the insulating layer following the pattern, applying photolithography to and etching the dielectric material layer to reduce overhang of the dielectric material layer relative to the insulating layer, removing material from top and side walls of the pockets in the insulating layer, and depositing electrically conductive bump material in the pattern so a respective bump is formed in each pocket.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: December 29, 2020
    Assignee: Sensors Unlimited, Inc.
    Inventors: Wei Zhang, Wei Huang, Joshua Lund, Namwoong Paik
  • Patent number: 10879203
    Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10872942
    Abstract: A display device includes a substrate having a first region in which an image is displayed, a second region in which an image is not displayed, and a bending region connecting the first region and the second region. The bending region is configured to bend along a bending axis which extends in a first direction. A plurality of pad terminals is disposed within the second region. A first width of the bending region, measured along the first direction, is narrower than a second width of the second region, measured along the first direction.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 22, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae Hoon Kwon, Won Kyu Kwak, Kwang-Min Kim, Hey Jin Shin, Seung-Kyu Lee
  • Patent number: 10872864
    Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10869393
    Abstract: Examples related to the incorporation of a sensor into an electronic device are disclosed. One example provides a system including a circuit board comprising a first side and a second side opposite the first side, a sensor housed in a package bonded to the first side of the circuit board, and a mounting pedestal coupled to the circuit board on the second side at a location opposite the package, the mounting pedestal configured to be mounted to a surface in an electronic device.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: December 15, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yinan Wu, Michael S. Sutton
  • Patent number: 10869382
    Abstract: An interposer includes an insulating element body, a wiring electrode inside the element body, a signal terminal electrode at the top surface of the element body and connected to a flat cable with a conductive bonding material interposed therebetween, and a ground terminal electrode. A through-hole penetrates through the element body to allow a bar-shaped metal fixing member to be inserted. A metal fixing member connecting electrode to be electrically connected to a metal fixing member is provided at at least one of the top surface of the element body and an inner wall of the through-hole. Predetermined signal terminal electrodes are electrically connected by the wiring electrode. The ground terminal electrode and the metal fixing member connecting electrode are electrically connected.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: December 15, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirokazu Yazaki, Keito Yonemori
  • Patent number: 10863625
    Abstract: A flexible printed circuit board includes: a base material including a principal face; at least one first wiring pattern disposed on the principal face of the base material and extending along a first direction; and a first member and a second member disposed on the first wiring pattern so as to be spaced from each other in the first direction. In the first direction, the first member and the second member divide the flexible printed circuit board into: a first region located opposite to the second member with respect to the first member in the first direction, a second region located between the first member and the second member, a third region located opposite to the first member with respect to the second member, a fourth region in which the first member is disposed, and a fifth region in which the second member is disposed.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 8, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takumi Nagamine, Yoichi Kitamura
  • Patent number: 10860044
    Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: December 8, 2020
    Assignee: XILINX, INC.
    Inventor: Stephen M. Trimberger
  • Patent number: 10863618
    Abstract: A composite substrate structure includes a circuit substrate, a first anisotropic conductive film, a first glass substrate, a dielectric layer, a patterned circuit layer and a conductive via. The first anisotropic conductive film is disposed on the circuit substrate. The first glass substrate is disposed on the first anisotropic conductive film and has a first surface and a second surface opposite to the first surface. The first glass substrate includes a first circuit layer, a second circuit layer and at least one first conductive via. The first circuit layer is disposed on the first surface. The second circuit layer is disposed on the second surface. The first conductive via penetrates the first glass substrate and is electrically connected to the first circuit layer and the second circuit layer. The first glass substrate and the circuit substrate are respectively located on two opposite sides of the first anisotropic conductive film.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 8, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Pei-Wei Wang, Bo-Cheng Lin, Chun-Hsien Chien, Chien-Chou Chen
  • Patent number: 10861815
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • Patent number: 10863616
    Abstract: A circuit board includes an insulating layer; and a wiring layer disposed on a surface of the insulating layer, wherein the wiring layer includes a noise canceling region including a first wiring having a linear shape; and a second wiring having a linear shape and disposed side by side with the first wiring, wherein the first wiring and the second wiring include a bent portion.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: December 8, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Jeong Hyun Park
  • Patent number: 10852783
    Abstract: A system and method of operatively coupling a motherboard and a graphics board supported on a chassis, coating the motherboard and the graphics board with an anti-tarnish finish, plating a first interposer on at least a first side with a neutral metal material, soldering pass-through electrical contacts of the first interposer to a connector pad area of the motherboard, and clamping a first compression jumper pad to compress an array of compressible communication contacts to the pass-through electrical contacts on the first interposer, adjusting a flexible jumper trace array cable between the first compression jumper pad and a second compression jumper pad to adjacently align the motherboard and graphics board to minimize thickness of the information handling system, and coupling the second compression jumper pad to the graphics board to provide lanes of data communication.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: December 1, 2020
    Assignee: Dell Products, LP
    Inventors: Arnold Thomas Schnell, Ivan Guerra, Gurpreet Sahota
  • Patent number: 10852890
    Abstract: A touch panel includes a substrate, a touch sensing electrode, a peripheral conductive trace, a protective layer, and a conductive layer. The substrate has a display area and a peripheral area. The touch sensing electrode is disposed in the display area. The peripheral conductive trace is disposed in the peripheral area. The touch sensing electrode is electrically connected to the peripheral conductive trace. The touch sensing electrode and the peripheral conductive trace at least include metal nanowires. The protective layer is disposed on the touch sensing electrode, and the conductive layer is disposed on the peripheral conductive trace.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: December 1, 2020
    Assignee: TPK Touch Solutions Inc.
    Inventors: Chen-Yu Liu, Bo-Ren Jian, Cheng-Ping Liu
  • Patent number: 10818624
    Abstract: A semiconductor device includes a first substrate including a first surface, at least one first bonding pad disposed on the first surface, and at least one second bonding pad disposed on the first surface. The first bonding pad includes a first width, and the second bonding pad includes a second width. The second width is substantially different from the first width.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen
  • Patent number: 10811471
    Abstract: A display apparatus includes a touch screen panel having an active area and a non-active area. The touch screen panel includes a first side and a second side. A display flexible printed circuit board is connected to the touch screen panel. The display flexible printed circuit board at least partially overlaps the first side of the touch screen panel. A touch flexible printed circuit board is connected to the touch screen panel. The touch flexible printed circuit board at least partially overlaps the second side of the touch screen panel. The touch flexible printed circuit board is bent toward a lower surface of the touch screen panel. A reinforcement member contacts a lower surface of the touch flexible printed circuit board. A portion of a side surface of the touch screen panel is connected to the second side of the touch screen panel.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myoung-ha Jeon, Hyeonjeong Oh, Kichang Lee
  • Patent number: 10813213
    Abstract: The present disclosure provides a high-frequency composite substrate which includes a metal layer and an insulating structure. The insulating structure includes at least one liquid crystal polymer (LCP) layer with dielectric constant ranged from about 2 to about 4. The liquid crystal polymer layer adheres to the metal layer. The high-frequency composite substrate may reduce the adverse effects caused by the Resistor-Capacitor delay (RC delay).
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 20, 2020
    Assignee: AZOTEK CO., LTD.
    Inventor: Hung-Jung Lee
  • Patent number: 10804629
    Abstract: The present invention provides a method, structure, and system of beveling staggered card edges. In some embodiments, the method, computer program product, and system include receiving a card with a plug end and two or more metal contact leads running up to the plug end, removing material from the plug end such that one or more engagement points for one or more of the leads are set back from the plug end resulting in staggered steps, where an engagement point is where a metal contact lead will enter a receptacle, and removing material from an edge formed for each engagement point of the card such that beveled edges are created at the one or more engagement points for each lead.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sandra Shirk/Heath, Paul Schaefer, Mark Hoffmeyer
  • Patent number: 10806024
    Abstract: In one or more embodiments, a circuit board may include a trace pair and a serpentine region of the trace pair, which may include: a first subregion in which the first trace includes a first portion that has a third width and a first length and in which the second trace includes a second portion, at least substantially parallel to the first portion, that has a fourth width, greater than the second width, and a second length; and a second subregion, adjacent to the first subregion, in which the first trace includes a third portion that has the third width and a third length and in which the second trace includes a third portion that has the fourth width and a third length, different from the second length.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: October 13, 2020
    Assignee: Dell Products L.P.
    Inventors: Bhyrav Murthy Mutnury, Chun-Lin Liao
  • Patent number: 10795474
    Abstract: There is provided a display apparatus and a production method thereof. The display apparatus has a touch control panel and a display panel, wherein at least one surface of the touch control panel has a plurality of concave-convex fine structures, and wherein the touch control panel is on a light-emitting side of the display panel. The touch control panel may have: a flexible substrate having a plurality of concave-convex fine structures on at least one surface; and a touch control electrode having at least one part formed on one or more concave-convex fine structures of the flexible substrate.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: October 6, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dejun Bu, Pao Ming Tsai, Zhao Li
  • Patent number: 10784128
    Abstract: Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Frank Jun, Paul Kennedy
  • Patent number: 10779410
    Abstract: The present disclosure provides a circuit board, an electrical component and a display apparatus. The circuit board includes a wiring pad which is divided into a plurality of sub-pads by bubble discharge paths, the bubble discharge paths intersect at a first point which is a geometric center of the wiring pad. By configuring bubble discharge paths with a shape of a straight line and as being intersected at the geometric center point of the wiring pad, the circuit board can discharge gas bubbles, generated when the wiring pad is soldered to a wiring terminal of other circuit board, from the geometric center point of the wiring pad to the edge thereof via the bubble discharge paths. Thus gas bubbles can be eliminated or reduced between the wiring pad and the wiring terminal when soldering, connection between the wiring pad and the wiring terminal can be more secure.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: September 15, 2020
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lingguo Wang, Xin Wang, Ying Liu, Yaodong Wang, Bin Fan, Binbin Liu
  • Patent number: 10770498
    Abstract: A method for manufacturing the image sensor includes providing a substrate structure; forming a mask layer on the substrate structure, the mask layer having openings; depositing a metal grid material covering a surface of the mask layer and a bottom of the openings; and stripping the mask layer for removing a portion of the metal grid material on the top surface of the mask layer. The substrate structure includes: a substrate having a first surface; a plurality of pixels in the substrate; isolation structures around each of the plurality of pixels; and an anti-reflective coating on the first surface of the substrate. The openings include first openings exposing a portion of the first surface of the substrate structure above the isolation structures. A remaining portion of the metal grid material at the bottom of the openings forms metal grids.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: September 8, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Kui Qi, Fu Cheng Chen, Jue Lu, Xuan Jie Liu
  • Patent number: 10757800
    Abstract: A circuit board transmission line structures has microstrip or stripline transmission line geometries and cross-hatch patterned return planes. The cross-hatch design structure of the return planes and the relative position of the cross-hatch pattern to the transmission lines are configured to increase the usable bandwidth of the transmission lines. By properly adjusting the size and shape of the cross-hatch pattern, the performance of the microstrip and stripline transmission lines can be largely restored to the performance where continuous, solid return planes are used.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: August 25, 2020
    Assignee: Flex Ltd.
    Inventors: Mark Bergman, Franz Gisin
  • Patent number: 10743403
    Abstract: A wiring board includes an insulating layer, and a metal layer. The insulating layer includes a first pattern and a second pattern. The first pattern includes first grooves extending parallel to each other, and a first projecting part separating adjacent first grooves. The second pattern includes a second projecting part, and a second groove surrounding the second projecting part. The metal layer includes a wiring formed within the first grooves, and a degassing hole formed within the second pattern and having an opening formed by the second projecting part.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 11, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Rie Mizutani
  • Patent number: 10736214
    Abstract: A printed circuit board and a method for the production thereof. The printed circuit board can include a shaped part made of an electrically conducting material and can be used to manage the currents and heat volumes that occur in the field of power electronics.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: August 4, 2020
    Assignee: JUMATECH GMBH
    Inventor: Markus W├Âlfel
  • Patent number: 10705002
    Abstract: A sensor for detecting electrically conductive and/or polarizable particles, in particular for detecting soot particles, includes a substrate, a first electrode layer, and a second electrode layer, which is arranged between the substrate and the first electrode layer. An insulation layer is formed betweem the first electrode layer and the second electrode layer and at least one opening is formed in the first electrode layer and in the insulation layer, wherein the opening of the first electrode layer and the opening of the insulation layer are arranged one over the other at least in some segments in such a way that at least one passage to the second electrode layer is formed.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 7, 2020
    Assignee: HERAEUS NEXENSOS GMBH
    Inventors: Tim Asmus, Karlheinz Wienand, Stefan Dietmann
  • Patent number: 10701799
    Abstract: According to an example, a device may comprise a printed circuit board. The printed circuit board may further comprise a first layer and a second layer. The first layer may comprise a first material and the second layer may comprise a second material. In some examples, the first layer may further comprise at least one mounting hole surrounded by a third material at a thickness equal to a thickness of the first layer, and the first material may be electrically isolated from the third material. In some examples, the printed circuit board may be mated to a light guide assembly for a touchscreen system.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 30, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stewart R. Wyatt, Don E. Saunders, Scott David Hahn, Cameron L. Hutchings
  • Patent number: 10689248
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 23, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming Yen Lee, Chia Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
  • Patent number: 10679892
    Abstract: A method is presented for reducing a resistance-capacitance product and RIE lag in a semiconductor device. The method includes depositing a first ultra-low-k (ULK) material over a dielectric cap, the first ULK material defining a recess, filling the recess with a second ULK material, the second ULK material being different than the first ULK material, where the first and second ULK materials are formed in a common metal level of a back-end-of-the-line (BEOL) structure, forming first trenches within the first ULK material and second trenches within the second ULK material, and filling the first and second trenches with a conductive material.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Chih-Chao Yang, Hosadurga Shobha
  • Patent number: 10681819
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Patent number: 10672718
    Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: June 2, 2020
    Assignee: Georgia Tech Research Corporation
    Inventors: Venkatesh Sundaram, Fuhan Liu, Rao R. Tummala, Vijay Sukumaran, Vivek Sridharan, Qiao Chen
  • Patent number: 10663662
    Abstract: A hybrid spiral waveguide geometry is proposed that exhibits essentially zero curvature (i.e., infinite bend radius) at the center of the spiral (similar to a Fermat spiral), with the curvature then increasing in value as the spiral moves outward. Advantageously, as the spiral moves away from the center, the spacing between adjacent waveguides quickly approaches a constant value (similar to an Archimedean spiral). This hybrid spiral structure has been found to allow for a high density waveguide to be created with lower loss and requiring a smaller size than many conventional spiral configurations and finds use in optical delay lines, amplifiers and arrayed waveguide gratings.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 26, 2020
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Michael Gehl, Christopher DeRose