Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
  • Patent number: 11908497
    Abstract: A hard disk drive flexure assembly includes a base layer, a conductive layer, a plurality of electrical pads over the conductive layer, and a sidewall layer including sidewalls on each side of and extending higher than a corresponding electrical pad. Pre-solder bumps are formed between the sidewalls and over each pad. Use of sidewalls prevents the pre-solder bumps from undesirably bridging to an adjacent electrical pad and forming a short circuit, which might otherwise cause head-gimbal assembly (HGA) manufacturing failures and consequent increased cost. These techniques are especially relevant with narrow, high-density, small pitch electrical pads.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Irizo Naniwa, Kenichi Murata
  • Patent number: 11900720
    Abstract: A circuit board according to an embodiment includes: a substrate including one surface and the other surface; a first circuit pattern disposed on the one surface; and a second circuit pattern disposed on the other surface, wherein at least one via is formed in the substrate, and the first circuit pattern and the second circuit pattern are wire-bonded through the via to conduct electricity.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 13, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Seung Joon Kim, Yong Hyun Gwon, Yong Hyun Cho
  • Patent number: 11889620
    Abstract: A radio-frequency module includes a mounting board, a first electronic component, and a second electronic component. The second electronic component is lower in height than the first electronic component. The mounting board includes dielectric layers, conductive layers, and via-conductors. In the mounting board, the dielectric layers and the conductive layers are stacked in the thickness direction of the mounting board. The mounting board has a first region and a second region. The first region overlaps the first electronic component and extends from a first major surface to a second major surface. The second region overlaps the second electronic component and extends from the first major surface to the second major surface. In the mounting board, the conductive layers in the first region are fewer than the conductive layers in the second region. In the mounting board, the first region is thinner than the second region.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: January 30, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yutaka Shuto, Hiroshi Nishikawa, Tomomi Yasuda
  • Patent number: 11889627
    Abstract: A display device includes a first substrate, a second substrate, a plurality of drive ICs and at least one flexible circuit board. The first substrate has a first region and a second region near to the first region. The second substrate is disposed on the first region and has a lateral side. The plurality of drive ICs are disposed on the second region and arranged along the lateral side. The at least one flexible circuit board is disposed on the second region and disposed correspondingly to the lateral side. Wherein in a top view of the display device, each of the plurality of drive ICs does not overlap with the at least one flexible circuit board in a direction perpendicular to an extending direction of the lateral side.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 30, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Chin-Cheng Kuo, Chia-Chun Yang, Wen-Cheng Huang
  • Patent number: 11881457
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 23, 2024
    Assignee: Tahoe Research, Ltd.
    Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
  • Patent number: 11874579
    Abstract: A multi-layer device comprising a first substrate, a first electrically conductive layer on a surface thereof, and a first current modulating layer, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 16, 2024
    Assignee: HALIO, INC.
    Inventors: Howard S. Bergh, Jonathan Ziebarth, Nicolas Timmerman
  • Patent number: 11866837
    Abstract: The invention relates to a method for fabrication of a one-piece, metal-based component of simple shape offering the illusion of faceting and/or chamfering for forming all or part of the exterior part of a timepiece.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 9, 2024
    Assignee: Nivarox-FAR S.A.
    Inventors: Pierre Cusin, Alex Gandelhman, Michel Musy
  • Patent number: 11871513
    Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: January 9, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Shigeki Koya, Kenji Sasaki
  • Patent number: 11871526
    Abstract: A circuit board includes a substrate, a first circuit layer, a second circuit layer, and a third circuit layer. The substrate includes a base layer, a first metal layer formed on the base layer, and a seed layer formed on the first metal layer. The first circuit layer is located on the substrate and includes the first metal layer and a signal layer formed on a surface of the first metal layer. The second circuit layer is coupled to the first circuit layer and includes the first metal layer, the seed layer, and a connection pillar formed on a surface of the first metal layer and the seed layer. The third circuit layer is coupled to the second circuit layer and includes the seed layer and a coil formed on a surface of the seed layer.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: January 9, 2024
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Jun Dai
  • Patent number: 11860499
    Abstract: A multi-layer device comprising a first substrate and a first electrically conductive layer on a surface thereof, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 2, 2024
    Assignee: HALIO, INC.
    Inventors: Howard S. Bergh, Jonathan Ziebarth, Nicolas Timmerman
  • Patent number: 11864312
    Abstract: According to one aspect of the present disclosure, a printed circuit board includes: an insulating base film; and a plurality of wiring portions formed on a surface of the base film, wherein the wiring portions include a seed layer that is directly or indirectly layered on the surface of the base film and a metal layer that is layered on the seed layer, wherein the base film has a wiring area including the plurality of wiring portions and a non-wiring area not including the wiring portions, wherein the plurality of wiring portions include at least one outermost boundary wiring portion and a plurality of inner wiring portions other than the outermost boundary wiring portion, wherein the outermost boundary wiring portion is formed on an outermost side of the base film in the wiring area and at a boundary between the wiring area and the non-wiring area, wherein an average width of the outermost boundary wiring portion is 30 ?m or more, wherein an average width of the inner wiring portions is 20 ?m or less, and w
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 2, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi Ueda, Ippei Tanaka, Takashi Kasuga, Masamichi Yamamoto
  • Patent number: 11853502
    Abstract: Display panel and display device are provided. The display panel includes an array substrate and a cover plate disposed opposite to the array substrate, touch electrode layers on a side of the cover plate facing the array substrate, and a plurality of first touch pads and a plurality of second touch pads disposed opposite to the plurality of the first touch pads. Each of the array substrate and the cover plate include a display area and a non-display area at least partially surrounding the display area. The non-display area of the array substrate includes a step area provided with bonding pads. The non-display area of the array substrate includes at least one irregularly-shaped area adjacent to the step area. A first touch pad is electrically connected to a second touch pad.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: December 26, 2023
    Assignees: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Qibing Wei, Peng Zhang, Xingyao Zhou, Wei Liu
  • Patent number: 11841746
    Abstract: A display device according to an embodiment comprises: an elastic member; and at least one panel from among a display panel and a touch panel which are arranged on the elastic member, wherein the elastic member includes one surface and the other surface opposite to the one surface, the elastic member includes a first area and a second area, the first area is defined as a folding area, the second area is defined as an unfolding area, the elastic member has a plurality of first grooves arranged on the one surface in the first area thereof, and the panel is arranged on the other surface of the elastic member via an adhesive layer.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: December 12, 2023
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sung Won Kang, Jae Seok Park
  • Patent number: 11842016
    Abstract: A flexible display device is provided that includes a display panel having an active area including a plurality of pixels displaying an image and a non-active area surrounding the active area, first data pads disposed in the non-active area adjacent to the active area of the display panel and electrically connected with the plurality of pixels, pads disposed in a direction away from the first data pads and the active area, second data pads disposed between the first data pads and the pads, and a protrusion pattern located between the second data pads and the third data pads and disposed on an upper part of the insulating layer.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: December 12, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kiyoung Sung, Sangho Kim, Eunjin Oh
  • Patent number: 11842828
    Abstract: Transparent conductive films comprising sparse metal conductive layers are processed after coating with an overcoat to lower the sheet resistance of the film. The sparse metal conductive layer can comprise a fused metal nanostructured network. A coating, such as a polymer overcoat or a polymer undercoat can noble metal ions that can further reduce the sheet resistance with the application of heat and optionally humidity. In particular, silver ions in a coating are demonstrated to provide important stabilization of sparse metal conductive layers, whether or not fused, upon the application of heat and humidity. A coating can further comprise a metal salt stabilization composition.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: December 12, 2023
    Assignee: C3 Nano, Inc.
    Inventors: Xiqiang Yang, Ajay Virkar
  • Patent number: 11836955
    Abstract: Aspects of the disclosure relate to determining a sign type of an unfamiliar sign. The system may include one or more processors. The one or more processors may be configured to receive an image and identify image data corresponding to a traffic sign in the image. The image data corresponding to the traffic sign may be input in a sign type model. The processors may determine that the sign type model was unable to identify a type of the traffic sign and determine one or more attributes of the traffic sign. The one or more attributes of the traffic sign may be compared to known attributes of other traffic signs and based on this comparison, a sign type of the traffic sign may be determined. The vehicle may be controlled in an autonomous driving mode based on the sign type of the traffic sign.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 5, 2023
    Assignee: Waymo LLC
    Inventors: Zhinan Xu, Maya Kabkab, Chen Wu, Woojong Koh
  • Patent number: 11839019
    Abstract: A communication module includes a first wiring board including a plurality of first signal lines and a first ground line, and a second wiring board including a first layer and a second layer. The first layer includes a plurality of second signal lines. The second layer includes a shielding member. The communication module includes a plurality of first connection members via which the plurality of first signal lines are electrically connected to the plurality of second signal lines, and at least one conductive member provided between the first ground line and the shielding member. The at least one conductive member is provided so as to overlap with at least one second signal line among the plurality of second signal lines as viewed in a direction perpendicular to a main surface of the first wiring board.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: December 5, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomohisa Ishigami, Makoto Aoki, Yuya Okada
  • Patent number: 11839029
    Abstract: One aspect provides an apparatus for locking circuit boards in position between a pair of guide rails. The apparatus can include a slider attached to a sidewall of one guide rail. The slider is allowed to slide along the guide rail within a predetermined range and one or more plunger-and-spring assemblies. A respective plunger-and-spring assembly comprises a plunger and a spring surrounding the plunger, and the plunger is inserted into a through-hole on the sidewall of the guide rail such that a first end of the plunger can be aligned with a notch on a corresponding circuit board and a second end of the plunger is in contact with the slider. Sliding of the slider causes the spring to compress and decompress and the first end of the plunger to move in and out of the notch on the circuit board, thereby facilitating locking and unlocking of the circuit board.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: December 5, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Warren A. Kartadinata, Neil Jefferson Asmussen, Vance B. Murakami
  • Patent number: 11832393
    Abstract: An information handling system printed circuit board includes solder pads that accept footprint compatible integrated circuits, such as charger integrated circuits that provide power with different choke circuit supporting components. Solder pads for supporting components include first and second conductive areas sized to accept a first supporting component, each of the first and second conductive areas including an intervening non-conductive area that manages positioning of a smaller second supporting component at solder reflow.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: November 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Yu-Lin Tsai, Chia-Hsien Lu, Chun-Min He, RungLung Lin, Chin-Chung Wu
  • Patent number: 11829133
    Abstract: A vehicle remote control system includes a server including a transceiver and a controller. The transceiver is configured to receive location data from a vehicle and location data from a remote device. The controller is configured to receive an operating instruction signal from the remote device, the operating instruction signal including instructions to operate one or more components of the vehicle. A distance between the vehicle and the remote device is determined based on the location data from the vehicle and the location data from the remote device. The operating instruction signal is transmitted to the vehicle in response to a determination that the distance between the vehicle and the remote device is equal to or less than a corresponding threshold distance.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 28, 2023
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: Masashi Nakagawa
  • Patent number: 11824287
    Abstract: Disclosed is an apparatus for electrically contacting a control/evaluation electronics of a field device of automation technology with an external energy supply and/or a controller, wherein the control/evaluation electronics of the field device is arranged on a circuit card, wherein at least one terminal box is provided, in which a plurality of adjoining electrical connection terminals are provided, wherein the electrical connection terminals serve, in each case, for accommodating an electrical connecting element, wherein the electrical connecting elements are connected mechanically and electrically with the circuit card, in each case, via a solder pad, and wherein there are provided between each two solder pads vacancies in the circuit card, which are so embodied that the length of the leakage preventing distance between the solder pads satisfies a predetermined ignition protection type.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: November 21, 2023
    Assignee: Endress+Hauser SE+Co. KG
    Inventors: Michael Dötsch, Robert Schmidt, Ralf Leisinger
  • Patent number: 11818840
    Abstract: A printed wiring board includes an electrode pad to be soldered to an electrode of an electronic component, an electrode pad to be soldered to an electrode of the electronic component, a barrier conductor continuous with the electrode pad, and a barrier conductor continuous with the electrode pad, the barrier conductor and the barrier conductors are located at positions facing each other with a gap area therebetween, the barrier conductor and the electrode pads are positioned such that the electrode pad faces the gap area with the barrier conductor therebetween and that the electrode pad faces the gap area with the barrier conductor therebetween, and the gap area is an area in which an adhesive is placed when adhering the electronic component.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 14, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Shigeta, Masato Morita, Hironobu Fukushima, Masahiro Koyama, Naoki Matsumoto
  • Patent number: 11804428
    Abstract: Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 31, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Wen Yin, Yonghao An, Manuel Aldrete
  • Patent number: 11797123
    Abstract: A coplanar sensor includes a plurality of first sensing units and a plurality of second sensing units. Each of the first sensing units includes a plurality of first electrode blocks that are spaced apart from each other in a first direction, and a first connecting line that is electrically coupled to the first electrode blocks. Each of the second sensing units includes a plurality of second electrode blocks that are spaced apart from each other in a second direction intersecting the first direction, and a second connecting line that is electrically coupled to the second electrode blocks. Each of the first electrode blocks has a first sensing surface. Each of the second electrode blocks has a second sensing surface. The first sensing surfaces of the first electrode blocks and the second sensing surfaces of the second electrode blocks are coplanar.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: October 24, 2023
    Inventors: William Wang, Yu-Sung Su
  • Patent number: 11800641
    Abstract: Here are described composite panels comprising at least one integrated or embedded electrical circuit, their methods of manufacturing and their use in the aeronautic and aircraft industries. Also described are aircraft components including the composite panel as defined herein.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: October 24, 2023
    Assignee: HUTCHINSON AERONAUTIQUE & INDUSTRIE LTÉE.
    Inventors: Martin Levesque, Jean-Philippe Larose, Franck Guillemand
  • Patent number: 11783998
    Abstract: The present disclosure relates to a process to integrate sintered components in a laminate substrate. The disclosed process starts with providing a precursor substrate, which includes a substrate body having an opening through the substrate body, and a first foil layer. Herein, the first foil layer is formed underneath the substrate body, so as to fully cover a bottom of the opening. Next, a sinterable base material is applied into the opening and over the first foil layer, and then sintered at a first sintering temperature to create a sintered base component. A sinterable contact material is applied over the sintered base component, and then sintered at a second sintering temperature to create a sintered contact film. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on bottom, and by the sintered contact film on top.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 10, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Tarak A. Railkar, Deepukumar M. Nair, Jeffrey Dekosky
  • Patent number: 11776883
    Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: October 3, 2023
    Assignee: GaN Systems Inc.
    Inventors: Cameron McKnight-MacNeil, Greg P. Klowak
  • Patent number: 11768569
    Abstract: A touch substrate and a method of forming the same, and a touch display device are provided. The touch substrate includes: electrode connecting bridges, a signal wiring layer, an insulating layer and a touch electrode layer which are sequentially formed along a direction away from a base, where the touch electrode layer includes a plurality of first touch electrodes and a plurality of second touch electrodes, and the first touch electrodes and the second touch electrodes are arranged in a crossed manner.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: September 26, 2023
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zouming Xu, Xiaofeng Yin, Tsungchieh Kuo, Jian Tian, Chunjian Liu
  • Patent number: 11758658
    Abstract: A display panel having a bonding region for bonding a flexible printed circuit in a peripheral region is provided. The display panel includes a plurality of first signal lines on a base substrate; and a plurality of bonding pins on the base substrate and in the bonding region. The plurality of bonding pins include a plurality of first bonding pins respectively electrically connected to the plurality of first signal lines. The display panel further includes a plurality of connecting portions respectively connecting the plurality of first signal lines portions to the plurality of first bonding pin portions. A respective one of the plurality of first bonding pin portions and a respective one of the plurality of connecting portions are substantially parallel to each other, and are arranged at a substantially same inclined angle with respect to a respective one of the plurality of first signal line portions.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 12, 2023
    Assignees: Chengdu BOE Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Donghui Tian, Bo Zhang, Zhiwen Chu, Rong Wang, Yulong Wei
  • Patent number: 11744009
    Abstract: An electronic module, such as a VRM, has a power inductor and power wave pins disposed on a bottom surface of a circuit board so as to reduce the size and increase the heat dissipation capability of the VRM.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: August 29, 2023
    Assignee: CYNTEC CO., LTD.
    Inventors: Kaipeng Chiang, Da-Jung Chen, Bau-Ru Lu, Chun Hsien Lu
  • Patent number: 11735232
    Abstract: A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 22, 2023
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventor: Christopher Cox
  • Patent number: 11737207
    Abstract: A printed circuit board (PCB) includes a substrate defining a major plane. A first side of the major plane is configured for mounting of functional circuit elements. A cable connector is mounted on a second side of the major plane of the substrate, opposite the first side, for coupling to a shielded radiofrequency (RF) communications cable. At least one component grounding layer is parallel to the major plane and configured for coupling to the functional elements. At least one cable grounding layer is parallel to the major plane and is separated from the at least one component grounding layer. Each cable grounding layer in the at least one cable grounding layer is coextensive with the substrate and is configured for coupling, through the connector, to shielding of the shielded RF communications cable, without coupling to any other component. Nodes of an RF communications system may be mounted on such PCBs.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 22, 2023
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shaowu Huang, Dance Wu
  • Patent number: 11716813
    Abstract: A module includes a wiring board having a first main surface, a first component mounted on the first main surface and having a first height H1, a second component mounted on the first main surface and having a second height H2 lower than the first height H1, and a sealing resin arranged so as to cover the first component and the second component while covering the first main surface. Compared to a first connection terminal used for connection between the first component and the first main surface, a second connection terminal used for connection between the second component and the first main surface has a higher height. A surface of the first component on a side far from the first main surface and a surface of the second component on a side far from the first main surface are exposed from the sealing resin.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: August 1, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Kyo Shin
  • Patent number: 11711892
    Abstract: A thin, flexible computerized sensing platform which can be affixed to a structure to be sensed, which has excellent mechanical coupling between the sensors and the object to be sensed, which can be self-powered and rechargeable, and which can be environmentally sealed, and a method for assembling and utilizing the same.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 25, 2023
    Assignee: Velvetwire LLC
    Inventors: Eric Oleg Bodnar, Jacob Van Reenen Pretorius
  • Patent number: 11699645
    Abstract: A semiconductor device includes a wiring substrate having: a first wiring layer having pads; and a second wiring layer having wirings and via-lands. The via-lands include: first-row via-lands connected to first-row pads of the pads, respectively; and second-row via-lands connected to the second-row pads of the pads, respectively. In the perspective plan view, the first-row via-lands have: first via-lands arranged such that a center of each of the first via-lands is shifted in a direction away from a first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad; and second via-lands arranged such that a center of each of the second via-lands arranged at a position closer to the first side than the first via-land. In the perspective plan view, the first and second via-lands are alternately arranged in a first direction along the first side.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: July 11, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Tsuchiya, Shuuichi Kariyazaki
  • Patent number: 11699670
    Abstract: A module that improves heat-dissipation efficiency and can prevent a warp and a deformation of the module is provided. A module includes a substrate, a first component mounted on an upper surface of the substrate, a heat-dissipation member, and a sealing resin layer that seals the first component and the heat-dissipation member. The heat-dissipation member is formed to be larger than the area of the first component when viewed in a direction perpendicular to the upper surface of the substrate and prevents heat generation of the module by causing the heat generated from the first component to move outside the module. The heat-dissipation member has through holes, and the through holes are packed with a resin, which can prevent the sealing resin layer from peeling off.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: July 11, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Akihiro Fujii
  • Patent number: 11682613
    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kaladhar Radhakrishnan, Kemal Aygun
  • Patent number: 11683890
    Abstract: A reflowable grid array (RGA) interposer includes first connection pads on a first surface of a body and second connection pads on a second surface of the body. Heating elements within the body are adjacent to the second connection pads. First interconnects within the body connect some of the second connection pads to the first connection pads. Second interconnects within the body connect pairs of the second connection pads. A motherboard assembly includes first and second components (e.g., CPU with co-processor and/or memory) and the RGA interposer. The first connection pads are in contact with motherboard contacts. The second connection pads are in contact with the first and second components. The first component passes signals directly to the motherboard by the first interconnects. The second component passes signals directly to the first component by the second interconnects but does not pass signals directly to the motherboard by the first interconnects.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Jonathan W. Thibado, Jeffory L. Smalley, John C. Gulick, Phi Thanh, Mohanraj Prabhugoud
  • Patent number: 11653454
    Abstract: A printed wiring board according to an aspect of the present invention includes a base film having insulation properties and a conductive pattern including multiple wiring portions laminated, the conductive pattern running on at least one surface of the base film, wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, wherein an average width of each wiring portion is 10 ?m or greater to 50 ?m or smaller, and an average thickness of the second conductive portion is 1 ?n or greater to smaller than 8.5 ?m.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 16, 2023
    Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kohei Okamoto, Kousuke Miura, Hiroshi Ueda, Shoichiro Sakai, Maki Ikebe
  • Patent number: 11647591
    Abstract: Aspects of the invention include a press-fit pin for mechanically and electrically connecting to a through-hole of a substrate. The press-fit pin can include a press-fit portion configured to be deformed upon insertion into the through-hole against a plated surface of the through-hole. A surface mount technology (SMT) pad can be coupled to a first end of the press-fit portion. The SMT pad can include a conductive material. The press-fit pin can further include a trace extension coupled to the SMT pad. The trace extension can extend from the SMT pad in a direction perpendicular to the press-fit portion. The press-fit pin can include a tip portion coupled to a second end of the press-fit portion.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: May 9, 2023
    Assignee: International Business Machines Corporation
    Inventors: Theron Lee Lewis, David J. Braun, John R. Dangler
  • Patent number: 11631622
    Abstract: A semiconductor device, including a substrate having an insulating plate and a conductive plate formed on the insulating plate, a semiconductor chip formed on the conductive plate, a contact part arranged on the conductive plate with a bonding member therebetween, a rod-shaped external connection terminal having a lower end portion thereof fitted into the contact part, and a lid plate having a front surface and a back surface facing the substrate. An insertion hole pierces the lid plate, forming an entrance and exit respectively on the back and front surfaces of the lid plate. The external connection terminal is inserted in the insertion hole. The semiconductor device has at least one of a guide portion with an inclined surface, fixed to a portion of the external connection terminal located in the insertion hole, or an inclined inner wall of the insertion hole.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: April 18, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Makoto Isozaki
  • Patent number: 11628728
    Abstract: A battery module includes a lower housing and a plurality of battery cells. The plurality of battery cells are electrically coupled together to produce a voltage. The module also includes an assembly disposed over the battery cells and coupled to the lower housing. The assembly may include a lid and a plurality of bus bar interconnects mounted on the lid. The module also includes a printed circuit board (PCB) assembly disposed on and coupled to the assembly. The PCB assembly may include a PCB. The module also includes a cover disposed over and coupled to the lower housing to hermetically seal the battery module. Also disclosed is a method of manufacturing the battery module.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: April 18, 2023
    Assignee: CPS Technology Holdings LLC
    Inventors: Ronald J. Dulle, Mark D. Gunderson, Bryan L. Thieme, Richard M. DeKeuster, Edward J. Soleski, Robert J. Mack, Gary P. Houchin-Miller, Stephen D. Cash, Lisa L. Winders, Jack L. Johnson
  • Patent number: 11626259
    Abstract: A membrane circuit structure having a plurality of switch regions includes first, second and third membranes and a spacer layer. The second membrane is beneath the first membrane, and a lower surface of the second membrane is provided with a conductive pattern in at least one of the switch regions. The spacer layer is disposed between the first and second membranes. The third membrane is beneath the second membrane, and an upper surface of the third membrane is provided with first and second trigger portions separated from each other in the at least one of the switch regions, and the conductive pattern is able to be in contact with the first and second trigger portions, so that the first and second trigger portions are able to be electrically connected to each other through the conductive pattern.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: April 11, 2023
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Lei-Lung Tsai, Sheng-Fan Chang, Chin-Sung Pan
  • Patent number: 11625134
    Abstract: A touch sensing unit includes a base substrate, touch sensing lines disposed on the base substrate, a first touch insulating layer disposed on the touch sensing lines, and touch electrodes disposed on the first touch insulating layer. The touch electrodes overlap the touch sensing lines in a thickness direction. Each of the touch electrodes has a mesh shape including a body and mesh holes. The bodies do not overlap the touch sensing lines in the thickness direction in a remaining area, except for partial areas.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: April 11, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Hoon Kim, Sang Hun Park
  • Patent number: 11617264
    Abstract: An interconnect substrate includes a first insulating layer, an interconnect layer formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer to cover the interconnect layer, wherein the second insulating layer includes a first resin layer and a second resin layer, the first resin layer covering at least part of a surface of the interconnect layer exposed outside the first insulating layer, the second resin layer covering the first resin layer, wherein both the first resin layer and the second resin layer contain a resin and a filler, and wherein a proportion of the resin in the first resin layer per unit area is higher than a proportion of the resin in the second resin layer per unit area.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: March 28, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yuji Yukiiri
  • Patent number: 11603427
    Abstract: The present application relates to a composition, a battery module and a battery pack. According to one example of the present application, the related manufacturing process can be improved and a battery module having excellent insulation can be provided.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: March 14, 2023
    Inventors: Yoon Gyung Cho, Se Woo Yang, Yang Gu Kang, Eun Suk Park, Hyun Suk Kim, Hyoung Sook Park, Sang Min Park, Young Jo Yang
  • Patent number: 11602046
    Abstract: A wiring board according to the present disclosure includes a core board including an upper surface, a lower surface, a through-hole penetrating from the upper surface to the lower surface, and a plurality of glass fibers located inside, and a through-hole conductor located in the through-hole. The through-hole conductor includes a first portion located on an inner wall of the through-hole, and second portions connected to the first portion and located inside the glass fibers. The second portions include portions in a first direction and a second direction intersecting the first direction in a planar direction of the core board, the portions having a shorter length in the planar direction from the inner wall of the through-hole than portions, of the second portions, in directions other than the first direction and the second direction.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: March 7, 2023
    Assignee: KYOCERA Corporation
    Inventor: Hiroshi Takeuchi
  • Patent number: 11599047
    Abstract: An image forming apparatus includes an image forming device, a fixing device, a high voltage power supply board, a main body housing and a door. The door is provided in the main body housing so as to face the fixing device. The fixing device includes a fixing member, a pressure roller, a charge applying device, a fixing housing and a contact member. The fixing member is rotatable. The charge applying device is applied with a voltage from the high voltage power supply board and applies a charge to the fixing member. The fixing housing stores the fixing member, the pressure roller and the charge applying device. The contact member is provided in the fixing housing at a position accessible by opening the door and to which a feed line on the high voltage power supply board side and a feed line on the charge applying device side are connected.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: March 7, 2023
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Shota Onishi
  • Patent number: 11594480
    Abstract: A circuit assembly may include a substrate and a pattern of contact points formed from deformable conductive material supported by the substrate. The assembly may further include an electric component supported by the substrate and having terminals arranged in a pattern corresponding to the pattern of contacts points. The one or more of the terminals of the electric component may contact one or more of the corresponding contact points to form one or more electrical connections between the electric component and the contact points.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: February 28, 2023
    Assignee: Liquid Wire Inc.
    Inventors: Mark William Ronay, Trevor Antonio Rivera, Michael Adventure Hopkins, Edward Martin Godshalk, Charles J. Kinzel
  • Patent number: 11594479
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, conductive joints, conductive terminals, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first side and a second side opposite to the first side, wherein trenches are located on the second side of the redistribution structure and extend to an edge of the second side of the redistribution structure. The conductive joints are disposed over the first side of the redistribution structure. The conductive terminals are disposed over the second side of the redistribution structure. The circuit substrate electrically coupled to the redistribution structure through the conductive joints. The insulating encapsulation is disposed on the first side of the redistribution structure to cover the circuit substrate.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: February 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Lin Ho, Chin-Liang Chen, Pei-Rong Ni, Chia-Min Lin, Yu-Min Liang, Jiun-Yi Wu