Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
  • Patent number: 12048091
    Abstract: A stretchable wiring board that includes: a stretchable substrate; a first stretchable wiring extending in a length direction on a main surface side of the stretchable substrate; and a second stretchable wiring extending in the length direction on the main surface side of the stretchable substrate, the second stretchable wiring having a first portion with a first region overlapping on top of the first stretchable wiring on an end portion side of the first stretchable wiring, and a width of the first portion of the second stretchable wiring in a width direction orthogonal to the length direction is smaller than a width of the first stretchable wiring.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: July 23, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keisuke Nishida, Hayato Katsu, Yutaka Takeshima
  • Patent number: 12041730
    Abstract: A method of manufacturing a component carrier is described. The method includes forming a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and reducing an amount of solvent in a fiber-free dielectric layer, which is directly connected to a metal layer, so that the dielectric layer with reduced amount of solvent remains at least partially uncured.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: July 16, 2024
    Assignee: AT&SAustria Technologie & Systemtechnik AG
    Inventors: Seok Kim Tay, Mikael Tuominen, Kim Liu
  • Patent number: 12032119
    Abstract: An optical stack structure includes a metal nanowire layer and an organic polymer layer. A crosslinking degree of the organic polymer layer is greater than or equal to 80% and less than or equal to 100%, and a content of volatile organic compounds in the organic polymer layer is less than or equal to 1%. The content of the volatile organic compounds in the organic polymer layer is defined as a difference between a thermal weight loss of the organic polymer layer measured at a measuring temperature and a water content of the organic polymer layer measured at the measuring temperature.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: July 9, 2024
    Assignee: TPK Advanced Solutions Inc.
    Inventors: Huang Chen, Ching Mao Huang, Wei Sheng Chen
  • Patent number: 12034260
    Abstract: A connection body, a method for manufacturing a connection body, and a connection method which can secure conduction reliability by trapping conductive particles even when the bump size is minimized. In a connection body in which a first component having a first electrode and a second component having a second electrode are connected to each other via a filler-containing film having a filler-aligned layer in which independent fillers are aligned in a binder resin layer, the maximum effective connection portion area where the first electrode and the second electrode face each other is 4,000 ?m2 or less and a ratio of the effective connection portion area to a particle area on the connection portion projection plane is 3 or more.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 9, 2024
    Assignee: DEXERIALS CORPORATION
    Inventors: Ryota Aizaki, Kosuke Asaba
  • Patent number: 12028964
    Abstract: A shielded printed wiring board includes a substrate film including a base film and printed circuits including a ground circuit formed on the base film; an electromagnetic wave shielding film including a shielding layer and an insulating layer; and a reinforcing member including a conductive adhesive layer and a metal reinforcing plate, wherein the ground circuit of the substrate film is sufficiently electrically connected to the metal reinforcing plate of the reinforcing member.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: July 2, 2024
    Assignee: Tatsuta Electric Wire & Cable Co., Lid.
    Inventor: Yuusuke Haruna
  • Patent number: 12027285
    Abstract: A wiring member with a fixing member includes a flat wiring member, and a fixing member. The flat wiring member includes a plurality of wire-like transmission members and a base material. The plurality of wire-like transmission members are fixed to the base material in an arrayed state. The fixing member includes a plate-like part and a fixing part. The plate-like part is formed into a plate-like shape elongated in one direction, and the plate-like part is attached to the base material while a main surface of the plate-like part comes in surface contact with the base material. The fixing part is a part being provided to project on the plate-like part and being configured to fix the flat wiring member to a fixing target.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: July 2, 2024
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Daisuke Ebata, Ryuta Takakura, Taku Umehara, Tetsuya Nishimura, Kenta Arai, Miyu Aramaki
  • Patent number: 12017406
    Abstract: In an example 3D printing method, an electrical conductivity value for a resistor is identified. Based upon the identified electrical conductivity value, a predetermined amount of a conductive agent is selectively applied to at least a portion of a build material layer in order to introduce a predetermined volume percentage of a conductive material to the resistor. Based upon the identified electrical conductivity value and the predetermined volume percent of the conductive material, a predetermined amount of a resistive agent is selectively applied to the at least a portion of the build material layer in order to introduce a predetermined volume percentage of a resistive material to the resistor. The build material layer is exposed to electromagnetic radiation, whereby the at least the portion coalesces to form a layer of the resistor.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: June 25, 2024
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jarrid A. Wittkopf, Kristopher J. Erickson, Lihua Zhao
  • Patent number: 11984677
    Abstract: Technologies and implementations for a clip to connect coaxial cables onto a printed circuit board assembly (PCBA) are disclosed. The technologies and implementations facilitate improved signal integrity from the cable to various components of the PCBA. Additionally, the technologies and implementations help facilitate management of mechanical variations during connection of the coaxial cable.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 14, 2024
    Assignee: WEST AFFUM HOLDINGS DAC
    Inventors: Robert R. Buchanan, Douglas K. Medema, Daniel R. Piha, Dallas E. Meeker, Daniel J. Finney
  • Patent number: 11977707
    Abstract: Each of first electrode sections forming a transmission electrode includes a first main line and a plurality of first auxiliary lines. Each of second electrode sections forming a reception electrode includes a second main line and a plurality of second auxiliary lines. With the transmission and reception electrodes and overlapping each other, the first main line and the second main line intersect with each other at one point, and a cell region is unclosed. The cell region is surrounded by two or more types of thin wires selected from a group consisting of the first main line, the first auxiliary lines, the second main line, and the second auxiliary lines.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: May 7, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiromitsu Niwa, Kota Araki, Akihiro Yamamura, Hiroaki Nishiono
  • Patent number: 11963298
    Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including first and second pads, a solder resist layer formed on the base layer, covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, a first bump formed on the first pad and including a base plating layer and a top plating layer, and a second bump formed on the second conductor pad and including a base plating layer and a top plating layer. The second opening has diameter smaller than diameter of the first opening, the second bump has diameter smaller than diameter of the first bump, the first pad has a first recess formed on the first pad, the second pad has a second recess formed on the second pad, and the first recess is larger than the second recess.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: April 16, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoshiki Matsui, Atsushi Deguchi
  • Patent number: 11956890
    Abstract: A circuit board includes a first insulating layer; a first wiring pattern and a second wiring pattern each formed to be side to side with each other on an upper surface of the first insulating layer; a second insulating layer formed on the upper surface of the first insulating layer to cover the first and second wiring patterns; a third wiring pattern formed on an upper surface of the second insulating layer to overlap the first wiring pattern in a vertical direction; a fourth wiring pattern formed on the upper surface of the second insulating layer to overlap the second wiring pattern in the vertical direction; a first via passing through the second insulating layer and connecting the first and fourth wiring patterns; and a second via passing through the second insulating layer and connecting the second and third wiring patterns.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yunho Lee, Yoojeong Kwon, Kyoungsun Kim, Dongyeop Kim, Sungjoo Park
  • Patent number: 11956894
    Abstract: The invention provides a printed circuit board assembly (1) comprising (i) an at least partly folded flexible printed circuit board (100), and (ii) an at least partly folded support (200), wherein: —the at least partly folded flexible printed circuit board (100) comprises a first PCB region (110) and a second PCB region (120), wherein at least part of the second PCB region (120) is configured folded over at least part of the first PCB region (110); —the at least partly folded support (200) is configured to support at least part of the at least partly folded flexible printed circuit board (100), wherein the at least partly folded support (200) comprises a first support region (210) and a second support region (220), wherein at least part of the second support region (220) is configured folded over at least part of the first support region (210), wherein at least part of the at least partly folded flexible printed circuit board (100) is configured between the first support region (210) and the second support re
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: April 9, 2024
    Assignee: SIGNIFY HOLDING, B.V.
    Inventor: Pieter Joseph Clara Van Der Wel
  • Patent number: 11957006
    Abstract: A display device includes a display panel and an integrated circuit chip configured with a plurality of first bonding terminals spaced apart from each other. The display panel is provided with a plurality of second bonding terminals, and a first insulating layer is disposed between the first bonding terminals and the second bonding terminals. A plurality of electrically conductive particles are provided on the second bonding terminals and penetrate the first insulating layer so that the electrically conductive particles are in contact with the first bonding terminals.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: April 9, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Caihua Ding
  • Patent number: 11956903
    Abstract: A transmission line includes a first structure including a first flexible resin base material, and a first ground conductor thereon, a second structure including a second flexible resin base material, and a first signal line and an interlayer connection conductor in or on the second resin base material, a first spacer between the first and second structures, and a first metal joining material joining the first and second structures with the first spacer interposed therebetween. A first hollow portion is between the first and second structures with the first spacer interposed therebetween. The first signal line and the first ground conductor face each other in a joining direction with the first hollow portion interposed therebetween. The first resin base material and the second resin base material are not in contact with each other. The first metal joining material has a melting point lower than that of the interlayer connection conductor.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: April 9, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Nobuo Ikemoto
  • Patent number: 11940568
    Abstract: Devices, systems, and methods are provided for enhanced multispectral sensor calibration. A device may include a first layer having copper, a second layer having solder material, the second layer above the first layer, and a third layer having a white silkscreen material, the third layer above the second layer. Regarding the device, the first layer may be used for calibration of a thermal sensor, the second layer may be used for calibration of an image sensor and calibration of a light detection and ranging (LIDAR) sensor, and the third layer may be used for the calibration of the image sensor and the calibration of the LIDAR sensor.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 26, 2024
    Assignee: Argo AI, LLC
    Inventor: Michel H. J. Laverne
  • Patent number: 11937369
    Abstract: A component carrier related body which includes a stack with a plurality of electrically conductive and/or electrically insulating layer structures, and at least two information carrying structures formed vertically displaced on at least two different of the layer structures, wherein at least two of the at least two information carrying structures are laterally displaced in a plan view on the stack.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 19, 2024
    Assignee: AT&S(China) Co. Ltd.
    Inventors: Seok Kim Tay, Azmi Ibrahim, Wenping Dai, Chunjie Shen
  • Patent number: 11929335
    Abstract: A semiconductor structure for wafer level bonding includes a bonding dielectric layer disposed on a substrate and a bonding pad disposed in the bonding dielectric layer. The bonding pad includes a top surface exposed from the bonding dielectric layer, a bottom surface opposite to the top surface, and a sidewall between the top surface and the bottom surface. A bottom angle between the bottom surface and sidewall of the bonding pad is smaller than 90 degrees.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: March 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Ming Lai
  • Patent number: 11927878
    Abstract: Provided is a projection screen. The projection screen includes a first transparent cover plate, a transparent touch panel, and a first nanoparticle layer, wherein the first nanoparticle layer and the first transparent cover plate are sequentially laminated on one side of the transparent touch panel, and the first nanoparticle layer comprises a plurality of dispersed nanoparticles of different particle sizes. A method for manufacturing a projection screen, a projection display system, and a projection display method are also provided.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: March 12, 2024
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guangyun Tong, Yu Zhang, Zhuolong Li, Xuefei Qin, Junning Su
  • Patent number: 11908497
    Abstract: A hard disk drive flexure assembly includes a base layer, a conductive layer, a plurality of electrical pads over the conductive layer, and a sidewall layer including sidewalls on each side of and extending higher than a corresponding electrical pad. Pre-solder bumps are formed between the sidewalls and over each pad. Use of sidewalls prevents the pre-solder bumps from undesirably bridging to an adjacent electrical pad and forming a short circuit, which might otherwise cause head-gimbal assembly (HGA) manufacturing failures and consequent increased cost. These techniques are especially relevant with narrow, high-density, small pitch electrical pads.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 20, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Irizo Naniwa, Kenichi Murata
  • Patent number: 11900720
    Abstract: A circuit board according to an embodiment includes: a substrate including one surface and the other surface; a first circuit pattern disposed on the one surface; and a second circuit pattern disposed on the other surface, wherein at least one via is formed in the substrate, and the first circuit pattern and the second circuit pattern are wire-bonded through the via to conduct electricity.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 13, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Seung Joon Kim, Yong Hyun Gwon, Yong Hyun Cho
  • Patent number: 11889627
    Abstract: A display device includes a first substrate, a second substrate, a plurality of drive ICs and at least one flexible circuit board. The first substrate has a first region and a second region near to the first region. The second substrate is disposed on the first region and has a lateral side. The plurality of drive ICs are disposed on the second region and arranged along the lateral side. The at least one flexible circuit board is disposed on the second region and disposed correspondingly to the lateral side. Wherein in a top view of the display device, each of the plurality of drive ICs does not overlap with the at least one flexible circuit board in a direction perpendicular to an extending direction of the lateral side.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 30, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Chin-Cheng Kuo, Chia-Chun Yang, Wen-Cheng Huang
  • Patent number: 11889620
    Abstract: A radio-frequency module includes a mounting board, a first electronic component, and a second electronic component. The second electronic component is lower in height than the first electronic component. The mounting board includes dielectric layers, conductive layers, and via-conductors. In the mounting board, the dielectric layers and the conductive layers are stacked in the thickness direction of the mounting board. The mounting board has a first region and a second region. The first region overlaps the first electronic component and extends from a first major surface to a second major surface. The second region overlaps the second electronic component and extends from the first major surface to the second major surface. In the mounting board, the conductive layers in the first region are fewer than the conductive layers in the second region. In the mounting board, the first region is thinner than the second region.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: January 30, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yutaka Shuto, Hiroshi Nishikawa, Tomomi Yasuda
  • Patent number: 11881457
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: January 23, 2024
    Assignee: Tahoe Research, Ltd.
    Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
  • Patent number: 11874579
    Abstract: A multi-layer device comprising a first substrate, a first electrically conductive layer on a surface thereof, and a first current modulating layer, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 16, 2024
    Assignee: HALIO, INC.
    Inventors: Howard S. Bergh, Jonathan Ziebarth, Nicolas Timmerman
  • Patent number: 11871526
    Abstract: A circuit board includes a substrate, a first circuit layer, a second circuit layer, and a third circuit layer. The substrate includes a base layer, a first metal layer formed on the base layer, and a seed layer formed on the first metal layer. The first circuit layer is located on the substrate and includes the first metal layer and a signal layer formed on a surface of the first metal layer. The second circuit layer is coupled to the first circuit layer and includes the first metal layer, the seed layer, and a connection pillar formed on a surface of the first metal layer and the seed layer. The third circuit layer is coupled to the second circuit layer and includes the seed layer and a coil formed on a surface of the seed layer.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: January 9, 2024
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventor: Jun Dai
  • Patent number: 11866837
    Abstract: The invention relates to a method for fabrication of a one-piece, metal-based component of simple shape offering the illusion of faceting and/or chamfering for forming all or part of the exterior part of a timepiece.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 9, 2024
    Assignee: Nivarox-FAR S.A.
    Inventors: Pierre Cusin, Alex Gandelhman, Michel Musy
  • Patent number: 11871513
    Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: January 9, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Shigeki Koya, Kenji Sasaki
  • Patent number: 11860499
    Abstract: A multi-layer device comprising a first substrate and a first electrically conductive layer on a surface thereof, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: January 2, 2024
    Assignee: HALIO, INC.
    Inventors: Howard S. Bergh, Jonathan Ziebarth, Nicolas Timmerman
  • Patent number: 11864312
    Abstract: According to one aspect of the present disclosure, a printed circuit board includes: an insulating base film; and a plurality of wiring portions formed on a surface of the base film, wherein the wiring portions include a seed layer that is directly or indirectly layered on the surface of the base film and a metal layer that is layered on the seed layer, wherein the base film has a wiring area including the plurality of wiring portions and a non-wiring area not including the wiring portions, wherein the plurality of wiring portions include at least one outermost boundary wiring portion and a plurality of inner wiring portions other than the outermost boundary wiring portion, wherein the outermost boundary wiring portion is formed on an outermost side of the base film in the wiring area and at a boundary between the wiring area and the non-wiring area, wherein an average width of the outermost boundary wiring portion is 30 ?m or more, wherein an average width of the inner wiring portions is 20 ?m or less, and w
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: January 2, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroshi Ueda, Ippei Tanaka, Takashi Kasuga, Masamichi Yamamoto
  • Patent number: 11853502
    Abstract: Display panel and display device are provided. The display panel includes an array substrate and a cover plate disposed opposite to the array substrate, touch electrode layers on a side of the cover plate facing the array substrate, and a plurality of first touch pads and a plurality of second touch pads disposed opposite to the plurality of the first touch pads. Each of the array substrate and the cover plate include a display area and a non-display area at least partially surrounding the display area. The non-display area of the array substrate includes a step area provided with bonding pads. The non-display area of the array substrate includes at least one irregularly-shaped area adjacent to the step area. A first touch pad is electrically connected to a second touch pad.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: December 26, 2023
    Assignees: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Qibing Wei, Peng Zhang, Xingyao Zhou, Wei Liu
  • Patent number: 11841746
    Abstract: A display device according to an embodiment comprises: an elastic member; and at least one panel from among a display panel and a touch panel which are arranged on the elastic member, wherein the elastic member includes one surface and the other surface opposite to the one surface, the elastic member includes a first area and a second area, the first area is defined as a folding area, the second area is defined as an unfolding area, the elastic member has a plurality of first grooves arranged on the one surface in the first area thereof, and the panel is arranged on the other surface of the elastic member via an adhesive layer.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: December 12, 2023
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sung Won Kang, Jae Seok Park
  • Patent number: 11842016
    Abstract: A flexible display device is provided that includes a display panel having an active area including a plurality of pixels displaying an image and a non-active area surrounding the active area, first data pads disposed in the non-active area adjacent to the active area of the display panel and electrically connected with the plurality of pixels, pads disposed in a direction away from the first data pads and the active area, second data pads disposed between the first data pads and the pads, and a protrusion pattern located between the second data pads and the third data pads and disposed on an upper part of the insulating layer.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: December 12, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kiyoung Sung, Sangho Kim, Eunjin Oh
  • Patent number: 11842828
    Abstract: Transparent conductive films comprising sparse metal conductive layers are processed after coating with an overcoat to lower the sheet resistance of the film. The sparse metal conductive layer can comprise a fused metal nanostructured network. A coating, such as a polymer overcoat or a polymer undercoat can noble metal ions that can further reduce the sheet resistance with the application of heat and optionally humidity. In particular, silver ions in a coating are demonstrated to provide important stabilization of sparse metal conductive layers, whether or not fused, upon the application of heat and humidity. A coating can further comprise a metal salt stabilization composition.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: December 12, 2023
    Assignee: C3 Nano, Inc.
    Inventors: Xiqiang Yang, Ajay Virkar
  • Patent number: 11839029
    Abstract: One aspect provides an apparatus for locking circuit boards in position between a pair of guide rails. The apparatus can include a slider attached to a sidewall of one guide rail. The slider is allowed to slide along the guide rail within a predetermined range and one or more plunger-and-spring assemblies. A respective plunger-and-spring assembly comprises a plunger and a spring surrounding the plunger, and the plunger is inserted into a through-hole on the sidewall of the guide rail such that a first end of the plunger can be aligned with a notch on a corresponding circuit board and a second end of the plunger is in contact with the slider. Sliding of the slider causes the spring to compress and decompress and the first end of the plunger to move in and out of the notch on the circuit board, thereby facilitating locking and unlocking of the circuit board.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: December 5, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Warren A. Kartadinata, Neil Jefferson Asmussen, Vance B. Murakami
  • Patent number: 11836955
    Abstract: Aspects of the disclosure relate to determining a sign type of an unfamiliar sign. The system may include one or more processors. The one or more processors may be configured to receive an image and identify image data corresponding to a traffic sign in the image. The image data corresponding to the traffic sign may be input in a sign type model. The processors may determine that the sign type model was unable to identify a type of the traffic sign and determine one or more attributes of the traffic sign. The one or more attributes of the traffic sign may be compared to known attributes of other traffic signs and based on this comparison, a sign type of the traffic sign may be determined. The vehicle may be controlled in an autonomous driving mode based on the sign type of the traffic sign.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: December 5, 2023
    Assignee: Waymo LLC
    Inventors: Zhinan Xu, Maya Kabkab, Chen Wu, Woojong Koh
  • Patent number: 11839019
    Abstract: A communication module includes a first wiring board including a plurality of first signal lines and a first ground line, and a second wiring board including a first layer and a second layer. The first layer includes a plurality of second signal lines. The second layer includes a shielding member. The communication module includes a plurality of first connection members via which the plurality of first signal lines are electrically connected to the plurality of second signal lines, and at least one conductive member provided between the first ground line and the shielding member. The at least one conductive member is provided so as to overlap with at least one second signal line among the plurality of second signal lines as viewed in a direction perpendicular to a main surface of the first wiring board.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: December 5, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomohisa Ishigami, Makoto Aoki, Yuya Okada
  • Patent number: 11829133
    Abstract: A vehicle remote control system includes a server including a transceiver and a controller. The transceiver is configured to receive location data from a vehicle and location data from a remote device. The controller is configured to receive an operating instruction signal from the remote device, the operating instruction signal including instructions to operate one or more components of the vehicle. A distance between the vehicle and the remote device is determined based on the location data from the vehicle and the location data from the remote device. The operating instruction signal is transmitted to the vehicle in response to a determination that the distance between the vehicle and the remote device is equal to or less than a corresponding threshold distance.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 28, 2023
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventor: Masashi Nakagawa
  • Patent number: 11832393
    Abstract: An information handling system printed circuit board includes solder pads that accept footprint compatible integrated circuits, such as charger integrated circuits that provide power with different choke circuit supporting components. Solder pads for supporting components include first and second conductive areas sized to accept a first supporting component, each of the first and second conductive areas including an intervening non-conductive area that manages positioning of a smaller second supporting component at solder reflow.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: November 28, 2023
    Assignee: Dell Products L.P.
    Inventors: Yu-Lin Tsai, Chia-Hsien Lu, Chun-Min He, RungLung Lin, Chin-Chung Wu
  • Patent number: 11824287
    Abstract: Disclosed is an apparatus for electrically contacting a control/evaluation electronics of a field device of automation technology with an external energy supply and/or a controller, wherein the control/evaluation electronics of the field device is arranged on a circuit card, wherein at least one terminal box is provided, in which a plurality of adjoining electrical connection terminals are provided, wherein the electrical connection terminals serve, in each case, for accommodating an electrical connecting element, wherein the electrical connecting elements are connected mechanically and electrically with the circuit card, in each case, via a solder pad, and wherein there are provided between each two solder pads vacancies in the circuit card, which are so embodied that the length of the leakage preventing distance between the solder pads satisfies a predetermined ignition protection type.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: November 21, 2023
    Assignee: Endress+Hauser SE+Co. KG
    Inventors: Michael Dötsch, Robert Schmidt, Ralf Leisinger
  • Patent number: 11818840
    Abstract: A printed wiring board includes an electrode pad to be soldered to an electrode of an electronic component, an electrode pad to be soldered to an electrode of the electronic component, a barrier conductor continuous with the electrode pad, and a barrier conductor continuous with the electrode pad, the barrier conductor and the barrier conductors are located at positions facing each other with a gap area therebetween, the barrier conductor and the electrode pads are positioned such that the electrode pad faces the gap area with the barrier conductor therebetween and that the electrode pad faces the gap area with the barrier conductor therebetween, and the gap area is an area in which an adhesive is placed when adhering the electronic component.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: November 14, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Shigeta, Masato Morita, Hironobu Fukushima, Masahiro Koyama, Naoki Matsumoto
  • Patent number: 11804428
    Abstract: Disclosed is a package and method of forming the package with a mixed pad size. The package includes a first set of pads having a first size and a first pitch, where the first set of pads are solder mask defined (SMD) pads. The package also includes a second set of pads having a second size and a second pitch, where the second set of pads are non-solder mask defined (NSMD) pads.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: October 31, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Wen Yin, Yonghao An, Manuel Aldrete
  • Patent number: 11797123
    Abstract: A coplanar sensor includes a plurality of first sensing units and a plurality of second sensing units. Each of the first sensing units includes a plurality of first electrode blocks that are spaced apart from each other in a first direction, and a first connecting line that is electrically coupled to the first electrode blocks. Each of the second sensing units includes a plurality of second electrode blocks that are spaced apart from each other in a second direction intersecting the first direction, and a second connecting line that is electrically coupled to the second electrode blocks. Each of the first electrode blocks has a first sensing surface. Each of the second electrode blocks has a second sensing surface. The first sensing surfaces of the first electrode blocks and the second sensing surfaces of the second electrode blocks are coplanar.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: October 24, 2023
    Inventors: William Wang, Yu-Sung Su
  • Patent number: 11800641
    Abstract: Here are described composite panels comprising at least one integrated or embedded electrical circuit, their methods of manufacturing and their use in the aeronautic and aircraft industries. Also described are aircraft components including the composite panel as defined herein.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: October 24, 2023
    Assignee: HUTCHINSON AERONAUTIQUE & INDUSTRIE LTÉE.
    Inventors: Martin Levesque, Jean-Philippe Larose, Franck Guillemand
  • Patent number: 11783998
    Abstract: The present disclosure relates to a process to integrate sintered components in a laminate substrate. The disclosed process starts with providing a precursor substrate, which includes a substrate body having an opening through the substrate body, and a first foil layer. Herein, the first foil layer is formed underneath the substrate body, so as to fully cover a bottom of the opening. Next, a sinterable base material is applied into the opening and over the first foil layer, and then sintered at a first sintering temperature to create a sintered base component. A sinterable contact material is applied over the sintered base component, and then sintered at a second sintering temperature to create a sintered contact film. The sintered base component is confined within the opening by the substrate body on sides, by the first foil layer on bottom, and by the sintered contact film on top.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 10, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Tarak A. Railkar, Deepukumar M. Nair, Jeffrey Dekosky
  • Patent number: 11776883
    Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: October 3, 2023
    Assignee: GaN Systems Inc.
    Inventors: Cameron McKnight-MacNeil, Greg P. Klowak
  • Patent number: 11768569
    Abstract: A touch substrate and a method of forming the same, and a touch display device are provided. The touch substrate includes: electrode connecting bridges, a signal wiring layer, an insulating layer and a touch electrode layer which are sequentially formed along a direction away from a base, where the touch electrode layer includes a plurality of first touch electrodes and a plurality of second touch electrodes, and the first touch electrodes and the second touch electrodes are arranged in a crossed manner.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: September 26, 2023
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zouming Xu, Xiaofeng Yin, Tsungchieh Kuo, Jian Tian, Chunjian Liu
  • Patent number: 11758658
    Abstract: A display panel having a bonding region for bonding a flexible printed circuit in a peripheral region is provided. The display panel includes a plurality of first signal lines on a base substrate; and a plurality of bonding pins on the base substrate and in the bonding region. The plurality of bonding pins include a plurality of first bonding pins respectively electrically connected to the plurality of first signal lines. The display panel further includes a plurality of connecting portions respectively connecting the plurality of first signal lines portions to the plurality of first bonding pin portions. A respective one of the plurality of first bonding pin portions and a respective one of the plurality of connecting portions are substantially parallel to each other, and are arranged at a substantially same inclined angle with respect to a respective one of the plurality of first signal line portions.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 12, 2023
    Assignees: Chengdu BOE Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Donghui Tian, Bo Zhang, Zhiwen Chu, Rong Wang, Yulong Wei
  • Patent number: 11744009
    Abstract: An electronic module, such as a VRM, has a power inductor and power wave pins disposed on a bottom surface of a circuit board so as to reduce the size and increase the heat dissipation capability of the VRM.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: August 29, 2023
    Assignee: CYNTEC CO., LTD.
    Inventors: Kaipeng Chiang, Da-Jung Chen, Bau-Ru Lu, Chun Hsien Lu
  • Patent number: 11737207
    Abstract: A printed circuit board (PCB) includes a substrate defining a major plane. A first side of the major plane is configured for mounting of functional circuit elements. A cable connector is mounted on a second side of the major plane of the substrate, opposite the first side, for coupling to a shielded radiofrequency (RF) communications cable. At least one component grounding layer is parallel to the major plane and configured for coupling to the functional elements. At least one cable grounding layer is parallel to the major plane and is separated from the at least one component grounding layer. Each cable grounding layer in the at least one cable grounding layer is coextensive with the substrate and is configured for coupling, through the connector, to shielding of the shielded RF communications cable, without coupling to any other component. Nodes of an RF communications system may be mounted on such PCBs.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 22, 2023
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Shaowu Huang, Dance Wu
  • Patent number: 11735232
    Abstract: A memory device includes a printed circuit board having a plurality of conductive layers; memory chips mounted over the printed circuit board, wherein the memory chips comprise at least a first number of memory chips and a second number of memory chips; a first power module mounted over the printed circuit board and for providing a first set of power supplies to the first number of memory chips through the plurality of conductive layers; and a second power module mounted over the printed circuit board and for providing a second set of power supplies to the second number of memory chips through the plurality of conductive layers.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 22, 2023
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventor: Christopher Cox