Abstract: Disclosed are a transparent antenna and a device. The transparent antenna includes: a first polymer layer; a first transparent antenna, wherein the first transparent antenna includes an antenna body and a partition region, and one side of the first polymer layer is provided with a grid-like conductive wire to form the antenna body; a second polymer layer, wherein the second polymer layer is provided at one side, where the first transparent antenna is provided, of the first polymer layer; and a second transparent antenna, wherein the second transparent antenna is provided at one side of the second polymer layer away from the first transparent antenna, the second transparent antenna includes an antenna body, and one side of the second polymer layer away from the first transparent antenna is provided with a grid-like conductive wire to form the antenna body.

Abstract: System for enabling circuit board surface-slot-edge connections. A main board includes a slot through its surfaces. At least one edge of the slot includes electrical contacts to the main board. An auxiliary board includes a connector component mounted on a surface that opposes a surface of the main board. When the connector component is aligned with the slot, the connector component can protrude vertically through the slot, in addition to moving laterally towards an edge of the slot. Electrical contacts on the edge of the slot can engage with electrical contacts in the connector component. This enables two boards to be arranged closely, without extending the main surface in an orthogonal or lateral direction, using a secure connection provided by a connector attached to the auxiliary board, rather than the main board.

Abstract: Provided is a wiring circuit board that includes a first insulating layer, a conductive pattern disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the conductive pattern, and a third protective layer disposed between the conductive pattern and the second insulating layer and protecting the conductive pattern. The third protective layer consists of a metal oxide.

Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Abstract: A display device including a display panel and an input sensor including detection electrodes overlapping an active area, and first trace lines connected to the detection electrodes, having a portion overlapping the active area, and including mesh lines overlapping the active area, having a portion extending in a first direction, and including a first row mesh line having a portion extending in the first direction, and a second row mesh line having a portion extending in the first direction, and spaced apart from the first row mesh line in a second direction, and a second portion electrically connected to the mesh lines, overlapping the peripheral area, extending in the second direction, and including a first column wiring connected to the first row mesh line and extending in the second direction, and a second column wiring connected to the second row mesh line and extending in the second direction.

Abstract: A monomer represented by Chemical Formula (1): wherein, X, Y, and Z are the same as described in the specification, and the polymer including repeat units derived from the monomer.

Abstract: An electronic component mounting substrate includes: a metal substrate including a first surface, an insulation substrate including a second surface on which a first metal layer having a frame shape is provided, and a bonding material that bonds the first surface and the first metal layer. The bonding material is located in a region that includes the first metal layer and that is surrounded by the first metal layer in a plane perspective.

Abstract: A liquid container connected to a liquid ejection apparatus for ejecting a liquid, includes a container for containing liquid and a filter section for collecting foreign matter, an injection port for injecting the liquid into the container and a lead out port for leading out the liquid from the container are opened in the container, and the filter part is positioned in the injection port.

Abstract: A semiconductor product, which comprises a semiconductor chip, an edge integrity detection structure extending along at least part of an edge of the semiconductor chip, and evaluation circuitry formed in and/or on the semiconductor chip, being electrically connected with the edge integrity detection structure, and being configured to evaluate an electric characteristic of the edge integrity detection structure to provide an evaluation signal indicative of a detected edge integrity status of the edge.

Abstract: A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.

Abstract: A display apparatus includes: a substrate comprising a display area and a peripheral area outside the display area; a first insulating layer covering the peripheral area; a plurality of first pads on the first insulating layer in the peripheral area; a second insulating layer on the first insulating layer in the peripheral area, the second insulating layer having an opening exposing the plurality of first pads; and a first wiring comprising a 1-1st wiring and a 1-2nd wiring, wherein, in a plan view, the 1-1st wiring is under the first insulating layer to cross the opening of the second insulating layer in the peripheral area, the 1-2nd wiring is electrically connected to the 1-1st wiring outside the opening in the second insulating layer, and the 1-2nd wiring is between the first insulating layer and the second insulating layer.

Abstract: A host device includes surface mount conductive pads on a printed circuit board (PCB) for external peripheral communications. Conductive ink is printed on the conductive pads with a base member is printed over the conductive ink. Three-dimensional (3D) conductive wires are printed on the base member and extend along a housing to a new external port. Conductive ink is printed with a second base member and terminating ends of the wires are printed on the front of the base member establishing the new peripheral port for the host device. A peripheral device includes its own surface mount conductive pads which when aligned and brought into contact with the external port of the host device permits the host device and the peripheral device to establish a wired connection with one another without cables, without cable harnesses, and without port connectors.

Abstract: An interface in accordance with present embodiments includes a base and a theme portion disposed on the base. A first layer is disposed on the base and includes a mixture with metallic powder suspended within a translucent medium. A second layer is disposed on the base over the first layer and over the theme portion, and includes the mixture. A third layer is disposed on the base and on the theme portion over only portions of the second layer. The third layer includes paint and paint thinner. A fourth layer is disposed on the theme portion over the third layer and exposed portions of the second layer. The fourth layer also includes the mixture.

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.

Abstract: Disclosed is solar cell, a photovoltaic module, and a method for manufacturing a photovoltaic module. The solar cell includes a substrate, first busbars and second busbars arranged on the substrate, first fingers connected to the first busbars, and second fingers connected to the second busbars. The first busbars and the second busbars have opposite polarities. The first fingers have a same polarity as the first busbars, and the second fingers have a same polarity as the second busbars. The substrate is provided with busbar pits. At least part of the first and second busbars are located in the busbar pits. Depths of the busbar pits range from 30 ?m to 50 ?m. Along a thickness direction of the substrate, ratios of the depths of the busbar pits to heights of the first busbars and/or the second busbars range from 10:3 to 6:5.

Abstract: A circuit board includes an insulating substrate layer, a ground layer, an insulating layer, insulating through holes, a signal transmission layer and a polymer conductive member. The ground layer is disposed between the insulating layer and the insulating substrate layer. The signal transmission layer is disposed on one side of the insulating layer opposite to the ground layer. The insulating through holes penetrate through the signal transmission layer and the insulation layer to connect to the ground layer. The polymer conductive member is disposed within the insulating through holes, and one part thereof is electrically connected to the ground layer, and another part thereof extends outwards from the signal transmission layer.

Abstract: Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.

Abstract: An interconnect substrate includes a pad for external connection and an insulating layer, wherein a portion of a lower surface of the pad is covered with the insulating layer, wherein an upper surface of the pad is situated at a lower position than an upper surface of the insulating layer, and wherein a groove whose bottom surface is formed by the insulating layer is formed around the pad in a plan view, and has an opening on an upper surface side of the insulating layer.

Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member.

Abstract: An electronic component housing package includes an insulating substrate including a first surface with a mounting region mounting an electronic component, a second surface located opposite to the first surface, a plurality of side surfaces located between the first surface and the second surface, and a corner portion located between two of the side surfaces; an external connection conductor located on the second surface; and a corner conductor connected to the external connection conductor. The corner conductor is located from the external connection conductor toward the corner portion in a manner to increase the distance from the second surface.

Abstract: The present invention relates to solder particles, each of which partially has a flat portion in the surface. By using these solder particles, electrodes facing each other are able to be appropriately connected, thereby achieving an anisotropic conductive material that exhibits excellent conduction reliability and excellent insulation reliability.

Abstract: Devices including electrical connections to embedded electronic components and methods of making the same are provided. The devices include a flexible electronic component buried inside a substrate. The free end of the flexible electronic component can be extracted to stick out of the major plane of the substrate as a projecting contact.

Abstract: A printed circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and having an upper surface exposed through the cavity; wherein the cavity includes a first part including a first inner wall; and a second part including a second inner wall under the first part; and wherein an inclination angle of the first inner wall is different from an inclination angle of the second inner wall.

Abstract: An electronic device comprises a waveguide block defining a cavity therein. The device has a monolithic microwave or millimetre-wave integrated circuit device positioned at least partially in the cavity. The integrated circuit device comprises a dielectric substrate and a metal foil layer that extends outwards from an external edge of the dielectric substrate. The metal foil layer and the dielectric substrate define a through hole, wherein a first edge of the through hole is an edge of the metal foil layer and defines an end of the elongate waveguide channel, and wherein the metal foil layer at least partly determines both a length and a width of an elongate waveguide channel within the cavity.

Abstract: A display device including a first sensor part that includes a first trunk portion, a first branch portion connected to the first trunk portion and extending in a direction different from a first direction and a second direction, a second branch portion spaced apart from the first branch portion, and a bridge connecting the first branch portion to the second branch portion. A second sensor part includes a second trunk portion extending in the second direction, and a third branch portion disposed between the first branch portion and the second branch portion.

Abstract: A wiring substrate according to the present disclosure includes: an insulation layer disposed at an outermost layer; an electrode conductor disposed at a surface of the insulation layer with a seed layer being interposed therebetween; a nickel layer configured to cover at least one of the electrode conductors and include a contact portion that comes into contact with a surface of the seed layer; and a gold layer configured to cover the nickel layer. The nickel layer includes a plurality of gaps at the contact portion, at least a portion of the gaps includes an opening toward the contact portion, and a portion of the gold layer is disposed in at least a portion of the gaps.

Abstract: According to one embodiment, a flexible substrate includes an insulating base including a first surface and a second surface on an opposite side to the first surface, a wiring layer provided on the second surface side of the insulating base and a resin layer including a support located on the first surface side of the insulating base and a coating layer located on the second surface side of the insulating base, the resin layer including a first area and a second area in planar view, the resin layer having a first elastic modulus in the first area and a second elastic modulus in the second area, and the first elastic modulus being greater than the second elastic modulus.

Abstract: A method for producing an electrically conductive component having a cavity is described. An efficient production method for such a component, which allows a high variability of the wall thickness of the component, is implemented by applying a load-bearing layer consisting of an electrically conductive material to a soluble substrate and then dissolving and at least partially removing the substrate.

Abstract: A flying probe includes a test module and a processor. The test module measures a plurality of delta capacitances associated with a plurality of vias in a printed circuit board. The plurality of vias include first, second, third and fourth vias. Each different delta capacitance is measured between a different pair of the vias. The processor compares all the delta capacitances to a threshold value. In response to multiple delta capacitances associated with the first via being greater than or equal to the threshold value, the processor detects a possible via stripping issue for the first via.

Abstract: A circuit board and an electronic device are provided. The circuit board includes a circuit board body (10) and a shielding film layer (11), and further includes a dielectric layer (12), where the dielectric layer (12) is arranged between the circuit board body (10) and the shielding film layer (11).

Abstract: A method of manufacturing a glass assembly to have an opaque boundary feature includes a step of forming a first glass substrate that is curved, with the first glass substrate having an outer surface (P1) and an opposing inner surface (P2), and a second glass substrate that is curved, with the second glass substrate having an inner surface (P3) and an opposing outer surface (P4). The method also includes a step of digitally-applying an organic ink without a mask on at least one of the P2 surface and the P3 surface. The method further includes curing the organic ink to form the opaque boundary feature on at least one of the P2 surface and the P3 surface. The method also further includes disposing a polymeric interlayer between the P2 surface and the P3 surface.

Abstract: A flexible hybrid electronic system and method includes a first structure and a second structure. The first structure includes a first flexible substrate, a first electronic component secured to the first flexible substrate, and a first flexible conductive trace formed in part from conductive gel. The second structure includes a second flexible substrate, a second electronic component secured to the second flexible substrate, and a second flexible conductive trace formed in part from conductive gel. The first structure is bonded to the second structure at an interconnect region, the first conductive trace is electrically coupled to the second conductive trace within the interconnect region, and the first electronic component is operatively coupled to the second electronic component.

Abstract: A semiconductor device includes an inductance structure and a shielding structure. The shielding structure is arranged to at least partially shield the inductance structure from external electromagnetic fields. The shielding structure includes a shielding structure portion arranged along a side of the inductance structure such that the shielding structure portion is around at least a portion of a perimeter of the inductance structure.

Abstract: The storage device unit includes: a substrate having a main surface and having a plurality of wiring layers stacked together; and a storage device that has a plate shape having a first surface and is disposed on the substrate, the first surface facing the main surface. The plurality of wiring layers includes a heat-generating layer having a heat-generating circuit.

Abstract: A dielectric substrate has a first surface including a first terminal connector and a second terminal connector located along a first side surface. A recess is between the first terminal connector and the second terminal connector. The recess has a first inner surface continuous with the first terminal connector, a second inner surface continuous with the second terminal connector, and a bottom surface between the first inner surface and the second inner surface. The first terminal connector has first wettability with a bond on its surface, and a first region has second wettability with the bond on its surface lower than the first wettability.

Abstract: A stretchable wiring board that includes: a stretchable substrate; a first stretchable wiring extending in a length direction on a main surface side of the stretchable substrate; and a second stretchable wiring extending in the length direction on the main surface side of the stretchable substrate, the second stretchable wiring having a first portion with a first region overlapping on top of the first stretchable wiring on an end portion side of the first stretchable wiring, and a width of the first portion of the second stretchable wiring in a width direction orthogonal to the length direction is smaller than a width of the first stretchable wiring.

Abstract: A method of manufacturing a component carrier is described. The method includes forming a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure, and reducing an amount of solvent in a fiber-free dielectric layer, which is directly connected to a metal layer, so that the dielectric layer with reduced amount of solvent remains at least partially uncured.

Abstract: An optical stack structure includes a metal nanowire layer and an organic polymer layer. A crosslinking degree of the organic polymer layer is greater than or equal to 80% and less than or equal to 100%, and a content of volatile organic compounds in the organic polymer layer is less than or equal to 1%. The content of the volatile organic compounds in the organic polymer layer is defined as a difference between a thermal weight loss of the organic polymer layer measured at a measuring temperature and a water content of the organic polymer layer measured at the measuring temperature.

Abstract: A connection body, a method for manufacturing a connection body, and a connection method which can secure conduction reliability by trapping conductive particles even when the bump size is minimized. In a connection body in which a first component having a first electrode and a second component having a second electrode are connected to each other via a filler-containing film having a filler-aligned layer in which independent fillers are aligned in a binder resin layer, the maximum effective connection portion area where the first electrode and the second electrode face each other is 4,000 ?m2 or less and a ratio of the effective connection portion area to a particle area on the connection portion projection plane is 3 or more.

Abstract: A wiring member with a fixing member includes a flat wiring member, and a fixing member. The flat wiring member includes a plurality of wire-like transmission members and a base material. The plurality of wire-like transmission members are fixed to the base material in an arrayed state. The fixing member includes a plate-like part and a fixing part. The plate-like part is formed into a plate-like shape elongated in one direction, and the plate-like part is attached to the base material while a main surface of the plate-like part comes in surface contact with the base material. The fixing part is a part being provided to project on the plate-like part and being configured to fix the flat wiring member to a fixing target.

Abstract: A shielded printed wiring board includes a substrate film including a base film and printed circuits including a ground circuit formed on the base film; an electromagnetic wave shielding film including a shielding layer and an insulating layer; and a reinforcing member including a conductive adhesive layer and a metal reinforcing plate, wherein the ground circuit of the substrate film is sufficiently electrically connected to the metal reinforcing plate of the reinforcing member.

Abstract: In an example 3D printing method, an electrical conductivity value for a resistor is identified. Based upon the identified electrical conductivity value, a predetermined amount of a conductive agent is selectively applied to at least a portion of a build material layer in order to introduce a predetermined volume percentage of a conductive material to the resistor. Based upon the identified electrical conductivity value and the predetermined volume percent of the conductive material, a predetermined amount of a resistive agent is selectively applied to the at least a portion of the build material layer in order to introduce a predetermined volume percentage of a resistive material to the resistor. The build material layer is exposed to electromagnetic radiation, whereby the at least the portion coalesces to form a layer of the resistor.

Abstract: Technologies and implementations for a clip to connect coaxial cables onto a printed circuit board assembly (PCBA) are disclosed. The technologies and implementations facilitate improved signal integrity from the cable to various components of the PCBA. Additionally, the technologies and implementations help facilitate management of mechanical variations during connection of the coaxial cable.

Abstract: Each of first electrode sections forming a transmission electrode includes a first main line and a plurality of first auxiliary lines. Each of second electrode sections forming a reception electrode includes a second main line and a plurality of second auxiliary lines. With the transmission and reception electrodes and overlapping each other, the first main line and the second main line intersect with each other at one point, and a cell region is unclosed. The cell region is surrounded by two or more types of thin wires selected from a group consisting of the first main line, the first auxiliary lines, the second main line, and the second auxiliary lines.

Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including first and second pads, a solder resist layer formed on the base layer, covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, a first bump formed on the first pad and including a base plating layer and a top plating layer, and a second bump formed on the second conductor pad and including a base plating layer and a top plating layer. The second opening has diameter smaller than diameter of the first opening, the second bump has diameter smaller than diameter of the first bump, the first pad has a first recess formed on the first pad, the second pad has a second recess formed on the second pad, and the first recess is larger than the second recess.

Abstract: A circuit board includes a first insulating layer; a first wiring pattern and a second wiring pattern each formed to be side to side with each other on an upper surface of the first insulating layer; a second insulating layer formed on the upper surface of the first insulating layer to cover the first and second wiring patterns; a third wiring pattern formed on an upper surface of the second insulating layer to overlap the first wiring pattern in a vertical direction; a fourth wiring pattern formed on the upper surface of the second insulating layer to overlap the second wiring pattern in the vertical direction; a first via passing through the second insulating layer and connecting the first and fourth wiring patterns; and a second via passing through the second insulating layer and connecting the second and third wiring patterns.

Abstract: A transmission line includes a first structure including a first flexible resin base material, and a first ground conductor thereon, a second structure including a second flexible resin base material, and a first signal line and an interlayer connection conductor in or on the second resin base material, a first spacer between the first and second structures, and a first metal joining material joining the first and second structures with the first spacer interposed therebetween. A first hollow portion is between the first and second structures with the first spacer interposed therebetween. The first signal line and the first ground conductor face each other in a joining direction with the first hollow portion interposed therebetween. The first resin base material and the second resin base material are not in contact with each other. The first metal joining material has a melting point lower than that of the interlayer connection conductor.

Abstract: A display device includes a display panel and an integrated circuit chip configured with a plurality of first bonding terminals spaced apart from each other. The display panel is provided with a plurality of second bonding terminals, and a first insulating layer is disposed between the first bonding terminals and the second bonding terminals. A plurality of electrically conductive particles are provided on the second bonding terminals and penetrate the first insulating layer so that the electrically conductive particles are in contact with the first bonding terminals.

Abstract: The invention provides a printed circuit board assembly (1) comprising (i) an at least partly folded flexible printed circuit board (100), and (ii) an at least partly folded support (200), wherein: —the at least partly folded flexible printed circuit board (100) comprises a first PCB region (110) and a second PCB region (120), wherein at least part of the second PCB region (120) is configured folded over at least part of the first PCB region (110); —the at least partly folded support (200) is configured to support at least part of the at least partly folded flexible printed circuit board (100), wherein the at least partly folded support (200) comprises a first support region (210) and a second support region (220), wherein at least part of the second support region (220) is configured folded over at least part of the first support region (210), wherein at least part of the at least partly folded flexible printed circuit board (100) is configured between the first support region (210) and the second support re