Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
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Patent number: 12382577Abstract: Disclosed is a flexible PCB RF cable having a ground pattern that is divided into two ground patterns, which are connected through a connection pattern arranged in an area overlapped with a signal line pattern, and thus cracks are minimized during bending. The disclosed flexible PCB RF cable comprises: a signal line pattern interposed between a first dielectric sheet and a second dielectric sheet; first and second lower ground patterns, which are mesh patterns arranged to be spaced from each other below the first dielectric sheet; a lower connection pattern connected to the first and second lower ground patterns; first and second upper ground patterns, which are mesh patterns arranged to be spaced from each other above the second dielectric sheet; and an upper connection pattern connected to the first and second ground patterns.Type: GrantFiled: May 31, 2021Date of Patent: August 5, 2025Assignee: AMOSENSE CO., LTDInventors: Jeonggeun Heo, Seho Lee, Jeongsang Yu, Hyungil Baek
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Patent number: 12378687Abstract: Devices including high-aspect ratio electroplated structures and methods of forming high-aspect ratio electroplated structures are described. A method for manufacturing metal structures includes providing a substrate having a metal base characterized by a height to width aspect ratio A/B and electroplating a metal crown on the base to form the metal structure with a height to width aspect ratio A/S greater than the aspect ratio A/B of the base.Type: GrantFiled: March 23, 2020Date of Patent: August 5, 2025Assignee: Hutchinson Technology IncorporatedInventors: Douglas P. Riemer, Kurt C. Swanson, Peter F. Ladwig
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Patent number: 12382580Abstract: A printed circuit board includes: a plurality of insulating layers; a plurality of wiring pattern layers disposed on at least one surface of the plurality of insulating layers; a via connecting wiring pattern layers, among the plurality of wiring pattern layers, disposed on upper and lower surfaces of one of the plurality of insulating layers to each other; a connection pad disposed on a surface of an outermost layer among the plurality of insulating layers; and a solder resist having a hole exposing at least a portion of the connection pad. An external surface of the solder resist has surface roughness.Type: GrantFiled: May 17, 2022Date of Patent: August 5, 2025Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jung Han Kim, Youn Gyu Han
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Patent number: 12376231Abstract: Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.Type: GrantFiled: March 11, 2024Date of Patent: July 29, 2025Assignee: Apple Inc.Inventors: Anne M. Mason, Chad O. Simpson, William Hannon, Mark J. Beesley
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Patent number: 12366942Abstract: A touch screen sensor includes a visible light transparent substrate and an electrically conductive micropattern disposed on or in the visible light transparent substrate. The micropattern includes a first region micropattern within a touch sensing area and a second region micropattern. The first region micropattern has a first sheet resistance value in a first direction, is visible light transparent, and has at least 90% open area. The second region micropattern has a second sheet resistance value in the first direction. The first sheet resistance value is different from the second sheet resistance value.Type: GrantFiled: July 23, 2024Date of Patent: July 22, 2025Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Matthew H. Frey, Michael J. Robrecht, George F. Jambor
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Patent number: 12369245Abstract: Provided is a printed circuit board for degradation detection, the printed circuit board having an insulator substrate and a wiring pattern for degradation detection, the wiring pattern being formed on an outer surface of the insulator substrate, and the printed circuit board for degradation detection being attached to a main printed circuit board for which degradation is to be detected. The wiring pattern is formed on, of the outer surfaces of the insulator substrate, a back surface positioned on the main printed circuit board side. The insulator substrate has a penetrating part (through hole, notch part) penetrating from the back surface to a front surface positioned on the side opposite from the back surface.Type: GrantFiled: July 28, 2021Date of Patent: July 22, 2025Assignee: FANUC CORPORATIONInventors: Takeshi Sawada, Fuyuki Ueno
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Patent number: 12347759Abstract: A semiconductor package includes a substrate; a semiconductor chip on a first surface of the substrate; and a plurality of external connection terminals on a second surface of the substrate that is opposite to the first surface. The substrate includes a plurality of wirings configured to electrically connect the semiconductor chip and the plurality of external connection terminals. The plurality of wirings includes a first wiring, and the first wiring includes a first portion and a second portion connected to each other, the second portion overlapping an edge of the semiconductor chip in a vertical direction that is perpendicular to the first surface of the substrate. A second width of the second portion is greater than a first width of the first portion.Type: GrantFiled: February 2, 2022Date of Patent: July 1, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Mo Kwon, Dong Uk Kim, Jin Hee Hong
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Patent number: 12342459Abstract: Provided is a flexible printed wiring board including: a base film which is an insulating layer; a first conductor layer; a second conductor layer; and a through-hole, in which the first conductor layer is provided on one surface of the base film, the second conductor layer is provided on the other surface of the base film, and the through-hole is provided so as to penetrate the base film and electrically connect the first conductor layer and the second conductor layer to each other, and the second conductor layer has a solderable region.Type: GrantFiled: March 1, 2023Date of Patent: June 24, 2025Assignee: MEKTEC CORPORATIONInventors: Shunsuke Aoyama, Masanori Hirata
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Patent number: 12328820Abstract: A printed circuit board includes a substrate structure including a first insulating material, a plurality of first wiring layers disposed on or in the first insulating material, and a plurality of first via layers disposed in the first insulating material; and an interconnect structure including a second insulating material, a plurality of second wiring layers disposed on or in the second insulating material, and one or more second via layers disposed in the second insulating material. The interconnect structure is disposed on an upper side of the substrate structure. The interconnect structure includes first and second connection regions. The first and second connection regions are spaced apart from each other.Type: GrantFiled: September 28, 2022Date of Patent: June 10, 2025Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Gopal Garg, Jung Hyun Cho, Yong Ho Baek
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Patent number: 12300590Abstract: The present invention discloses a package structure and a method for forming the same. The package structure includes a substrate, a chip, a first plastic package layer and a support block, wherein the substrate includes a first surface and a second surface; the chip is disposed on the first surface; the first plastic package layer is disposed on the first surface and packages the chip; the support block is disposed on the second surface; and in a thickness direction of the substrate, an overlapping region exists between the chip and the support block, and a thermal expansion coefficient of the chip is equal to a thermal expansion coefficient of the support block. The support block can counteract part of stress to avoid problems such as warping or twisting. Due to the overlapping region, a counteraction function of the support block on the stress exerted on the chip can be improved.Type: GrantFiled: May 25, 2020Date of Patent: May 13, 2025Assignee: JCET GROUP CO., LTD.Inventor: Yaojian Lin
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Patent number: 12300578Abstract: A power electronic interposer (10) for mounting a number of power transistor integrated circuit dice (14) can be made from a multi-layer ceramic process to provide an aluminum nitride body (11) having internal tungsten traces (30-35) to electrically connect die bond pads (17,18) to interposer contact pads (25,26) allowing connection to circuitry off of the interposer. The traces can include one or more groupings of parallelly spaced apart conductive vias (30,31) that are connected in an electrically parallel manner to reduce electrical resistance and inductance in the circuitry. A network of cooling conduits and optional resistance temperature detector traces can be run through other parts of the body to provide controlled active cooling. The interposer can be formed separate ceramic bodies bonded together, to package the dice.Type: GrantFiled: July 31, 2020Date of Patent: May 13, 2025Assignee: TriPent Power LLCInventors: Stephen P. Nootens, Frank J. Polese, Steven S. Scrantom
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Patent number: 12292002Abstract: There is provided a casing assembly for a gas turbine engine comprising: a casing and electrically conductive intumescent material extending around the casing. The intumescent material is being activatable in response to electrical current to expand. The casing assembly comprises an electrical activation line extending around the casing to activate the intumescent material. The activation line extends in a pattern such that an activation area which circumscribes the activation line has an axial extent of at least 50% of the casing and a circumferential extent of at least 50%, to thereby activate the intumescent material at multiple locations over a corresponding area of the casing.Type: GrantFiled: March 19, 2019Date of Patent: May 6, 2025Assignee: ROLLS-ROYCE PLCInventor: Marcus J. George
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Patent number: 12295101Abstract: An electronic component comprises: a first board; a first flexible board that is used to connect the first board and a second board; and a first transmission wiring, formed on the first board, the second board and the first flexible board, that transmits a signal from the first board to the second board. One of the first flexible board is connected to the first board with a conductive connecting material, and a connector capable of attaching to and detaching from the second board is provided on the other end of the first flexible board.Type: GrantFiled: September 12, 2022Date of Patent: May 6, 2025Assignee: CANON KABUSHIKI KAISHAInventor: Naoyuki Nakagawara
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Patent number: 12269238Abstract: A multilayer resin substrate includes resin layers that are laminated, a first copper foil on the resin layers and including first and second main surfaces having first and second surface roughnesses, respectively, and a second copper foil on the resin layers and including third and fourth main surfaces having third and fourth surface roughnesses, respectively. A distance between the first main surface and the second copper foil is shorter than a distance between the second main surface and the second copper foil. When the first, second, third, and fourth surface roughnesses are denoted as SR1, SR2, SR3, and SR4 respectively, a relationship SR1<SR3?SR4<SR2 is satisfied.Type: GrantFiled: December 15, 2022Date of Patent: April 8, 2025Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Yoshimasa Nishi, Tomohiro Nagai
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Patent number: 12267955Abstract: An object of the present invention is to provide a technique capable of suppressing displacement of an electronic component and a solder ball without using a jig. A semiconductor device includes an insulating substrate, an electronic component, and solder. A metal pattern and a semiconductor element are disposed on the insulating substrate. The metal pattern has a first recess and a second recess that are provided side by side. A part of the electronic component is disposed in the first recess. The solder connects the metal pattern disposed on the insulating substrate and the electronic component.Type: GrantFiled: May 21, 2020Date of Patent: April 1, 2025Assignee: Mitsubishi Electric CorporationInventor: Takeshi Higashihata
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Patent number: 12255389Abstract: Disclosed are a transparent antenna and a device. The transparent antenna includes: a first polymer layer; a first transparent antenna, wherein the first transparent antenna includes an antenna body and a partition region, and one side of the first polymer layer is provided with a grid-like conductive wire to form the antenna body; a second polymer layer, wherein the second polymer layer is provided at one side, where the first transparent antenna is provided, of the first polymer layer; and a second transparent antenna, wherein the second transparent antenna is provided at one side of the second polymer layer away from the first transparent antenna, the second transparent antenna includes an antenna body, and one side of the second polymer layer away from the first transparent antenna is provided with a grid-like conductive wire to form the antenna body.Type: GrantFiled: June 6, 2022Date of Patent: March 18, 2025Assignee: SHINE OPTOELECTRONICS (KUNSHAN) CO., LTD.Inventors: Lidong Liu, Yulong Gao, Weiying Bao
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Patent number: 12249779Abstract: System for enabling circuit board surface-slot-edge connections. A main board includes a slot through its surfaces. At least one edge of the slot includes electrical contacts to the main board. An auxiliary board includes a connector component mounted on a surface that opposes a surface of the main board. When the connector component is aligned with the slot, the connector component can protrude vertically through the slot, in addition to moving laterally towards an edge of the slot. Electrical contacts on the edge of the slot can engage with electrical contacts in the connector component. This enables two boards to be arranged closely, without extending the main surface in an orthogonal or lateral direction, using a secure connection provided by a connector attached to the auxiliary board, rather than the main board.Type: GrantFiled: July 18, 2022Date of Patent: March 11, 2025Assignee: Aptiv Technologies AGInventor: Markus Neumann
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Patent number: 12238859Abstract: Provided is a wiring circuit board that includes a first insulating layer, a conductive pattern disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the conductive pattern, and a third protective layer disposed between the conductive pattern and the second insulating layer and protecting the conductive pattern. The third protective layer consists of a metal oxide.Type: GrantFiled: November 9, 2022Date of Patent: February 25, 2025Assignee: NITTO DENKO CORPORATIONInventors: Shusaku Shibata, Teppei Niino, Yosuke Nakanishi
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Patent number: 12230559Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.Type: GrantFiled: June 5, 2023Date of Patent: February 18, 2025Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Jefferson W. Hall, Michael J. Seddon
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Patent number: 12228858Abstract: A monomer represented by Chemical Formula (1): wherein, X, Y, and Z are the same as described in the specification, and the polymer including repeat units derived from the monomer.Type: GrantFiled: October 31, 2018Date of Patent: February 18, 2025Assignee: DUPONT SPECIALTY MATERIALS KOREA LTDInventors: Jae Hwan Sim, Suwoong Kim, Jin Hong Park, Myung Yeol Kim, Yoo-Jin Ghang, Jae-Bong Lim
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Patent number: 12232395Abstract: A display device including a display panel and an input sensor including detection electrodes overlapping an active area, and first trace lines connected to the detection electrodes, having a portion overlapping the active area, and including mesh lines overlapping the active area, having a portion extending in a first direction, and including a first row mesh line having a portion extending in the first direction, and a second row mesh line having a portion extending in the first direction, and spaced apart from the first row mesh line in a second direction, and a second portion electrically connected to the mesh lines, overlapping the peripheral area, extending in the second direction, and including a first column wiring connected to the first row mesh line and extending in the second direction, and a second column wiring connected to the second row mesh line and extending in the second direction.Type: GrantFiled: March 28, 2023Date of Patent: February 18, 2025Assignee: Samsung Display Co., Ltd.Inventors: Jaehyung Cho, Dong-Hoon Lee, Mukyung Jeon
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Patent number: 12224390Abstract: An electronic component mounting substrate includes: a metal substrate including a first surface, an insulation substrate including a second surface on which a first metal layer having a frame shape is provided, and a bonding material that bonds the first surface and the first metal layer. The bonding material is located in a region that includes the first metal layer and that is surrounded by the first metal layer in a plane perspective.Type: GrantFiled: March 23, 2021Date of Patent: February 11, 2025Assignee: KYOCERA CORPORATIONInventors: Kouichirou Sugai, Kazuki Nishimoto
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Patent number: 12219831Abstract: A display apparatus includes: a substrate comprising a display area and a peripheral area outside the display area; a first insulating layer covering the peripheral area; a plurality of first pads on the first insulating layer in the peripheral area; a second insulating layer on the first insulating layer in the peripheral area, the second insulating layer having an opening exposing the plurality of first pads; and a first wiring comprising a 1-1st wiring and a 1-2nd wiring, wherein, in a plan view, the 1-1st wiring is under the first insulating layer to cross the opening of the second insulating layer in the peripheral area, the 1-2nd wiring is electrically connected to the 1-1st wiring outside the opening in the second insulating layer, and the 1-2nd wiring is between the first insulating layer and the second insulating layer.Type: GrantFiled: July 20, 2021Date of Patent: February 4, 2025Assignee: Samsung Display Co., Ltd.Inventors: Changwon Jeong, Wonmi Hwang, Geurim Lee, Jaewon Cho
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Patent number: 12216153Abstract: A semiconductor product, which comprises a semiconductor chip, an edge integrity detection structure extending along at least part of an edge of the semiconductor chip, and evaluation circuitry formed in and/or on the semiconductor chip, being electrically connected with the edge integrity detection structure, and being configured to evaluate an electric characteristic of the edge integrity detection structure to provide an evaluation signal indicative of a detected edge integrity status of the edge.Type: GrantFiled: March 21, 2022Date of Patent: February 4, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Xiaoming Li, Liming Tsau, Andy Brotman
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Patent number: 12218020Abstract: A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.Type: GrantFiled: March 16, 2022Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Yu-Min Liang
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Patent number: 12214595Abstract: A liquid container connected to a liquid ejection apparatus for ejecting a liquid, includes a container for containing liquid and a filter section for collecting foreign matter, an injection port for injecting the liquid into the container and a lead out port for leading out the liquid from the container are opened in the container, and the filter part is positioned in the injection port.Type: GrantFiled: September 28, 2022Date of Patent: February 4, 2025Assignee: Seiko Epson CorporationInventors: Jun Shimazaki, Azusa Takagi, Kazuyoshi Mizuno, Shigenori Nakagawa
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Patent number: 12212054Abstract: An interface in accordance with present embodiments includes a base and a theme portion disposed on the base. A first layer is disposed on the base and includes a mixture with metallic powder suspended within a translucent medium. A second layer is disposed on the base over the first layer and over the theme portion, and includes the mixture. A third layer is disposed on the base and on the theme portion over only portions of the second layer. The third layer includes paint and paint thinner. A fourth layer is disposed on the theme portion over the third layer and exposed portions of the second layer. The fourth layer also includes the mixture.Type: GrantFiled: February 24, 2022Date of Patent: January 28, 2025Assignee: Universal City Studios LLCInventors: Richard Joseph Swim, Jr., George Peter Gakoumis, Jr., Matthew Tangan Usi, Jason William Hawk, Anthony Louis Mandile, Brian Matthew Stuckey, Vanessa Rachael Luedtke, Douglas Evan Goodner
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Patent number: 12213250Abstract: A host device includes surface mount conductive pads on a printed circuit board (PCB) for external peripheral communications. Conductive ink is printed on the conductive pads with a base member is printed over the conductive ink. Three-dimensional (3D) conductive wires are printed on the base member and extend along a housing to a new external port. Conductive ink is printed with a second base member and terminating ends of the wires are printed on the front of the base member establishing the new peripheral port for the host device. A peripheral device includes its own surface mount conductive pads which when aligned and brought into contact with the external port of the host device permits the host device and the peripheral device to establish a wired connection with one another without cables, without cable harnesses, and without port connectors.Type: GrantFiled: August 31, 2022Date of Patent: January 28, 2025Assignee: NCR Voyix CorporationInventors: John Paul Bacalso Aliganga, Jason Delos Angeles, Jan Angielee Alpuerto Gesite, Teofrenz Aralquez Ycot
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Patent number: 12207395Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.Type: GrantFiled: September 27, 2023Date of Patent: January 21, 2025Assignee: Amphenol CorporationInventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
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Patent number: 12199195Abstract: Disclosed is solar cell, a photovoltaic module, and a method for manufacturing a photovoltaic module. The solar cell includes a substrate, first busbars and second busbars arranged on the substrate, first fingers connected to the first busbars, and second fingers connected to the second busbars. The first busbars and the second busbars have opposite polarities. The first fingers have a same polarity as the first busbars, and the second fingers have a same polarity as the second busbars. The substrate is provided with busbar pits. At least part of the first and second busbars are located in the busbar pits. Depths of the busbar pits range from 30 ?m to 50 ?m. Along a thickness direction of the substrate, ratios of the depths of the busbar pits to heights of the first busbars and/or the second busbars range from 10:3 to 6:5.Type: GrantFiled: December 29, 2022Date of Patent: January 14, 2025Assignees: Jinko Solar Co., Ltd., Zhejiang Jinko Solar Co., Ltd.Inventors: Yuncheng Cao, Yingli Guan, Shiliang Huang, Zhiqiu Guo, Jianghai Du
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Patent number: 12200865Abstract: A circuit board includes an insulating substrate layer, a ground layer, an insulating layer, insulating through holes, a signal transmission layer and a polymer conductive member. The ground layer is disposed between the insulating layer and the insulating substrate layer. The signal transmission layer is disposed on one side of the insulating layer opposite to the ground layer. The insulating through holes penetrate through the signal transmission layer and the insulation layer to connect to the ground layer. The polymer conductive member is disposed within the insulating through holes, and one part thereof is electrically connected to the ground layer, and another part thereof extends outwards from the signal transmission layer.Type: GrantFiled: November 29, 2022Date of Patent: January 14, 2025Assignee: BIZLINK INTERNATIONAL CORP.Inventors: Shi-Jung Chen, Jui-Hung Chien, Yen-Chun Chen
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Patent number: 12191255Abstract: An interconnect substrate includes a pad for external connection and an insulating layer, wherein a portion of a lower surface of the pad is covered with the insulating layer, wherein an upper surface of the pad is situated at a lower position than an upper surface of the insulating layer, and wherein a groove whose bottom surface is formed by the insulating layer is formed around the pad in a plan view, and has an opening on an upper surface side of the insulating layer.Type: GrantFiled: October 14, 2022Date of Patent: January 7, 2025Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hikaru Tanaka, Takashi Kasuga, Tomoyuki Shimodaira, Hitoshi Kondo
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Patent number: 12191243Abstract: Novel tools and techniques are provided for implementing cantilevered power planes to provide a return current path for high-speed signals. In various embodiments, a semiconductor package includes a substrate core, a plurality of layers, and an AC coupler(s). The plurality of layers includes power, ground, and signal layers each layer disposed on or above the substrate core, each signal layer being disposed between a power layer and a ground layer, the power layer and the ground layer each providing a return path for high frequency (e.g., 1 kHz or greater) signals carried by each signal layer. Each dielectric layer is disposed between and in contact with a pair of power, ground, or signal layer. The AC coupler(s) is coupled to each of a power layer(s) and a ground layer(s), without any portion of any power layer that is near an edge of the substrate core being anchored to the substrate core.Type: GrantFiled: May 13, 2022Date of Patent: January 7, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Arun Ramakrishnan, Dharmendra Saraswat, Reza Sharifi, Sam Zhao, Sam Karikalan, Mayank Mayukh, Liming Tsau
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Patent number: 12183682Abstract: A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.Type: GrantFiled: July 9, 2021Date of Patent: December 31, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Chen, Chien-Hsun Lee, Chung-Shi Liu, Jiun-Yi Wu, Shou-Yi Wang, Tsung-Ding Wang
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Patent number: 12177983Abstract: An electronic component housing package includes an insulating substrate including a first surface with a mounting region mounting an electronic component, a second surface located opposite to the first surface, a plurality of side surfaces located between the first surface and the second surface, and a corner portion located between two of the side surfaces; an external connection conductor located on the second surface; and a corner conductor connected to the external connection conductor. The corner conductor is located from the external connection conductor toward the corner portion in a manner to increase the distance from the second surface.Type: GrantFiled: November 16, 2020Date of Patent: December 24, 2024Assignee: KYOCERA CorporationInventors: Yoshitomo Onitsuka, Keisuke Sawada
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Patent number: 12176214Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member.Type: GrantFiled: October 25, 2021Date of Patent: December 24, 2024Assignee: Intel CorporationInventors: Kevin Lin, Rahim Kasim, Manish Chandhok, Florian Gstrein
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Patent number: 12172240Abstract: The present invention relates to solder particles, each of which partially has a flat portion in the surface. By using these solder particles, electrodes facing each other are able to be appropriately connected, thereby achieving an anisotropic conductive material that exhibits excellent conduction reliability and excellent insulation reliability.Type: GrantFiled: June 26, 2019Date of Patent: December 24, 2024Assignee: RESONAC CORPORATIONInventors: Kunihiko Akai, Yoshinori Ejiri, Yuuhei Okada, Toshimitsu Moriya, Shinichirou Sukata, Masayuki Miyaji
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Patent number: 12156343Abstract: Devices including electrical connections to embedded electronic components and methods of making the same are provided. The devices include a flexible electronic component buried inside a substrate. The free end of the flexible electronic component can be extracted to stick out of the major plane of the substrate as a projecting contact.Type: GrantFiled: January 22, 2021Date of Patent: November 26, 2024Assignee: 3M INNOVATIVE PROPERTIES COMPANYInventors: Ankit Mahajan, Mikhail L Pekurovsky, Kara A. Meyers, Saagar A. Shah, Kayla C. Niccum
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Patent number: 12144116Abstract: A printed circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and having an upper surface exposed through the cavity; wherein the cavity includes a first part including a first inner wall; and a second part including a second inner wall under the first part; and wherein an inclination angle of the first inner wall is different from an inclination angle of the second inner wall.Type: GrantFiled: October 21, 2020Date of Patent: November 12, 2024Assignee: LG INNOTEK CO., LTD.Inventors: Jong Bae Shin, Soo Min Lee, Jae Hun Jeong
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Patent number: 12136757Abstract: An electronic device comprises a waveguide block defining a cavity therein. The device has a monolithic microwave or millimetre-wave integrated circuit device positioned at least partially in the cavity. The integrated circuit device comprises a dielectric substrate and a metal foil layer that extends outwards from an external edge of the dielectric substrate. The metal foil layer and the dielectric substrate define a through hole, wherein a first edge of the through hole is an edge of the metal foil layer and defines an end of the elongate waveguide channel, and wherein the metal foil layer at least partly determines both a length and a width of an elongate waveguide channel within the cavity.Type: GrantFiled: October 16, 2020Date of Patent: November 5, 2024Assignee: Teratech Components LimitedInventors: Byron Alderman, Jeffrey Powell
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Patent number: 12133442Abstract: A display device including a first sensor part that includes a first trunk portion, a first branch portion connected to the first trunk portion and extending in a direction different from a first direction and a second direction, a second branch portion spaced apart from the first branch portion, and a bridge connecting the first branch portion to the second branch portion. A second sensor part includes a second trunk portion extending in the second direction, and a third branch portion disposed between the first branch portion and the second branch portion.Type: GrantFiled: August 27, 2023Date of Patent: October 29, 2024Assignee: Samsung Display Co., Ltd.Inventors: Hyunjae Na, Jaseung Ku, Kwan-Ho Kim, Gyeongnam Bang, Hoseok Son, Sungyeon Cho
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Patent number: 12126232Abstract: A method for producing an electrically conductive component having a cavity is described. An efficient production method for such a component, which allows a high variability of the wall thickness of the component, is implemented by applying a load-bearing layer consisting of an electrically conductive material to a soluble substrate and then dissolving and at least partially removing the substrate.Type: GrantFiled: January 9, 2019Date of Patent: October 22, 2024Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.Inventors: Uwe Specht, Michael Heuser, Malte Burchardt, Franz-Josef Woestmann
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Patent number: 12127337Abstract: According to one embodiment, a flexible substrate includes an insulating base including a first surface and a second surface on an opposite side to the first surface, a wiring layer provided on the second surface side of the insulating base and a resin layer including a support located on the first surface side of the insulating base and a coating layer located on the second surface side of the insulating base, the resin layer including a first area and a second area in planar view, the resin layer having a first elastic modulus in the first area and a second elastic modulus in the second area, and the first elastic modulus being greater than the second elastic modulus.Type: GrantFiled: November 22, 2021Date of Patent: October 22, 2024Assignee: Japan Display Inc.Inventor: Takumi Sano
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Patent number: 12123907Abstract: A flying probe includes a test module and a processor. The test module measures a plurality of delta capacitances associated with a plurality of vias in a printed circuit board. The plurality of vias include first, second, third and fourth vias. Each different delta capacitance is measured between a different pair of the vias. The processor compares all the delta capacitances to a threshold value. In response to multiple delta capacitances associated with the first via being greater than or equal to the threshold value, the processor detects a possible via stripping issue for the first via.Type: GrantFiled: April 26, 2022Date of Patent: October 22, 2024Assignee: Dell Products L.P.Inventors: Ching-Huei Chen, Bhyrav Mutnury, Chun-Lin Liao, Chi-Hsiang Hung, Pei-Ju Lin
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Patent number: 12127340Abstract: A wiring substrate according to the present disclosure includes: an insulation layer disposed at an outermost layer; an electrode conductor disposed at a surface of the insulation layer with a seed layer being interposed therebetween; a nickel layer configured to cover at least one of the electrode conductors and include a contact portion that comes into contact with a surface of the seed layer; and a gold layer configured to cover the nickel layer. The nickel layer includes a plurality of gaps at the contact portion, at least a portion of the gaps includes an opening toward the contact portion, and a portion of the gold layer is disposed in at least a portion of the gaps.Type: GrantFiled: September 23, 2020Date of Patent: October 22, 2024Assignee: KYOCERA CORPORATIONInventors: Yoshihiro Hasegawa, Yasuhiro Higashikawa
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Patent number: 12108521Abstract: A circuit board and an electronic device are provided. The circuit board includes a circuit board body (10) and a shielding film layer (11), and further includes a dielectric layer (12), where the dielectric layer (12) is arranged between the circuit board body (10) and the shielding film layer (11).Type: GrantFiled: December 17, 2019Date of Patent: October 1, 2024Assignee: GUANGZHOU FANGBANG ELECTRONICS CO., LTDInventor: Zhi Su
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Patent number: 12090729Abstract: A method of manufacturing a glass assembly to have an opaque boundary feature includes a step of forming a first glass substrate that is curved, with the first glass substrate having an outer surface (P1) and an opposing inner surface (P2), and a second glass substrate that is curved, with the second glass substrate having an inner surface (P3) and an opposing outer surface (P4). The method also includes a step of digitally-applying an organic ink without a mask on at least one of the P2 surface and the P3 surface. The method further includes curing the organic ink to form the opaque boundary feature on at least one of the P2 surface and the P3 surface. The method also further includes disposing a polymeric interlayer between the P2 surface and the P3 surface.Type: GrantFiled: July 8, 2022Date of Patent: September 17, 2024Assignee: AGC Automotive Americas Co.Inventors: Jiangping Wang, Timothy D. Peck, Samuel Thomas Machi, Brandon Jones
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Patent number: 12096563Abstract: A flexible hybrid electronic system and method includes a first structure and a second structure. The first structure includes a first flexible substrate, a first electronic component secured to the first flexible substrate, and a first flexible conductive trace formed in part from conductive gel. The second structure includes a second flexible substrate, a second electronic component secured to the second flexible substrate, and a second flexible conductive trace formed in part from conductive gel. The first structure is bonded to the second structure at an interconnect region, the first conductive trace is electrically coupled to the second conductive trace within the interconnect region, and the first electronic component is operatively coupled to the second electronic component.Type: GrantFiled: August 31, 2021Date of Patent: September 17, 2024Assignee: Liquid Wire Inc.Inventors: Mark William Ronay, Trevor Antonio Rivera, Michael Adventure Hopkins, Katherine M. Nelson, Charles J. Kinzel
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Patent number: 12080656Abstract: A semiconductor device includes an inductance structure and a shielding structure. The shielding structure is arranged to at least partially shield the inductance structure from external electromagnetic fields. The shielding structure includes a shielding structure portion arranged along a side of the inductance structure such that the shielding structure portion is around at least a portion of a perimeter of the inductance structure.Type: GrantFiled: February 24, 2023Date of Patent: September 3, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jen-Yuan Chang
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Patent number: 12069796Abstract: The storage device unit includes: a substrate having a main surface and having a plurality of wiring layers stacked together; and a storage device that has a plate shape having a first surface and is disposed on the substrate, the first surface facing the main surface. The plurality of wiring layers includes a heat-generating layer having a heat-generating circuit.Type: GrantFiled: December 28, 2021Date of Patent: August 20, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shigehito Morita, Mitsuhiro Iizuka, Junichi Ito, Keiichi Omyo, Toshiya Senoh, Masato Yanai, Naoto Nishiura