Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
  • Patent number: 10383215
    Abstract: (1) A conductor layer is disposed on at least one surface of a dielectric layer, the dielectric layer including an intermediate layer and a pair or more of fluororesin layers disposed on both surfaces of the intermediate layer, in which the ratio of the total average thickness of the intermediate layer to the total average thickness of the fluororesin layers is 0.001 to 30, the relative dielectric constant of the intermediate layer is 1.2 to 10, the coefficient of linear expansion of the intermediate layer is ?1×10?4/° C. to 5×10?5/° C., and the adhesive strength between the fluororesin layer and the conductor layer is 300 g/cm or more.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: August 13, 2019
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Masahiko Kouchi, Kazuo Murata, Makoto Nakabayashi
  • Patent number: 10375849
    Abstract: The present invention concerns a backplane electronic board (20) having on inner face (142) suitable for being connected to electronic board connectors (12) and an outer face (143) suitable for being connected to an outer connector (15), the backplane board (20) being characterized in that it has blind holes opening on the inner face (142) of same, and holes opening on the outer face (143) of same, the holes being suitable for receiving press-fit connection elements and forming therewith an electrical connection point.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 6, 2019
    Assignee: SAFRAN ELECTRONICS & DEFENSE
    Inventors: Francois Guillot, Pascal Spoor, Patrice Chetanneau
  • Patent number: 10375820
    Abstract: A computer system receives an initial multilayered ceramic package design. The computer system maintains a first selection of mesh line segments of the mesh line segments at a first width and adjusts a second selection of mesh line segments of the plurality of mesh line segments to a second width. The computer system controls fabrication of the multilayered ceramic package based on the modified multilayered ceramic package design.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jinwoo Choi, Sungjun Chun, Jason L. Frankel, Paul R. Walling, Roger D. Weekly
  • Patent number: 10366949
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 30, 2019
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Jun Furuichi, Akio Rokugawa, Takashi Ito
  • Patent number: 10361135
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baek Ki, Tark-Hyun Ko, Kun-Dae Yeom, Yong-Kwan Lee, Keun-Ho Jang
  • Patent number: 10352536
    Abstract: According to the present disclosure, a support structure for lighting devices, e.g. LED lighting devices, is provided with an electrically insulating core layer having a first and a second mutually opposed surfaces, with mounting locations for electrically-powered light radiation sources on the first surface, a network of electrically conductive lines printed on said first surface, at least some of said electrically conductive lines extending between the mounting locations and fixed locations on the first surface, and electrical distribution lines of electrically conductive material on the second surface of the core layer, and electrically conductive vias extending through core layer and electrically coupling the electrical distribution lines on the second surface with the electrically conductive lines at said fixed locations on the first surface.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 16, 2019
    Assignee: OSRAM GMBH
    Inventors: Lorenzo Baldo, Federico Poggi, Luigi Pezzato, Aleksandar Nastov
  • Patent number: 10338760
    Abstract: A touch sensor unit includes a substrate and a plurality of touch electrodes disposed on the substrate for generating sensing signals. Each of the touch electrodes includes an electrically insulating layer that is light-transmissible, and a plurality of nano-scale conducting elements distributed in the electrically insulating layer and electrically connected to one another. Each of the conducting elements includes a metal body that has a roughened surface, that has a twisted structure, or that is formed with a light light-absorbing member thereon.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 2, 2019
    Assignee: TPK Universal Solutions Limited
    Inventors: Kuo-Feng Kao, Sheng-Wen Lin, Po-Yi Wu, Shiang-Ting Wu
  • Patent number: 10340326
    Abstract: A flexible display apparatus is provided, including a flexible substrate including a bending area, an insulating layer formed on the flexible substrate and including at least one cutout at the bending area, and a plurality of wires configured following a surface shape of the insulating layer at the bending area. The at least one cutout includes sloped sidewalls protruding away from the flexible substrate.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 2, 2019
    Assignee: Shanghai Tianma Micro-Electronics Co., Ltd.
    Inventors: Shipeng Yuan, Wenxin Jiang, Gang Liu
  • Patent number: 10327341
    Abstract: A display device includes an array substrate and a counter substrate. On the array substrate, a TFT, a pixel electrode, an antenna coil, at least two external connection terminals, and a capacitor are provided. Two ends of the antenna coil are respectively connected to the at least two external connection terminals. The TFT includes a switching TFT. A set of the switching TFT and the capacitor or a plurality of sets of the switching TFT and the capacitor is provided. To the antenna coil, the set of the switching TFT and the capacitor or the plurality of sets of the switching TFT and the capacitor is connected.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 18, 2019
    Assignee: Japan Display Inc.
    Inventors: Daichi Suzuki, Yuji Suzuki
  • Patent number: 10327327
    Abstract: In a suspension board, a first insulating layer is formed on a support substrate. A ground layer and a power wiring trace are formed on the first insulating layer. The ground layer has electric conductivity higher than that of the support substrate. A second insulating layer is formed on the first insulating layer to cover the ground layer and the power wiring trace. A write wiring trace is formed on the second insulating layer to overlap with the ground layer. In a stacking direction of the support substrate, the first insulating layer and the second insulating layer, a distance between the ground layer and the write wiring trace is larger than a distance between the power wiring trace and the write wiring trace.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 18, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Daisuke Yamauchi, Hiroyuki Tanabe
  • Patent number: 10321561
    Abstract: A flexible printed circuit board (PCB), a method for manufacturing the flexible PCB, and a PCB structure having the flexible PCB are disclosed. A flexible printed circuit board includes a first conductive pattern layer, a second conductive pattern layer, a plurality of first conductive pillars, and a plurality of second conductive pillars. Each of the plurality of first conductive pillars electrically connects to the first conductive pattern layer and is spaced from the second conductive pattern layer, and a plurality of second conductive pillars electrically connects to the second conductive pattern layer and is spaced from the first conductive pattern layer. The plurality of first conductive pillars and the plurality of second conductive pillars are exposed from one surface of the flexible printed circuit board to form a plurality of electrical contact pads.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: June 11, 2019
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Xian-Qin Hu, Ming-Jaan Ho
  • Patent number: 10321562
    Abstract: A flexible circuit board and an electronic device including a flexible circuit board are provided. The flexible circuit board may include a substrate having a bending area and a non-bending area, a wiring pattern layer provided on the bending area and the non-bending area, a plating layer provided on the wiring pattern layer and including an open area in an area corresponding to the bending area, and a protective layer that directly contacts one surface of the wiring pattern layer exposed at the open area and a side surface of the plating layer. The protective layer may have a larger thickness than a thickness of the plating layer.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 11, 2019
    Assignee: LG INNOTEK CO., LTD
    Inventors: Jun Young Lim, Woong Sik Kim, Hyung Kyu Yoon, Min Hwan Kim
  • Patent number: 10308197
    Abstract: An electric distribution box includes a substrate, a first connector fitting part which includes first terminals, wherein one end portions of the first terminals are electrically connected to the substrate and the other end portions of the first terminals are disposed above the substrate so as to fit with the first connectors in a fitting direction parallel to the substrate, a second connector fitting part which includes a second terminal, wherein one end portion of the second terminal is electrically connected to the substrate and the other end portion of the second terminal is disposed above the substrate so as to fit with the second connector in a direction opposite to the fitting direction, electronic components on the substrate, a case body, and a cover which closes an opening part of the case body.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 4, 2019
    Assignee: YAZAKI CORPORATION
    Inventor: Koji Ikegaya
  • Patent number: 10312711
    Abstract: An electronic device includes a device controller and a microprocessor. The device controller is coupled to a device for controlling the device. The microprocessor is coupled to the device controller. The microprocessor obtains information regarding an amount of power consumption of the electronic device and dynamically determines an amount of current provided to the device according to the amount of power consumption. When the microprocessor determines that the amount of power consumption is greater than a threshold, the microprocessor determines to decrease the amount of current provided to the device.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: June 4, 2019
    Assignee: QUANTA COMPUTER INC.
    Inventor: Chun-Jie Yu
  • Patent number: 10303316
    Abstract: [Object] To provide a method for manufacturing a touch sensor capable of concurrently forming routed circuit patterns on both surfaces of a base film and capable of aligning the routed circuit patterns on the top and bottom surfaces with each other with high accuracy. [Solution] A method for manufacturing a touch sensor includes forming electrode patterns on both surfaces of a base film through concurrent light exposure on both surfaces and development using photosensitive electrically conductive films each including a support film, an electrically conductive layer disposed on the support film and containing an electrically conductive fiber, and a second photosensitive resin layer disposed on the electrically conductive layer. Routed circuit patterns obtained by patterning the light-shielding metal layers are formed in advance on both surfaces of the base film.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: May 28, 2019
    Assignee: NISSHA CO., LTD.
    Inventors: Ryomei Omote, Takao Hashimoto, Takeshi Nishimura
  • Patent number: 10306817
    Abstract: Disclosed are exemplary embodiments of thermal management and/or EMI (electromagnetic interference) mitigation materials with modified or custom colored exterior surfaces. The thermal management and/or EMI mitigation materials disclosed herein may comprise thermal interface materials (e.g., thermally-conductive pads or gap fillers, thermally-conductive dielectric materials, etc.), EMI shielding materials (e.g., EMI suppression materials, electrically-conductive thermal insulators, EMI absorbers etc.), microwave absorbers (e.g., microwave absorbing elastomers, microwave absorbing foams, EMI/RF/microwave absorbers, etc.), combinations thereof, etc. The thermal management and/or EMI mitigation materials disclosed herein may comprise combined thermal management and EMI mitigation materials, such as hybrid thermal/EMI absorbers, thermally-conductive microwave absorbers, hybrid absorber/thermal management materials usable for EMI mitigation, combined thermal interface and EMI shielding materials (e.g.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 28, 2019
    Assignee: Laird Technologies, Inc.
    Inventors: Karen J. Bruzda, Troy Dewayne Derksen, David B. Wood
  • Patent number: 10306753
    Abstract: Tamper-respondent assemblies and fabrication methods are provided which incorporate enclosure-to-circuit board protection. The tamper-respondent assemblies include a circuit board, and an enclosure mounted to the circuit board along an enclosure-to-board interface. The enclosure facilitates enclosing at least one electronic component coupled to the circuit board within a secure volume. A tamper-respondent electronic circuit structure facilitates defining the secure volume, and includes one or more tamper-detect circuits including at least one conductive trace disposed, at least in part, within the enclosure-to-board interface. The conductive trace(s) includes stress rise regions to facilitate tamper-detection at the enclosure-to-board interface. An adhesive is provided to secure the enclosure to the circuit board. The adhesive contacts, at least in part, the conductive trace(s) of the tamper-detect circuit(s) at the enclosure-to-board interface, including at the stress rise regions of the conductive trace(s).
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kathleen Ann Fadden, James A. Busby, David C. Long, John R. Dangler, Alexandra Echegaray, Michael J. Fisher, William Santiago-Fernandez
  • Patent number: 10304622
    Abstract: An electronic component includes: a body containing a ceramic material; and an indication part formed on a surface of the body and including a base region and a marking region formed of a non-conductive paste on a portion of the base region.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Sung Sik Shin
  • Patent number: 10290586
    Abstract: A package substrate with embedded noise shielding walls is disclosed. One of the embodiment comprises a signal line S sandwiched by a left shielding wall W1 and a right shielding wall W2. The signal line S, left shielding wall W1, and the right shielding wall W2 are embedded in a dielectric layer.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: May 14, 2019
    Inventor: Dyi-Chung Hu
  • Patent number: 10290611
    Abstract: In an embodiment, a package includes a first package structure including a first die having a first active side and a first back-side, the first active side including a first bond pad and a first insulating layer a second die bonded to the first die, the second die having a second active side and a second back-side, the second active side including a second bond pad and a second insulating layer, the second active side of the second die facing the first active side of the first die, the second insulating layer being bonded to the first insulating layer through dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bond pads.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hang Tung, Kuo-Chung Yee
  • Patent number: 10272598
    Abstract: Anisotropic conductive film produced that a light-transmitting transfer die having openings with conductive particles disposed therein is prepared, and photopolymerizable insulating resin squeezed into openings to transfer conductive particles onto the surface of the photopolymerizable insulating resin layer, first connection layer is formed which has a structure in which conductive particles are arranged in a single layer in a plane direction of photopolymerizable insulating resin layer and the thickness of photopolymerizable insulating resin layer in central regions between adjacent ones of the conductive particles is smaller than thickness of photopolymerizable insulating resin layer in regions in proximity to conductive particles; first connection layer is irradiated with ultraviolet rays through light-transmitting transfer die; release film is removed from first connection layer; second connection layer is formed on the surface of first connection layer opposite to light-transmitting transfer die; and th
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: April 30, 2019
    Assignee: DEXERIALS CORPORATION
    Inventors: Seiichiro Shinohara, Yasushi Akutsu
  • Patent number: 10254557
    Abstract: A flexible touch screen panel includes a thin film substrate including a first section and a second section and first sensing electrodes disposed in the first section and the second section, the first sensing electrodes being connected to one another along a first direction. The first sensing electrodes include a first stack structure in the first section and a second stack structure in the second section, the second stack structure being different from the first stack structure.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 9, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jun Namkung
  • Patent number: 10253549
    Abstract: An insulated glazing unit can include a spacer frame disposed between a first substrate from a second substrate and forming a portion of a sealed boundary and a flexible circuit extending through the sealed boundary. In an embodiment, the flexible circuit includes a flexible ribbon having a total length, LA, and an effective length, LE, and wherein LE is less than LA. In another embodiment, the flexible circuit includes an expandable portion adapted to expand a length of the flexible circuit to accommodate: relative movement between two or more portions of the insulated glazing unit, resizing of one or more portions of the insulated glazing unit, or any combination thereof.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: April 9, 2019
    Assignee: SAGE ELECTROCHROMICS, INC.
    Inventors: Rino Messere, Christian Müller, Robert J. Anglemier, Bryan D. Greer, Clifford Lee Taylor
  • Patent number: 10249587
    Abstract: A semiconductor device is disclosed including semiconductor die formed with functionally redundant main and optional die bond pads. In examples, the optional die bond pad is configured to be optionally redundant to the main die bond pad by forming the optional die bond pad with first and second electrically isolated portions, and electrically interconnecting the main die bond pad with the first portion of the second die bond pad. The second die bond pad may or may not be made redundant to the first die bond pad depending on whether an electrically conductive material is deposited on the first and second portions of the optional die bond pad.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 2, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Han-Shiao Chen, Chih-Chin Liao
  • Patent number: 10234969
    Abstract: A method of fabricating a composite conductive film is provided. The method includes providing, as a matrix, a layer of cross-linkable polymer, where the cross-linkable polymer is in a non-cross-linked state. The method further includes introducing inorganic nanowires upon a surface of the layer of cross-linkable polymer. The inorganic nanowires are, in isolated form, characterized by a first conductivity stability temperature. The method further includes embedding at least some of the inorganic nanowires into the layer of cross-linkable polymer to form an inorganic mesh, thereby forming the composite conductive film. The method further includes cross-linking the polymer within a surface portion of the composite conductive film. Cross-linking the polymer within the surface portion of the composite conductive film results in the surface portion having a second conductivity stability temperature that is greater than the first conductivity stability temperature.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: March 19, 2019
    Assignee: Sinovia Technologies
    Inventors: Whitney Gaynor, George Burkhard
  • Patent number: 10231370
    Abstract: An electronic component mounting device, including: a board conveyance device which conveys and positions a board on which an electronic component is mounted; a mounting device which positions and mounts the electronic component to a mounting position of the board; a loading device which picks up multiple engaged members (clips), and positions and loads the engaged members to a loading position of the board; and a placing device which picks up a cover component that covers the mounted electronic component and that is provided with an engaging portion at a predetermined position, and positions and places the cover component to a position such that the engaging portion corresponds to the engaged member.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: March 12, 2019
    Assignee: FUJI CORPORATION
    Inventors: Tetsuo Hayashi, Kuniyasu Nakane, Chikashi Teshima
  • Patent number: 10224270
    Abstract: An electronic component package includes a substrate having an upper surface. Traces on the upper surface of the substrate extend in a longitudinal direction. The traces have a first latitudinal width in a latitudinal direction, the latitudinal direction being perpendicular to the longitudinal direction. Rectangular copper pillars are attached to bond pads of an electronic component, the copper pillars having a longitudinal length and a latitudinal second width. The latitudinal second width of the copper pillars is equal to and aligned with the first latitudinal width of the traces. Further, the longitudinal length of the copper pillars is parallel with the longitudinal direction of the trace and equal to the length of the bond pads. The copper pillars are mounted to the traces with solder joints.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: March 5, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Robert Francis Darveaux, David McCann, John McCormick, Louis W. Nicholls
  • Patent number: 10217810
    Abstract: The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 26, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Randy Yach, Francesco Mazzilli
  • Patent number: 10212808
    Abstract: Disclosed is a printed circuit hoard. The printed circuit board includes a plurality of insulation layers and a plurality of pattern layers alternately stacked. The printed circuit board includes a plurality of device areas on which semiconductor packages are mounted and a peripheral area adjacent the device areas. An electrostatic discharge pattern is in a respective pattern layer among the plurality of pattern layers and is disposed at a boundary region between a respective device area of the plurality of device areas and the peripheral area.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Iksung Park, Heeyoub Kang, Young-Min Kim, Eunji You, Hwi-jong Yoo
  • Patent number: 10211120
    Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Russell S. Aoki, Jonathan W. Thibado, Jeffory L. Smalley, David J. Llapitan, Thomas A. Boyd, Harvey R. Kofstad, Dimitrios Ziakas, Hongfei Yan
  • Patent number: 10206279
    Abstract: A substrate includes a ceramic layer, a metal layer fixed in a planar manner on a surface side of the ceramic layer and a cutout arranged in an edge region of the metal layer. The cutout in the edge region codes information. A multiple substrate having a plurality of these substrates is also provided, as is a method for producing the substrate.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies AG
    Inventor: Alexander Roth
  • Patent number: 10203791
    Abstract: The present application discloses a display substrate having a first area for bonding a driver integrated circuit. The display substrate includes a base substrate; an overcoat layer on the base substrate in a second area of the display substrate; the overcoat layer having an interface portion in an area abutting the first area, the interface portion having a plurality of teeth and a plurality of slits, two adjacent teeth being spaced apart by a slit; and a conductive line layer on a side of the overcoat layer proximal to the base substrate, having a plurality of conductive lines extending from the second area to the first area; each of the plurality of conductive lines electrically connected to a signal line in the second area.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jun Li, Jiayao Shi, Zhao Dong, Tsungchieh Kuo
  • Patent number: 10199346
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • Patent number: 10198139
    Abstract: A touch sensor member includes a substrate sectioned into a display region and a design region; a conductive pattern formed on the display region and having a line width of 2 to 6 ?m; and a conductive pattern formed on the design region and having a line width of 7 to 100 ?m, wherein the conductive pattern having a line width of 2 to 6 ?m and the conductive pattern having a line width of 7 to 100 ?m have the same composition.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: February 5, 2019
    Assignee: Toray Industries, Inc.
    Inventors: Miharu Tanabe, Akihiko Tanaka
  • Patent number: 10188000
    Abstract: An insulating board includes a first portion that is relatively thick and a second portion that is relatively thin. The first and second portions have different thicknesses so that a step is provided therebetween. The insulating board includes a first land conductor on a first mounting surface of the first portion at a side at which the step is provided, a second land conductor on a second mounting surface of the second portion at the side at which the step is provided, and an insulating protection film on the first mounting surface so that a portion of the first land conductor is exposed and another portion of the first land conductor is covered. An electronic component is soldered to the first land conductor. Another electronic component is joined to the second land conductor by an anisotropic conductive film that covers the second land conductor.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 22, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kuniaki Yosui
  • Patent number: 10185694
    Abstract: We describe a method of manufacturing a plurality of electronic devices. The method comprises manufacturing a multi-device motherboard bearing programmable device circuit boards, each of these with an electronic device comprising a processor and programmable memory and being detachable from the motherboard except for one of more frangible links, at least one of these links comprising a programming connection. A device programming region bears a motherboard processor and program memory for programming the device circuit boards. Code for at least one application program for said electronic device is stored in said motherboard program memory. A user interface for the multi-device motherboard allows a user to configure each of the electronic devices to perform a defined function.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: January 22, 2019
    Inventor: Heba Bevan
  • Patent number: 10181662
    Abstract: A cable connection method is provided. In a cable connection structure, a connection agent in which fine solder particle are densely scattered in a thermosetting resin-based adhesive is interposed between a connection portion of a flexible printed cable (FPC) cable in which a shield layer is formed on one surface side of a signal layer and a connection portion on a substrate side. Then, the connection portion of the FPC cable and the connection portion on the substrate side are solder connected by heating. A shield layer corresponding to the connection portion of the FPC cable and/or a region portion up to a position separated from the base end side of the connection portion of the FPC cable by a predetermined length is configured with a conductive mesh structure body. The other region of the shield layer contains a conductive flat plate structure.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: January 15, 2019
    Assignee: LENOVO (SINGAPORE) PTE LTD
    Inventors: Hirohide Komiyama, Yoshio Nakamura, Seiji Yamasaki, Osamu Yamamoto, Takaaki Okada
  • Patent number: 10178760
    Abstract: A flexible cable may include: a flexible substrate having a first surface and a second surface that are on opposite sides of the flexible substrate; a first conductive line formed on the first surface of the flexible substrate, and structured to transmit a signal having a first frequency; a second conductive line formed on the first surface of the flexible substrate, and structured to transmit a signal having a second frequency lower than the first frequency; and a ground line formed on the second surface of the flexible substrate, and comprising a first region overlapping the first conductive line and a second region overlapping the second conductive line. The first and second regions may have different shapes.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung-Ryong Lee, Sung-Jin Lee
  • Patent number: 10177012
    Abstract: A wiring substrate includes a first insulation layer having a component mounting area and a mark formation area, an electrode pad arranged in the component mounting area and having an upper surface exposed from the first insulation layer and a side surface and a lower surface embedded in the first insulation layer, and a mark arranged in the mark formation area and formed of an insulation pattern layer having an upper surface exposed from the first insulation layer and a side surface and a lower surface embedded in the first insulation layer. A color of the first insulation layer and a color of the insulation pattern layer are different.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: January 8, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kotaro Kodani
  • Patent number: 10169624
    Abstract: Tamper-proof electronic packages and fabrication methods are provided including an enclosure enclosing, at least in part, at least one electronic component within a secure volume, a two-phase dielectric fluid within the secure volume, and a tamper-respondent detector. The tamper-respondent detector monitors, at least in part, temperature and pressure of the two-phase dielectric fluid. In operation, the two-phase dielectric fluid deviates from an established saturation line of the two-phase dielectric fluid within the secure volume with an intrusion event into the secure volume, and the tamper-respondent detector detects, from the monitoring of the temperature and pressure of the two-phase dielectric fluid, the deviation from the established saturation line, and thereby occurrence of the intrusion event.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Levi A. Campbell, Milnes P. David, Dustin W. Demetriou, Michael J. Ellsworth, Jr.
  • Patent number: 10165680
    Abstract: The present invention provides a light-transmitting conductor comprising: a substrate; and a conduction layer on the substrate, wherein the conduction layer comprises a conductive material, and the conduction layer has a pattern corresponding to a network formed such that nanostructures are arranged to intersect with each other that includes a substrate and a conduction layer on the substrate.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: December 25, 2018
    Assignee: INTREE CO., LTD
    Inventor: Kyung Ho Jung
  • Patent number: 10163839
    Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 10154589
    Abstract: The objective of the present invention is to improve reliability in a solder connection portion between an electronic component and a wiring pattern. A pair of wiring patterns (31A and 31B) are formed on a circuit wiring board (30) with an insulation layer (37) therebetween. Each wiring pattern (31A and 31B) has a land (33a or 33b) and a wiring portion (34a or 34b) that is narrower than the land. By way of solder (42), a chip component (41) is soldered to the lands (33a and 33b). The x (width) direction center (Xa) of each connection portion (53) where a respective wiring portion (34a or 34b) is connected to a respective land (33a or 33b) is disposed at a position that is outside of both the region in which a region of predetermined width (Wc) of the chip component (41) extends in the x (longitudinal) direction, and the region in which a region of predetermined length (Lc) of the chip component (41) extends in a y (transverse) direction.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: December 11, 2018
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Miki Hiraoka, Shiro Yamashita, Tomishige Yatsugi
  • Patent number: 10134652
    Abstract: The present invention relates to a substrate for an integrated circuit package and, more specifically, to a substrate for an integrated circuit package, which reduces mismatch of coefficients of thermal expansion with a semiconductor chip, thereby preventing or minimizing warpage during a reflow process.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 20, 2018
    Assignee: Corning Precision Materials Co., Ltd.
    Inventors: Joon Soo Kim, Hyung Soo Moon, Jae Young Choi
  • Patent number: 10136514
    Abstract: An extensible flexible printed circuit board sets one or a plurality of flexible printed circuit boards each including a plurality of conductive layers and an insulating layer as a base circuit board, and includes: component mounting parts which are provided at least at parts of the base circuit board, and capable of mounting electronic components; an extensible conductive part which is provided at least at a part of the base circuit board, includes a plurality of joint parts each intersecting a center line in an extension/contraction direction and a plurality of curved parts each continuing from an end part of each joint part and curve, and exhibits extensibility by the curved parts curving to open or close; and a covering member whose material is a flexibly deformable elastomer, and which covers the component mounting parts and the extensible conductive part.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: November 20, 2018
    Assignee: NIPPON MEKTRON, LTD.
    Inventors: Akio Yoshida, Kiyoshi Igarashi, Shingo Muromoto, Taisuke Kimura, Nobuyuki Shintaku
  • Patent number: 10117329
    Abstract: A carrier plate includes a substrate and at least one conductor track. The conductor track includes a first layer, which is applied directly on the substrate, and a second layer, which is arranged on the first layer. The second layer includes a supply line region and a soldering region. Furthermore, the second layer is completely interrupted between the supply line region and the soldering region. A device can be produced with a carrier plate and an electrical component arranged on the carrier plate.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Sebastian Brunner, Stefan Leopold Hatzl
  • Patent number: 10096565
    Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: October 9, 2018
    Inventor: Ping-Jung Yang
  • Patent number: 10090596
    Abstract: Various methods related to antennas and embodiments of antennas are presented. The antenna may include an upper arm, wherein the upper arm is substantially parallel to a ground plane and is electrically coupled with at least a ground shorting structure, a support structure, and a feed structure. The antenna may include the ground shorting structure, which may be at a first end of the upper arm. The antenna may include the support structure, which may be at a second end of the length of the upper arm and may support the upper arm. The antenna may also include the feed structure, which is configured to provide a signal for wireless transmission, the feed structure may be attached to a side of the length of the upper arm.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: October 2, 2018
    Assignee: Google LLC
    Inventors: Eric Daniels, Daniel Adam Warren, Hirofumi Honjo
  • Patent number: 10080279
    Abstract: A wired circuit board, including a metal supporting layer; an insulating layer formed on one side of the metal supporting layer in a thickness direction thereof; and a conductive layer having a plurality of terminal portions placed to be spaced apart from each other and formed on one side of the insulating layer in the thickness direction. The insulating layer has a first opening which is formed to include the plurality of terminal portions, and the metal supporting layer includes a second opening formed to include the plurality of terminal portions, when projected in the thickness direction. The wired circuit board further includes at least one reinforcing insulating portion which is placed between the plurality of terminal portions in the first opening, and/or at least one reinforcing metal supporting portion which is placed between the plurality of terminal portions in the second opening, when projected in the thickness direction.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: September 18, 2018
    Assignee: NITTO DENKO CORPORATION
    Inventors: Tomoaki Okuno, Saori Kanezaki, Tsuyoshi Oguro, Takeshi Kawakami
  • Patent number: 10068958
    Abstract: In various embodiments, an organic light-emitting organic is provided. The organic light-emitting component may include a first electrode layer, an organic functional layer structure over the first electrode layer, and a second electrode layer over the organic functional layer structure. The second electrode layer and the organic functional layer structure are divided into subregions which are arranged laterally next to one another, which are respectively at least partially separated from one another. A plurality of the subregions are electrically connected to at least two neighboring subregions by at least two corresponding connecting elements with are formed by the second electrode layer and the organic functional layer structure.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: September 4, 2018
    Assignee: OSRAM OLED GMBH
    Inventors: Kilian Regau, Karsten Diekmann, Egbert Hoefling