Preformed Panel Circuit Arrangement (e.g., Printed Circuit) Patents (Class 174/250)
  • Patent number: 10705002
    Abstract: A sensor for detecting electrically conductive and/or polarizable particles, in particular for detecting soot particles, includes a substrate, a first electrode layer, and a second electrode layer, which is arranged between the substrate and the first electrode layer. An insulation layer is formed betweem the first electrode layer and the second electrode layer and at least one opening is formed in the first electrode layer and in the insulation layer, wherein the opening of the first electrode layer and the opening of the insulation layer are arranged one over the other at least in some segments in such a way that at least one passage to the second electrode layer is formed.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 7, 2020
    Assignee: HERAEUS NEXENSOS GMBH
    Inventors: Tim Asmus, Karlheinz Wienand, Stefan Dietmann
  • Patent number: 10701799
    Abstract: According to an example, a device may comprise a printed circuit board. The printed circuit board may further comprise a first layer and a second layer. The first layer may comprise a first material and the second layer may comprise a second material. In some examples, the first layer may further comprise at least one mounting hole surrounded by a third material at a thickness equal to a thickness of the first layer, and the first material may be electrically isolated from the third material. In some examples, the printed circuit board may be mated to a light guide assembly for a touchscreen system.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 30, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stewart R. Wyatt, Don E. Saunders, Scott David Hahn, Cameron L. Hutchings
  • Patent number: 10689248
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 23, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming Yen Lee, Chia Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
  • Patent number: 10681819
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Patent number: 10679892
    Abstract: A method is presented for reducing a resistance-capacitance product and RIE lag in a semiconductor device. The method includes depositing a first ultra-low-k (ULK) material over a dielectric cap, the first ULK material defining a recess, filling the recess with a second ULK material, the second ULK material being different than the first ULK material, where the first and second ULK materials are formed in a common metal level of a back-end-of-the-line (BEOL) structure, forming first trenches within the first ULK material and second trenches within the second ULK material, and filling the first and second trenches with a conductive material.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Chih-Chao Yang, Hosadurga Shobha
  • Patent number: 10672718
    Abstract: Disclosed herein are, for instance, methods for producing through package vias in a glass interposer. For instance, disclosed herein is a method for producing through package vias in a glass interposer comprising laminating a polymer on at least a portion of a top surface of a glass interposer, removing at least a portion of the polymer and the glass interposer to form a through via, filling at least a portion of the through via with a metal conductor to form a metallization layer, and selectively removing a portion of the metallization layer to form a metalized through package via. Other methods are also disclosed, along with through-package-via structures in glass interposers produced therefrom.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: June 2, 2020
    Assignee: Georgia Tech Research Corporation
    Inventors: Venkatesh Sundaram, Fuhan Liu, Rao R. Tummala, Vijay Sukumaran, Vivek Sridharan, Qiao Chen
  • Patent number: 10663662
    Abstract: A hybrid spiral waveguide geometry is proposed that exhibits essentially zero curvature (i.e., infinite bend radius) at the center of the spiral (similar to a Fermat spiral), with the curvature then increasing in value as the spiral moves outward. Advantageously, as the spiral moves away from the center, the spacing between adjacent waveguides quickly approaches a constant value (similar to an Archimedean spiral). This hybrid spiral structure has been found to allow for a high density waveguide to be created with lower loss and requiring a smaller size than many conventional spiral configurations and finds use in optical delay lines, amplifiers and arrayed waveguide gratings.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 26, 2020
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Michael Gehl, Christopher DeRose
  • Patent number: 10661300
    Abstract: A method for painting a work piece of plastic material. The method includes applying a first coating of an electrically conductive material to the work piece and electrically grounding the first coating. The method also includes electrostatically charging a paint to render the paint conductive for statically attracting the conductive paint toward the grounded first coating of the work piece. The method also includes overlying a mask of a non-conductive material over at least a portion of the first coating of the work piece and electrically insulating the mask. The work piece is then sprayed with the conductive paint to apply a layer of paint on the first coating with the mask preventing the conductive paint from being applied on the portions of the first coating of the work piece that are covered by the mask.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: May 26, 2020
    Assignee: Lacks Enterprises, Inc.
    Inventors: Lee Chase, Scott Stuart
  • Patent number: 10660200
    Abstract: The invention provides an electronic device that includes a first functional body, a second functional body, and at least one connection member connecting the first functional body to the second functional body. The at least one connection member has a spiral pattern, and is suspended in air to allow for stretching, flexing or compressing.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: May 19, 2020
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Hanqing Jiang, Cheng Lv, Hongyu Yu
  • Patent number: 10658329
    Abstract: A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and an electronic component. A curing degree curve is created. The curing degree curve indicates, with respect to each of heating temperatures, relationship between heating time and curing degree of the thermosetting resin. On the basis of the created curing degree curve, a void removal time of a void naturally moving upward in the thermosetting resin, at a first heating temperature, is calculated. The first heating temperature is one of the heating temperatures.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 19, 2020
    Assignee: SONY CORPORATION
    Inventor: Takeshi Ichimura
  • Patent number: 10660219
    Abstract: A resin multilayer substrate includes a stacked body including resin layers, a component, one or more first conductor patterns, and one or more second conductor patterns each disposed in a gap between the resin layers. At least a portion of an outline of each of the one or more first conductor patterns overlaps with the component. An outline of each of the one or more second conductor patterns does not overlap with the component. A resin portion is adjacent to each of the one or more first conductor patterns along a portion of the outline of each of the one or more first conductor patterns that overlaps with the component. The resin portion is made of a resin paste including thermoplastic resin powder as a main material. The resin portion is not disposed in a portion along the outline of each of the one or more second conductor patterns.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: May 19, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Asato Fujimoto
  • Patent number: 10660218
    Abstract: A multilayer circuit board comprises an inner circuit unit having at least one solder portion, and at least one outer circuit board coupled with the inner circuit unit. The inner circuit unit connects with the outer circuit board by an insulation colloid. At least one side of the inner circuit unit does not extend to edges of the multilayer circuit board. The at least one outer circuit board forms at least one through-hole and at least one conductive hole. The at least one conductive hole which is internally-plated with copper extends from the at least one outer circuit board to the inner circuit unit. A method of manufacturing the multilayer circuit board is also disclosed.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 19, 2020
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Xian-Qin Hu, Li-Kun Liu, Yan-Lu Li, Ming-Jaan Ho
  • Patent number: 10653006
    Abstract: Electrical conductors are disclosed. More particularly, undulating electrical conductors are disclosed. Certain disclosed electrical conductors may be suitable to be disposed on flexible or stretchable substrates.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: May 12, 2020
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Nicholas T. Gabriel, Ronald D. Jesme, Andrew J. Ouderkirk, Ravi Palaniswamy, Andrew P. Bonifas, Alejandro Aldrin A. Narag, II, Robert M. Jennings, Robin E. Gorrell
  • Patent number: 10643784
    Abstract: A filter inductor for high-current applications. The filter inductor includes a magnetic core and a winding. The winding includes a shaped section having opposing ends, a pair of arm sections laterally extending from the opposing ends of the shaped section, respectively, and a pair of inductor pins, each extending perpendicular from an end of a respective arm section. The magnetic core includes a first core portion and a second core portion. The first core portion includes a recessed channel configured to receive the shaped section of the winding. The second core portion includes a pair of recessed regions configured to receive the pair of arm sections of the winding, respectively. The first core portion and the second core portion are coupled in contact to one another to secure the shaped section of the winding within the magnetic core. The filter inductor can be edge-mounted to a printed circuit board.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: May 5, 2020
    Assignee: Bel Fuse (Macao Commercial Offshore) Limited
    Inventors: Jianbin Yao, Hai Huang
  • Patent number: 10632680
    Abstract: Embodiments include an apparatus, generated at least partially using a 3D printer, the apparatus including an object, the object being at least partially fabricated from a 3D printer, the object including a first part of the object, the first part of the object defining a first void and a second part of the object, the second part of the object defining a second void. The apparatus can include a pin, the pin having a first end and a second end, where the first end of the pin engages the first void of the object and the second end of the pin engages the second end of the pin such that the first part is coupled with the second part to form the object.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 28, 2020
    Assignee: GHOST CAPITAL, INC.
    Inventor: Brian Quincy Robinson
  • Patent number: 10638605
    Abstract: A circuit board design device judging whether a circuit board has a pair of via holes which are adjacent within a solder bridge formation distance within which a solder bridge can be formed; when the affirmative, the circuit board design device judging whether each of the pair of via holes is electrically connected in parallel to other via hole with a land not coated with solder resist; when the circuit board design device judges that at least one of the pair of via holes is electrically connected in parallel to the other via hole with a land not coated with solder resist, the circuit board design device determining the at least one of the pair of via holes which is electrically connected in parallel to the other via hole with a land not coated with solder resist as a coated via hole with a land coated with solder resist.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: April 28, 2020
    Assignee: DENSO TEN Limited
    Inventors: Tamaki Kawabata, Kenichi Osakabe
  • Patent number: 10638599
    Abstract: A printed circuit board includes a plurality of layers including conductive layers separated by dielectric layers, the conductive layers including a signal layer; and via patterns formed in the plurality of layers, each of the via patterns comprising first and second signal vias extending from a first surface of the printed circuit board to the signal layer, the signal layer including first and second signal traces connected to the first and second signal vias, respectively, the signal layer further including a ground conductor located between the signal traces and adjacent signal-carrying elements.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 28, 2020
    Assignee: Amphenol Corporation
    Inventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
  • Patent number: 10629850
    Abstract: A flexible OLED display panel is disclosed and includes an encapsulation structure. The encapsulation structure includes: a first inorganic thin film formed on a surface of an OLED display layer and a surrounding region of the surface; a first organic thin film formed on a surface of the first inorganic thin film; and a plurality of dams. Each of the dams has a first sub-dam close to the first inorganic thin film and a second sub-dam away from the first inorganic thin film. A gap is formed between the first sub-dam and the second sub-dam which are located at a same side. The gap is filled with desiccant.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 21, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Simin Peng, Hsiang lun Hsu, Jun Cao
  • Patent number: 10627099
    Abstract: A lighting assembly (100), a light source, a lamp and a luminaire are provided. The lighting assembly comprises a heat transferring element (102) and an elongated structure (120) comprising light emitting elements (122, 122?) and power connections. The heat transferring element comprises at a first side (104) a heat sink interface or a heat sink element. At the second opposite side (106) one or more upstanding walls (108, 108?) are provided extending away from the second side. The upstanding walls are heat conductive and thermally coupled to the first side. The elongated structure is arranged on a wall surface of at least one of the upstanding walls. The wall surface is adjacent to the second side. A surface of the elongated structure through which no light is emitted is thermally coupled to the wall surface. A pattern formed by the elongated structure is a meandering or spiral pattern.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 21, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Ties Van Bommel, Rifat Ata Mustafa Hikmet
  • Patent number: 10619248
    Abstract: The present invention provides a conductive laminate for a touch panel which includes a substrate, and a patterned metal layer which is visually recognized to have greater blackness when viewed from the substrate side; a touch panel; and a transparent conductive laminate. The conductive laminate includes a substrate which has two main surfaces; a patterned plated layer which is disposed on at least one main surface of the substrate and has a functional group that interacts with metal ions; and a patterned metal layer which is disposed on the patterned plated layer, in which the patterned plated layer includes a metal component constituting the patterned metal layer and the ratio of the average peak intensity resulting from the metal component contained in the patterned plated layer to the average peak intensity resulting from the metal component constituting the patterned metal layer is in a range of 0.5 to 0.95.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: April 14, 2020
    Assignee: FUJIFILM Corporation
    Inventor: Naoki Tsukamoto
  • Patent number: 10624208
    Abstract: A printed circuit board for a surface mount device (SMD) is provided. The printed circuit board includes adjacent, opposed first and second lands on a face of the printed circuit board, the first land comprising a first solder pad contacting or merged with a first annular pad of a first via, the second land comprising a second solder pad contacting or merged with a second annular pad of a second via, arranged for solder mounting a surface mount device to the first and second solder pads.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: April 14, 2020
    Assignee: Arista Networks, Inc.
    Inventor: Zev Gross
  • Patent number: 10624215
    Abstract: A method for manufacturing connection structure, the method includes arranging a first composite on a first surface of a first member where a first electrode is located and arranging conductive particles on the first electrode, arranging a second composite on a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: April 14, 2020
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 10616991
    Abstract: An interposer includes an insulating element body, a wiring electrode inside the element body, a signal terminal electrode at the top surface of the element body and connected to a flat cable with a conductive bonding material interposed therebetween, and a ground terminal electrode. A through-hole penetrates through the element body to allow a bar-shaped metal fixing member to be inserted. A metal fixing member connecting electrode to be electrically connected to a metal fixing member is provided at at least one of the top surface of the element body and an inner wall of the through-hole. Predetermined signal terminal electrodes are electrically connected by the wiring electrode. The ground terminal electrode and the metal fixing member connecting electrode are electrically connected.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 7, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirokazu Yazaki, Keito Yonemori
  • Patent number: 10617009
    Abstract: Methods, systems, and apparatus, including printed circuit boards (PCBs) with trace routing topologies are disclosed. In one aspect, a PCB includes an external layer that includes multiple integrated circuit (IC) installation regions that are each configured to receive an IC, a first trace routing layer having a first conductive trace that is routed along a first path from a first IC installation region to a second IC installation region, a second trace routing layer having a second conductive trace that is routed along a second path from the first IC installation region to the second IC installation region, a first via region having one or more first vias that extend from the first trace routing layer to the second trace routing layer, and a second via region having one or more second vias that extend from the first trace routing layer to the second trace routing layer.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 7, 2020
    Assignee: Google LLC
    Inventors: Andrew Gerard Noonan, Sara Zebian
  • Patent number: 10616990
    Abstract: Printed circuit board (PCB) apparatus comprising an apertured ground plane defining aperture pattern/s in the ground plane, each aperture pattern including apertures which, taken together, surround most but not all of SMT footprint/s and are interspersed with ground plane region/s which provide/s the SMT component with electrical connectivity to area/s of said ground plane other than said SMT footprint, thereby to maintain functionality of the SMT component including electrical connectivity between said SMT footprint and area/s of said ground plane other than said SMT footprint, while also slowing heat dissipation from the SMT footprint by restricting thermal conductivity between said area and said area's vicinity thereby to raise the temperature in the SMT footprint while a SMT component is being soldered thereto, thereby to at least partly prevent improper soldering of the SMT component which may cause the SMT component to subsequently detach from the board.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 7, 2020
    Assignee: ELTA SYSTEMS LTD.
    Inventor: Yaniv Boaron
  • Patent number: 10608018
    Abstract: A display device includes first, second and third connection wiring. The second connection wiring is located in a same layer as the first connection wiring. The third connection wiring is located in a layer different from the first connection wiring. The first connection wiring includes at least one first region running in a first direction and at least one second region running in a second direction different from the first direction. The second connection wiring includes at least one third region running in the first direction and at least one fourth region running in the second direction. The third connection wiring includes at least one fifth region running in the first direction and at least one sixth region running in the second direction. The at least one first region, the at least one third region, and the at least one fifth region are adjacent to one another.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: March 31, 2020
    Assignee: Japan Display Inc.
    Inventor: Jun Hanari
  • Patent number: 10606426
    Abstract: A touch panel electrode includes a transparent base, two or more first electrode patterns, and two or more second electrode patterns. The first electrode pattern and the second electrode pattern face each other being insulated, and overlap each other. Each of the first electrode pattern and the second electrode pattern is a combination of a plurality of cells formed by thin metal wires. The area of an overlapping portion between the first electrode pattern and the second electrode pattern is greater than 4 mm2 and less than 20 mm2.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 31, 2020
    Assignee: FUJIFILM Corporation
    Inventor: Hiroshige Nakamura
  • Patent number: 10602651
    Abstract: A system for tracking objects such as a printed circuit board (PCB) undergoing multiple manufacturing processes traceability system includes a coding unit, a scanning unit, and a reading unit and a database. The printed circuit board includes at least two inner copper foil substrates, subsequent substrates can be added. The coding unit marks identification and manufacturing stage codes on the inner copper foil substrate for through scanning by the scanning unit emitting X-rays. The reading unit can receive and parse the codes identified by the X-rays, and determine the previous or a next stage according to a predetermined encoding rule without risk of stage repetition or stage omission or product misplacement. The database stores standard identities and information as to manufacturing stages as a reference.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 24, 2020
    Assignees: Avary Holding (Shenzhen) Co., Limited., HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.
    Inventors: Fu-Sheng Luo, Pai-Hung Huang, Chien-Jui Lo, Yin-Zhen Zeng
  • Patent number: 10595396
    Abstract: In one or more embodiments, a circuit board may include a trace pair and a serpentine region of the trace pair, which may include: a first subregion in which the first trace includes a first portion that has a third width and a first length and in which the second trace includes a second portion, at least substantially parallel to the first portion, that has a fourth width, greater than the second width, and a second length; and a second subregion, adjacent to the first subregion, in which the first trace includes a third portion that has the third width and a third length and in which the second trace includes a third portion that has the fourth width and a third length, different from the second length.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 17, 2020
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Chun-Lin Liao
  • Patent number: 10595406
    Abstract: A module component includes a substrate; first, second, third and fourth main electrodes on or in a principal surface of the substrate; a sub-electrode located between two of the four main electrodes and connected to one of the four main electrodes by a solder; a first mount component mounted to the first and second main electrodes; and a second mount component mounted to the third and fourth main electrodes; wherein an area of the sub-electrode is smaller than an area of each of the first, second, third and fourth main electrodes.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 17, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroshi Nishikawa
  • Patent number: 10587023
    Abstract: An apparatus includes a plurality of conductive layers and a plurality of traces configured to carry a plurality of signals through a change of direction. The traces may be routed parallel to each other in a first trace segment in a first of the conductive layers toward the change of direction. The traces may be routed parallel to each other in a second trace segment in a second of the conductive layers in the change of direction. One of the traces in a third trace segment in the first conductive layer may cross over another of the traces in the second trace segment in the second conductive layer in the change of direction. The traces may be routed parallel to each other in the third trace segment in the first conductive layer away from the change of direction.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: March 10, 2020
    Assignee: Renesas Electronics America Inc.
    Inventors: Samet Zihir, Tumay Kanar, Naveen Krishna Yanduru
  • Patent number: 10562820
    Abstract: A low-temperature co-fired microwave dielectric ceramic material includes: (a) 85 wt % to 99 wt % ceramic material comprising Mg2SiO4, Ca2SiO4, CaTiO3, and CaZrO3, wherein a weight ratio of Mg2SiO4 relative to Ca2SiO4 is of (1?x):x, a weight ratio of CaTiO3 relative to CaZrO3 is of y:z, and a weight ratio of entities of Mg2SiO4 and Ca2SiO4 relative to CaTiO3 is of (1?y?z):y, 0.2?x?0.7, 0.05?y?0.2, 0.05?z?0.4; and (b) 1 wt % to 15 wt % glass material composed of Li2O, BaO, SrO, CaO, B2O3, and SiO2.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 18, 2020
    Assignee: WALSIN TECHNOLOGY CORPORATION
    Inventors: Li-Wen Chu, Kuei-Chih Feng, Chih-Hao Liang
  • Patent number: 10553966
    Abstract: The QSFP-DD module has an internal printed circuit board defining a mating port at a front edge region, and a connecting port at a rear edge region, and plural sets of wires mechanically and electrically connected to the connecting port with a plurality of ground staples discrete from one another to secure the respective sets of wires to the printed circuit board. The pitch among the ground staples is essentially 3.38 mm, and the wires are connected to two opposite surfaces of the printed circuit board with the associated ground staples. The staples are arranged in rows along the transverse direction.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 4, 2020
    Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Terrance F. Little, Patrick R. Casher
  • Patent number: 10555416
    Abstract: Disclosed in various examples of the present application is an electronic device comprising: first and second conductive patterns electrically connected to a communication circuit; a conductive material electrically connected between the first and second conductive patterns; a third conductive pattern spaced apart in a first direction from the first and/or second conductive patterns; and a fourth conductive pattern spaced apart in a second direction opposite to the first direction from the first and/or second conductive patterns, wherein each of the first and second conductive patterns comprises a first part of a first width and a second part of a second width wider than the first width, and the conductive material is arranged on at least a portion of the second part of the first conductive pattern and the second part of the second conductive pattern.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Wan Sang Ryu
  • Patent number: 10531805
    Abstract: Aspects are generally directed to systems and methods that integrate contactless electric field detectors to measure biophysical signals generated by a body. In one example, a biophysical sensing system includes a sensing assembly including an array of contactless electric field detectors, each of the contactless electric field detectors being configured to sense a corresponding component of an electric field generated by a body, a control system to receive sensor data indicative of the components of the electric field sensed by each of the contactless electric field detectors, the control system being configured to generate an estimate of the electric field based on the sensor data, and a feedback system coupled to at least the control system, the feedback system including at least one feedback interface, the feedback system being configured to operate the feedback interface to provide feedback based on the estimate of the electric field.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 14, 2020
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: James A. Bickford, Louis Kratchman, Daniel Freeman, Laura Jane Mariano
  • Patent number: 10527938
    Abstract: [Object] To provide a method for producing an electrical wiring member having a layered structure of copper wiring and a blackening layer and to provide the electrical wiring member through a search for a material for the blackening layer, the material being etched at a rate close to that for the copper wiring under conditions where etching controllability is ensured. [Solution] A method for producing an electrical wiring member according to the present invention includes a step of forming, on at least one main surface of a substrate, a layered film 6 of a Cu layer 3 and CuNO-based blackening layers (2a and 2b); a step of forming a resist layer 4a in a predetermined region on the layered film 6; and a step of removing a partial region of the layered film 6 by bringing the layered film 6 into contact with an etchant.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: January 7, 2020
    Assignee: NISSHA CO., LTD.
    Inventors: Hideaki Nada, Hiroaki Uefuji, Hirotaka Shigeno, Yoshihiro Sakata, Yuki Matsui, Hisaya Takayama
  • Patent number: 10524363
    Abstract: A method includes the following steps: S1, providing the insulating layer having an inclined face; S4, disposing a photomask so that in the photoresist, first and second exposure portions are exposed to light, and exposing the photoresist is to light through the photomask; S5, removing the first and the second exposure portions of the photoresist. On the assumption that in S4, light reflected at the metal thin film is focused between the first and the second exposure portions of the photoresist, the inclined face has a bending portion bending in one direction, the portion removed in S5 in the photoresist due to light focus being continuous with the first and the second exposure portions. The second exposure portion includes continuously an avoidance portion that avoids the bending portion and an overlapping portion that overlaps with at least a portion other than the bending portion in the inclined face.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: December 31, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Hiroyuki Tanabe, Yoshito Fujimura
  • Patent number: 10515917
    Abstract: The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chita Chuang, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 10499513
    Abstract: By flexographic printing or inkjet printing, insulating ink is applied on a wiring pattern in accordance with a predetermined printing pattern. The insulating ink is hardened, whereby an insulating layer is formed. A contact region of the wiring pattern that is used for electrical connection with a conductor other than the wiring pattern is not covered with the insulating layer. The printing pattern is delimited by the outline of a non-printing region including the contact region. The wiring pattern includes, in the non-printing region, a trunk wiring line leading, to the contact region, from a position on the wiring pattern at which the wiring pattern overlaps with the outline and a branch wiring line extending from a point on at least one side of the trunk wiring line and terminating without making contact with the outline.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 3, 2019
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Yutaro Kogawa, Mitsunori Sato, Yutaka Takezawa, Akitoshi Sakaue, Mitsutoshi Naito
  • Patent number: 10497663
    Abstract: A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: December 3, 2019
    Assignees: NIPPON MICROMETAL CORPORATION, NIPPON STEEL CHEMICAL & MATERIAL CO., LTD.
    Inventors: Takashi Yamada, Daizo Oda, Teruo Haibara, Tomohiro Uno
  • Patent number: 10492307
    Abstract: By flexographic printing or inkjet printing, insulating ink is applied on a wiring pattern in accordance with a predetermined printing pattern. The insulating ink is hardened, whereby an insulating layer is formed. A contact region of the wiring pattern that is used for electrical connection with a conductor other than the wiring pattern is not covered with the insulating layer. The printing pattern is delimited by the outline of a non-printing region including the contact region. The wiring pattern includes, in the non-printing region, a trunk wiring line leading, to the contact region, from a position on the wiring pattern at which the wiring pattern overlaps with the outline and a branch wiring line extending from a point on at least one side of the trunk wiring line and terminating without making contact with the outline.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: November 26, 2019
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Yutaro Kogawa, Mitsunori Sato, Yutaka Takezawa, Akitoshi Sakaue, Mitsutoshi Naito
  • Patent number: 10487222
    Abstract: The present invention relates to a conductive coating composition comprising a polyolefin copolymer resin comprising an olefin monomer and acrylic acid comonomer or (meth)acrylic acid comonomer, a plurality of anisotropic nanoparticles and a solvent.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 26, 2019
    Assignee: Henkel AG & Co. KGaA
    Inventors: Ard de Zeeuw, Nicole Auweiler, Gunther Dreezen, Inge van der Meulen
  • Patent number: 10483516
    Abstract: An electricity storage module unit that can improve installation work efficiency, and that can be used to build an electricity storage pack that is versatile in terms of installation. An electricity storage module unit is provided with an electricity storage module that includes a plurality of electricity storage elements, and the electricity storage module unit includes: a wiring member that is connected to the electricity storage module; a wiring connection part that connects the wiring member to the wiring member of another electricity storage module unit or to an external electrical component; and a unit base plate on which the electricity storage module is mounted. The unit base plate has a plurality of routing grooves that allow the wiring member to be routed such that a direction in which the wiring member is routed is changeable.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 19, 2019
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Ken Furusawa, Hitoshi Takeda, Ryoya Okamoto, Tetsuji Tanaka, Hiroki Hirai
  • Patent number: 10477702
    Abstract: A multilayer wiring board having a high degree of freedom of wiring design and realizing high-density wiring, and a method to simply manufacture the multilayer wiring board is provided. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically connected to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 ?m. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: November 12, 2019
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shigeki Chujo, Koichi Nakayama
  • Patent number: 10468654
    Abstract: A battery module includes a housing, a plurality of battery cells disposed in the housing, and a printed circuit board (PCB) assembly disposed in the housing. The PCB assembly includes a PCB and a shunt disposed across a first surface of the PCB. A second surface of the shunt directly contacts the first surface of the PCB, and the shunt is electrically coupled between the battery cells and a terminal of the battery module.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 5, 2019
    Assignee: CPS Technology Holdings LLC
    Inventors: Ronald J. Dulle, Mark D. Gunderson, Bryan L. Thieme
  • Patent number: 10468366
    Abstract: The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hong Cha, Chen-Shien Chen, Chen-Cheng Kuo, Tsung-Hsien Chiang, Hao-Juin Liu, Yao-Chun Chuang, Chita Chuang
  • Patent number: 10461001
    Abstract: This method for manufacturing a hermetic sealing lid member (1, 201, 301) includes forming a Ni plated metal plate (70, 170) by forming a Ni plated layer (11, 12, 41) on a surface of a metal plate (40) having a corrosion resistance and forming the hermetic sealing lid member by punching the Ni plated metal plate.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: October 29, 2019
    Assignee: HITACHI METALS, LTD.
    Inventors: Masayuki Yokota, Masaharu Yamamoto
  • Patent number: 10461055
    Abstract: A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: October 29, 2019
    Assignees: NIPPON MICROMETAL CORPORATION, NIPPON STEEL CHEMICAL & MATERIAL CO., LTD.
    Inventors: Takashi Yamada, Daizo Oda, Teruo Haibara, Tomohiro Uno
  • Patent number: 10462911
    Abstract: The present disclosure relates to a structure and a method for filling a via hole formed in a multilayer printed circuit board, and more particularly, to a structure and a method for filling a via hole formed in a multilayer printed circuit board, the structure and method enabling high-current transmission even in a narrow space in such a way that a via hole formed when a typical multilayer printed circuit board is manufactured is first filled with Cu and Ag plating, and the remaining vacant space is completely filled with a solder cream, thereby increasing the amount of conductors.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: October 29, 2019
    Assignee: LG CHEM, LTD.
    Inventors: Chang Hui Lee, Dong Hyun Kim
  • Patent number: 10455688
    Abstract: According to various aspects, exemplary embodiments are disclosed of board level shields with virtual grounding capability. In an exemplary embodiment, a board level shield includes one or more resonators configured to be operable for virtually connecting the board level shield to a ground plane or a shielding surface. Also disclosed are exemplary embodiments of methods relating to making board level shields having virtual grounding capability. Additionally, exemplary embodiments are disclosed of methods relating to providing shielding for one or more components on a substrate by using a board level shield having virtual grounding capability. Further exemplary embodiments are disclosed of methods relating to making system in package (SiP) or system on chip (SoC) shielded modules and methods relating to providing shielding for one or more components of SiP or SoC module.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: October 22, 2019
    Assignee: Laird Technologies, Inc.
    Inventors: Mohammadali Khorrami, Paul Francis Dixon, George William Rhyne