Abstract: A method for manufacturing an electronics assembly, includes obtaining or producing an electronics module, which includes a first circuitry on a first surface at a first side of a circuit board, at least one electronics component on the circuit board in electrical connection with the first circuitry, and at least one first connection portion on the first surface and/or an adjacent side surface at a peripheral portion of the circuit board, wherein the at least one first connection portion is electrically connected to or comprised in the first circuitry. The method further includes arranging the electronics module on a second substrate including a second connection portion connected to a second circuitry on a surface of the second substrate and arranging electrically conductive joint material onto the first and second connection portions to extend between them for electrically connecting the electronics module to the second circuitry.

Abstract: A packaged electronic device has a package structure, first leads, second leads and a tie bar. The package structure has a first side, a second side, a third side, a fourth side, a fifth side and a sixth side, the second side spaced from the first side along a first direction, the fourth side spaced from the third side along an orthogonal second direction, and the sixth side spaced from the fifth side along an orthogonal third direction. The first leads extend outward in a first plane of the second and third directions from respective portions of the third side, the second leads extend outward in the first plane from respective portions of the fourth side, and the tie bar is exposed along the fifth side in a second plane of the second and third directions, the second plane between the first plane and the first side.

Abstract: Embossed solder masks for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a package substrate includes the solder mask with non-planar features along a surface of the solder mask such that the area of the surface is increased. The non-planar features may correspond to concave recesses formed on the surface of the solder mask. Physical dimensions (e.g., widths, depths) and/or areal densities of the non-planar features of the embossed solder masks may vary based on local areas of the package substrate exclusive of conductive bumps. The non-planar features may be formed by pressing a mold having convex features against the surface of the solder mask. The solder mask may be heated while pressing the mold against the surface of the solder mask. In some embodiments, the mold includes regions lacking the convex features.

Abstract: A method of manufacturing a power amplifier package embedded with an input-output circuit including a dielectric circuit board, a heat sink and lead frames, the method comprising: the step of preparing the dielectric circuit board including the steps of forming a power amplifier hole in which a power amplifier chip is to be disposed on a dielectric substrate, printing an input matching network metal pattern on a left side of the power amplifier hole, and printing an output matching network metal pattern on a right side of the power amplifier hole, and sintering the input matching network metal pattern and the output matching network metal pattern printed on the dielectric substrate; the step of preparing the lead frames by etching alloy 42 and plating nickel; and the step of attaching the heat sink on a bottom surface of the dielectric circuit board.

Abstract: A hermetic high-current electronic package includes a package body and a base plate hermetically coupled to the package body. A semiconductor device is thermally mounted to the base plate and has a high-current output. A high-current input/output (I/O) terminal is bonded to the high-current output of the semiconductor device by a strap terminal that is an integral high current heatsink terminal. The high-current I/O terminal passes through a hole formed in a sidewall of the package body. A ceramic seal surrounds the high-current I/O terminal and has a first surface hermetically bonded to an outer surface of the sidewall of the package body. A metal hermetic seal washer surrounds the high-current I/O terminal and is bonded to a second surface of the ceramic seal and bonded to a portion of the high-current I/O terminal that passes through the metal hermetic seal washer.

Abstract: The present disclosure generally relates to printed circuit boards or printed circuit board assemblies for fiber optic communications. In one example, a method may include coupling at least one optoelectronic component to a surface of a printed circuit board. The method may include lasering the surface of the printed circuit board to form a laser-roughened area on the surface of the printed circuit board. The method may include coupling an optical component to the printed circuit board at the laser-roughened area on the surface of the printed circuit board.

Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.

Abstract: A display device includes a substrate including a display region, and a peripheral region that is outside of the display region, a plurality of dummy pads at the peripheral region, an insulating layer covering the plurality of dummy pads, wherein top surfaces of first portions of the insulating layer above the plurality of dummy pads are higher than top surfaces of second portions of the insulating layer between the plurality of dummy pads, and a plurality of pads over the second portions of the insulating layer at the peripheral region.

Abstract: A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer.

Abstract: A stress mitigation region is formed in which a predetermined number of stress mitigation holes penetrating through a wiring are disposed is formed in a proximity of a bonding portion of an electronic component via which the electronic component is bonded to the wiring with an electrically conductive bonding agent. Accordingly, even if a stress is generated in the wiring due to a heat, the stress mitigation holes are deformed so that the stress acted upon the electrically conductive bonding agent becomes small and a generation of cracks in the electrically conductive bonding agent can be suppressed. In addition, the stress mitigation holes are made circular so that concentrations of a current and the stress can be reduced and the generation of the cracks in the wiring can be suppressed.

Abstract: An embedded semiconductor package includes a semiconductor logic device comprising a plurality of signal input/output (I/O) pads spaced at a first pitch on an active surface thereof and a plurality of power I/O pads and ground I/O pads spaced on the active surface at a second pitch larger than the first pitch. At least one interconnect layer overlies the semiconductor logic device. Each of the at least one interconnect layers includes an insulating layer and a conductive layer formed on the insulating layer and extending into a plurality of vias formed therethrough. The conductive layer is electrically coupled to the plurality of signal I/O pads and the plurality of power I/O pads and ground I/O pads.

Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Abstract: This process for manufacturing an electrically conductive member for an electronic component comprises the following steps: providing a structure comprising at least one blind hole having a bottom and at least one internal lateral flank connected to said bottom via a base of said lateral flank; forming the member, this forming step comprising a step of growing an electrically conductive material in order to form at least one portion of the member in the blind hole, said growth being faster at the base of the lateral flank of the blind hole than on the rest of said lateral flank, said member when formed comprising a cavity arranged at that end of said member which is located opposite the bottom of the blind hole, said cavity being entirely or partially bordered by a rim.

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

Abstract: An electronic device includes an electronic component including a plurality of terminals and a circuit board on which the electronic component is mounted. The circuit board includes a board body, a plurality of electrode pads arranged on the board body, each of the electrode pads being connected to each of the terminals by solder, a first solder resist formed on the board body and having a plurality of first openings, each of the first openings accommodating each of the electrode pads, and a second solder resist formed on the first solder resist and having a plurality of second openings, each of the second openings being larger than each of the first openings and communicating with each of the first openings.

Abstract: An electronic component device having a first sealing frame formed on a main substrate and a second sealing frame formed on a cover substrate, both of which are composed of a Ni film. A bonding section bonds the first sealing frame to the second sealing frame. For example, a Bi layer is formed on the first sealing frame and an Au layer is formed on the second sealing frame, and then the first sealing frame and the second sealing frame are heated at a temperature of 300° C. for 10 seconds while applying pressure in the direction in which the first sealing frame and the second sealing frame are close contact with each other to form the bonding section. The bonding section is constituted by a mixed layer predominantly composed of a mixed alloy of a Ni—Bi—Au ternary alloy and Au2Bi.

Abstract: A surface mounted electronic component is provided. The surface mounted electronic component includes a main body, a circuit element, a conductive electrode, and a virtual electrode. The circuit element is arranged in the main body. The conductive electrode is disposed on an outer surface of the main body, wherein the conductive electrode electrically is connected to the circuit element. The virtual electrode is disposed on the outer surface of the main body, wherein the virtual electrode lies near the conductive electrode. There is a distance between the virtual electrode and the conductive electrode.

Abstract: A pad layout structure of a driver IC chip of a liquid crystal display device includes dummy power pads and dummy ground pads, which are disposed in corners of the driver IC chip and are connected to main power pads and main ground pads by metal lines in a chip-on-film (COF) package. Accordingly, it is possible to reduce the resistance of power supply lines and ground lines, to minimize a power dip of a block located far away from the main power pads and main ground pads, and to prevent a failure in power application, which may occur due to a decrease of adhesive strength at a specific position, by dispersing the adhesion positions of the power pads and ground pads.

Abstract: In a structure where an electronic component is mounted on a glass base material, an external electrode is provided on an opposite side to the component mounted on the base, and a through electrode and the base are welded to each other at a temperature equal to or higher than a glass softening point, electrical conduction is ensured between the electronic component and the external electrode. An electronic device includes a base, a through electrode which pass through the base and has a metal film formed on both end surfaces after an insulating material on the surface is removed by polishing, an electronic component which is provided on one surface of the through electrode through a connection portion, an external electrode which is provided on an opposite side to a side of the base on which the electronic component is provided, and a cap which protects the electronic component on the base.

Abstract: A PCB includes an outer layer and an inner layer. An electronic component is mounted on the outer layer. The outer layer further defines a first pad, a second pad, a third pad, a fourth pad, and a number of via holes. The electrical performances of the first pad and the second pad are the same to that of the inner layer. The first pad and the second pad are conducted to the electronic component. The third pad and the fourth pad are respectively conducted to the first pad and the second pad through the electronic component. The electrical performances of the third pad and the fourth pad are different from that of the inner layer. The via holes are respectively electrically connected to the third pad and the fourth pad.

Abstract: A wiring substrate includes a plurality of electrode terminals, to which external connection terminals of an electronic component are coupled, arranged in a row on one principal surface thereof, wherein the electrode terminals each include: a first linear portion; a second linear portion extending from an end of the first linear portion in a direction different from a direction of the first linear portion; and a bent portion that is a part where the first linear portion and the second linear portion are connected.

Abstract: A wiring board (package) includes: a cavity formed at a position corresponding to a chip mounting area of the outermost insulating layer on one side of both surfaces of the wiring board; a pad exposed from the surface of the insulating layer in the cavity; and a pad exposed from the surface of the insulating layer in a peripheral region of the cavity. A chip is flip-chip bonded to the pads in the cavity of the package, and another package is bonded to the pads in the peripheral region of the cavity, to thereby form a semiconductor device having a package on package (POP) structure.

Abstract: A circuit assembly (34) resistant to high-temperature and high g centrifugal force is disclosed. A printed circuit board (42) is first fabricated from alumina and has conductive traces of said circuit formed thereon by the use of a thick film gold paste. Active and passive components of the circuit assembly are attached to the printed circuit board by means of gold powder diffused under high temperature. Gold wire is used for bonding between the circuit traces and the active components in order to complete the circuit assembly (34). Also, a method for manufacturing a circuit assembly resistant to elevated temperature is disclosed.

Abstract: The present invention provides a circuit board and a method for manufacturing the circuit board, the circuit board and method allowing a further shorter connection distance between electrodes of a semiconductor device, and also allowing a sufficient thickness of a solder pre-coat in a soldering process. The circuit board comprises bonding pads for being connected with bumps of a semiconductor element, which act as connection terminals, the bonding pads being arrayed in parallel lines on a surface of the circuit board, and, on the adjacent parallel lines, the bonding pads being positioned to form a zigzag pattern along the parallel lines longitudinally.

Abstract: A surface mounted electronic component is provided. The surface mounted electronic component includes a main body, a circuit element, a conductive electrode, and a virtual electrode. The circuit element is arranged in the main body. The conductive electrode is disposed on an outer surface of the main body, wherein the conductive electrode electrically is connected to the circuit element. The virtual electrode is disposed on the outer surface of the main body, wherein the virtual electrode lies near the conductive electrode. There is a distance between the virtual electrode and the conductive electrode.

Abstract: An electronic carrier board is provided, including a carrier, at least two paired bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings corresponding in position to the two bond pads. The openings are aligned in the same direction and expose at least a first sidewall and a second sidewall of each of the two bond pads. The first sidewall is perpendicular to an alignment direction of the bond pads and the second sidewall is parallel to the alignment direction of the bond pads. A distance between the first sidewall of at least one of the bond pads and a corresponding side of a corresponding one of the openings is at least about 50 ?m greater than a distance between the second sidewall of the at least one bond pad and a corresponding side of the corresponding opening.

Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: To provide a printed wiring board where the impedance between pads through which differential signals pass has been set to a predetermined standard value. The printed wiring board includes a first conductor layer extending over an area excluding a hole formed for each pad group and filled with a dielectric, and a second conductor layer extending over an area containing areas facing the hole. The hole encompasses a plurality of areas facing predetermined respective pads which are adjacent to each other and which form the pad group from among the plurality of pads.

Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.