Abstract: A backplane is for electrically connecting electrical components and a method is for producing a backplane. The backplane includes a base board, conducting tracks arranged on and/or in the base board, and at least one actuator unit arranged on or in the base board.

Abstract: A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure.

Abstract: A semiconductor package structure includes a first package including a bonding region and a periphery region surrounding the bonding region, at least one insulating structure disposed in the bonding region of the first package, a second package disposed over the first package and the insulating structure in the bonding region, and a plurality of connectors disposed between the first package and the second package. The plurality of connectors provide electrical connection between the first package and the second package. Further, the insulating structure penetrates the first package and is spaced apart from the plurality of connectors.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes a substrate and a dielectric layer. The substrate has a wave guide pattern. The dielectric layer is disposed over the substrate. The photonic die is encapsulated by the encapsulant. The wave guide structure spans over the front side of the photonic die and a top surface of the encapsulant, and penetrates the dielectric layer to be optically coupled with the wave guide pattern.

Abstract: An apparatus includes a base portion having an upper surface and a lower surface opposite the upper surface. The apparatus also includes a first sidewall portion having a first upper portion distal the upper surface of the base portion and a first slanted sidewall between the first upper portion and the upper surface of the base portion. The apparatus further includes a second sidewall portion having a second upper portion distal the upper surface of the base portion and a second slanted sidewall between the second upper portion and the upper surface of the base portion. The first sidewall portion and the second sidewall portion define a first reservoir between the first slanted sidewall and the second slanted sidewall, the first reservoir being configured to receive a first chip package portion and to secure the first chip package portion in a first curing position.

Abstract: Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a conductor portion having a first portion and a second portion; at least three slots formed in the conductor portion between the first and second portions, each of the at least three slots having a length and at least one tip portion; at least two bridge portions each having a width separating two of the at least three slots and a length coupling the first and second portions; a first contact region disposed relative to the first portion and a second contact region disposed relative to the second portion; and at least one pair of magnetic sensor elements, a first pair of magnetic sensor elements arranged relative to and spaced apart from a first of the at least two bridge portions.

Abstract: The present invention provides a terminal structure 14 including a terminal 12 having a conductor 40 containing at least one metal selected from the group consisting of gold, silver, and copper, a first layer containing phosphorus and nickel disposed on the conductor 40, and a second layer having a nickel/phosphorus atomic ratio smaller than that of the first layer and containing Ni3P disposed on the first layer; and solder 70 disposed on the second layer of the terminal 12, while the second layer has a thickness of at least 0.35 ?m; and a module substrate 100 having the terminal structure.

Abstract: The present invention provides a circuit board and a method for manufacturing the circuit board, the circuit board and method allowing a further shorter connection distance between electrodes of a semiconductor device, and also allowing a sufficient thickness of a solder pre-coat in a soldering process. The circuit board comprises bonding pads for being connected with bumps of a semiconductor element, which act as connection terminals, the bonding pads being arrayed in parallel lines on a surface of the circuit board, and, on the adjacent parallel lines, the bonding pads being positioned to form a zigzag pattern along the parallel lines longitudinally.

Abstract: The present invention relates to a method for manufacturing an electronic assembly (50) comprising an electronic component, a cavity and a substrate which method comprises; —providing an electronic component (10) having a first pattern with a substantially closed configuration; —providing a cover (18) on a surface of the electronic component, which cover together with said surface defines a cavity (20), the closed configuration of the first pattern substantially enclosing the cover at said surface; —providing a substrate (30) having a second pattern with a substantially closed configuration, which closed configuration at least partially corresponds to the closed configuration of the first pattern and comprises a solder pad; —disposing solder material at the solder pad; —positioning the electronic component and the substrate so as to align both the substantially closed configurations of the first and second pattern, while the substrate supports a top surface (28) of the cover; —reflow-soldering the solder mate

Abstract: A wiring board includes a film base, a plurality of conductive wirings aligned on the film base, and protrusion electrodes formed of a plated metal in the vicinity of end portions of the conductive wirings, respectively. An outer surface at both side portions of the protrusion electrodes in cross section in a width direction of the conductive wirings defines a curve, and the protrusion electrodes in cross section in a longitudinal direction of the conductive wirings define a rectangular shape. The conductive wirings include a first conductive wiring having a wiring width of W1 and a second conductive wiring having a wiring width of W2 larger than W1, and the protrusion electrode on the first conductive wiring and the protrusion electrode on the second conductive wiring have a substantially same height.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: The invention provides a semiconductor chip package, and a means of forming such a semiconductor chip package, in which one or more semiconductor chips are electrically connected to a mounting substrate by wire bonding in which an adhesive tape is provided on the active surface of the semiconductor chips for encapsulating at least an upper portion of the bonding wires adjacent the active surfaces to improve the stability of the bonding wires during subsequent processing.