Tray Having Plural Circular Pockets Patents (Class 206/712)
  • Patent number: 11312559
    Abstract: The invention relates to a packaging tray composed of plastic with a base (10) and sidewalls (11) which adjoin the base (10) and delimit a receiving space for a product being packaged, and with a baseplate (2) which is placed onto the upper side of the base (10) and forms a supporting surface for the product being packaged, wherein the baseplate (2) and the base (10) are formed with at least one releasable connecting means for releasably fixing the baseplate (2) to the base (10) of the packaging tray (1), wherein the connecting means are complementary with respect to one another and are formed integrally in the base (10) and in the baseplate (2).
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 26, 2022
    Assignee: Silver Plastics GmbH & Co
    Inventor: Rene Derks
  • Patent number: 10840116
    Abstract: A wafer producing apparatus includes an ingot grinding unit that grinds the upper surface of an ingot to planarize the upper surface, a laser irradiation unit that positions the focal point of a laser beam with such a wavelength as to be transmitted through the ingot to a depth corresponding to the thickness of a wafer to be produced from the upper surface of the ingot and irradiates the ingot with the laser beam to form a separation layer, a wafer separating unit that separates the wafer from the ingot, and a tray having a support part that supports the separated wafer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 17, 2020
    Assignee: DISCO CORPORATION
    Inventors: Kentaro Iizuka, Naoki Omiya
  • Patent number: 10026436
    Abstract: Apparatus and methods for simultaneously supporting multiple workpieces inside a processing space of a plasma processing system for simultaneous two-sided plasma processing. The apparatus may be a fixture having a carrier plate configured to be supported inside the processing space and a plurality of first openings extending through the thickness of the carrier plate. The carrier plate is configured to contact each of the workpieces over an annular region at an outer peripheral edge so that the first and second sides of each of the workpieces is exposed to the plasma through a respective one of said plurality of first openings.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: July 17, 2018
    Assignee: Nordson Corporation
    Inventors: David K. Foote, James D. Getty
  • Patent number: 9694990
    Abstract: A transport and handing-over arrangement for disc shaped substrates, comprising a carrier (3) and a take-over arrangement (15). Both are moveable relative to each other. A relatively heavy substrate carrier (7) of magnetizable material is taken-over from the take-over arrangement (15) by distance control of a permanent magnet (17) at the take-over arrangement (15) or is returned therefrom to a carrier (3). The controlled drive of the permanent magnets (17) in the take-over arrangement (15) is performed by means of pneumatic piston/cylinder arrangements (19).
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: July 4, 2017
    Assignee: EVATEC AG
    Inventors: Stephan Voser, Bruno Gaechter, Pierre Matteacci
  • Patent number: 9691668
    Abstract: A wafer carrier comprises a supporting body having an opening therein, wherein said opening in said supporting body has a concave sidewall and a bottom surface in said supporting body which is curved in cross section; a plurality of vertical supporting rods configured to support and contact a wafer received in said opening and to displace said wafer from the bottom surface of the opening in said supporting body; wherein one of said supporting rods has an end for contacting and supporting said wafer; and wherein when viewing from a top view of the wafer carrier, one of said supporting rods has a base lining on the concave sidewall of said opening in said supporting body, a first concave side opposite to the base and two second concave sides connecting the base and the first concave side.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: June 27, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Chung-Ying Chang, Yun-Ming Lo, Chi Shen, Ying-Chan Tseng
  • Patent number: 9685186
    Abstract: Methods and apparatus for forming substrates having magnetically patterned surfaces is provided. A magnetic layer comprising one or more materials having magnetic properties is formed on a substrate. The magnetic layer is subjected to a patterning process in which selected portions of the surface of the magnetic layer are altered such that the altered portions have different magnetic properties from the non-altered portions without changing the topography of the substrate. A protective layer and a lubricant layer are deposited over the patterned magnetic layer. The patterning is accomplished through a number of processes that expose substrates to energy of varying forms. Apparatus and methods disclosed herein enable processing of two major surfaces of a substrate simultaneously, or sequentially by flipping. In some embodiments, magnetic properties of the substrate surface may be uniformly altered by plasma exposure and then selectively restored by exposure to patterned energy.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: June 20, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Majeed A. Foad, Jacob Newman, Jose Antonio Marin, Daniel J. Hoffman, Stephen Moffatt, Steven Verhaverbeke
  • Patent number: 8746666
    Abstract: A media carrier, adapted to hold a plurality of pieces of magnetic media, is disclosed. This media carrier can be placed on the workpiece support, or platen, allowing the magnetic media to be processed. In some embodiments, the media carrier is designed such that only one side of the magnetic media is exposed, requiring a robot or other equipment to invert each piece of media in the carrier to process the second side. In other embodiments, the media carrier is designed such that both sides of the magnetic media are exposed. In this scenario, the media carrier is inverted on the platen to allow processing of the second side.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Richard Hertel, Julian Blake, Edward Macintosh, Alexander Kontos, Frank Sinclair, Christopher Rowland, Mayur Jagtap, Sankar Ganesh Kolappan
  • Patent number: 8689812
    Abstract: In a first aspect, a substrate carrier is provided that includes an enclosure adapted to be sealable and to house at least one substrate. The substrate carrier includes a first port leading into the enclosure and adapted to allow a flow of gas into the enclosure while the substrate carrier is closed. Numerous other aspects are provided.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: April 8, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Vinay K. Shah, Eric Englhardt, Jeffrey C. Hudgens, Martin R. Elliott
  • Patent number: 8601975
    Abstract: In a first aspect, a loadport is provided. The loadport has a plate adapted to couple to a door of a substrate carrier to open the substrate carrier wherein the plate includes a first opening adapted to couple to a first port in the door of the substrate carrier on a first side of the plate and to couple to a gas source on a second side of the plate, and wherein the loadport is adapted to allow a flow of gas into the substrate carrier via the first opening in the plate. Methods of purging substrate carriers are provided, as are numerous other aspects.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: December 10, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Vinay K. Shah, Eric Englhardt, Jeffrey C. Hudgens, Martin R. Elliott
  • Patent number: 8397917
    Abstract: A wafer-retaining unit has a plurality of vertically superimposed single-wafer retaining sections, each having a wafer-retaining frame abutting against only a lower end edge portion of the outer periphery of a semiconductor wafer, a wafer-securing frame disposed vertically movably relative to the wafer-retaining frame to abut against only an upper end edge portion of the outer periphery of the semiconductor wafer, and wafer lift members that lift the semiconductor wafer to a position where it is upwardly separate from the wafer-retaining frame and keeps the semiconductor wafer in this position. Consequently, a plurality of semiconductor wafers can be accommodated efficiently and safely without increasing the space between each pair of mutually adjacent semiconductor wafers. At the same time, the semiconductor wafers can be loaded and unloaded satisfactorily.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: March 19, 2013
    Assignee: Miraial Co., Ltd.
    Inventors: Nobuyuki Kasama, Yukihiro Hyobu
  • Patent number: 8365919
    Abstract: A substrate storage container includes: a container body of a front open box type for holding a multiple number of semiconductor wafers supported in alignment by supporting ribs; a bottom plate removably attached to the bottom of the container body; and a pair of conveyor contact rails integrally formed along both the left and right sides of this bottom plate. These conveyor contact rails inhibit vibrations and impacts acting on the semiconductor wafers when the sealed container body is conveyed by a conveyor.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: February 5, 2013
    Assignee: Shin-Etsu Polymer Co., Ltd.
    Inventors: Takayuki Nakayama, Atsushi Sumi
  • Patent number: 8074597
    Abstract: In a first aspect, a substrate carrier is provided that includes an enclosure adapted to be sealable and to house at least one substrate. The substrate carrier includes a first port leading into the enclosure and adapted to allow a flow of gas into the enclosure while the substrate carrier is closed. Numerous other aspects are provided.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: December 13, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Vinay K. Shah, Eric Englhardt, Jeffrey C. Hudgens, Martin Elliott
  • Patent number: 7882616
    Abstract: In one embodiment, a method can include providing first and second intermediate structures, each having first and second surfaces. Also, the method can include placing the first surface of the first intermediate structure adjacent to the first surface of the second intermediate structure, such that the first and second intermediate structures are in a stacked relationship. Additionally, the method can include simultaneously removing at least a portion of each of the second surfaces of the first and second intermediate structures while in the stacked relationship. Furthermore, the method can include forming a plating layer on each of the first and second surfaces of each of the first and second intermediate structures. Moreover, the method can include forming a magnetic layer on the second surface but not the first surface of each of the first and second intermediate structures.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: February 8, 2011
    Assignee: Seagate Technology LLC
    Inventor: Joseph Allen
  • Patent number: 7631419
    Abstract: A disk processing device holds and rotates a disk with a spindle. Processing tapes are supplied out and wound up by a tape reel unit so as to sandwich and be pressed on both surfaces of the disk through contact rollers. As a crankshaft is rotated, a sliding plate rotates around it and a slidable shaft rotates around a fulcrum part while sliding along the sliding plate such that the contact roller undergoes a reciprocating motion in a radial direction of the disk together with a slider rotatably attached to the slidable shaft.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: December 15, 2009
    Assignee: NIHON Micro Coating Co., Ltd.
    Inventors: Hiromitsu Okuyama, Yuji Horie
  • Patent number: 7504315
    Abstract: To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihisa Matsubara, Hiromichi Suzuki, Wahei Kitamura, Kosho Akiyama, Seiji Kato
  • Publication number: 20090050519
    Abstract: A semiconductor chip housing tray that is used in a state of being stacked in a plurality of stages and houses a plurality of semiconductor chips, includes: a base plate; a plurality of upper surface protruding parts provided to an upper surface of the base plate and dividing the upper surface of the base plate into a plurality of first semiconductor chip housing areas; and a plurality of under surface protruding parts provided to an under surface of the base plate and dividing the under surface of the base plate into a plurality of second semiconductor chip housing areas. In the semiconductor chip housing tray, a margin width of the first semiconductor chip housing areas with respect to the semiconductor chips is smaller than a margin width of the second semiconductor chip housing areas with respect to the semiconductor chips.
    Type: Application
    Filed: July 11, 2008
    Publication date: February 26, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Ryohei TAMURA, Tomoyuki SHINDO, Hironori OTA, Kazuo YAZAWA
  • Publication number: 20090045196
    Abstract: An apparatus for holding stacked trays includes a cover and a hooking unit. The cover protects an upper surface of the stacked trays. The hooking unit is connected to the cover. The hooking unit is drawn from at least two side surfaces of the cover along the side surfaces of the stacked trays, to hold both lower ends of the stacked trays. Thus, the stacked trays may be easily held only by hooking the hook on the lower end of the stacked trays.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 19, 2009
    Inventors: Jae-Nam Lee, No-Shin Park, Jong-Hoon Kim, Woong-San Na
  • Publication number: 20090038987
    Abstract: A loading tray 13 supports at least one thin plate safely and reliably. It comprises a first loading portion 18, provided on one side thereof, on which at least one thin plate is loaded; a second loading portion 19, provided on the other side thereof, fitted to the first loading portion 18 of adjacent loading tray 13 to form a housing space sealed off from the external environment, for sandwiching the thin plate within the housing space, and for loading the thin plate on the loading tray when the loading tray is placed upside-down; a hook 30, provided on one side thereof, for coupling with an adjacent loading tray 13; and a hook locking mechanism 31, provided on the other side thereof, for coupling with the hook 30 of an adjacent loading tray 13. As many loading trays 13 as the number of the thin plate is stacked to constitute a thin plate container 11. The thin plate container 11 can support the thin plate from both upper and lower sides.
    Type: Application
    Filed: November 28, 2006
    Publication date: February 12, 2009
    Applicant: MIRAIAL CO., LTD.
    Inventor: Yukihiro Hyobu
  • Publication number: 20090023303
    Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.
    Type: Application
    Filed: May 20, 2008
    Publication date: January 22, 2009
    Inventor: Yoshiaki Kobayashi
  • Patent number: 7399657
    Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Todd O. Bolken, Chad A. Cobbley
  • Patent number: 7390758
    Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: June 24, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Yoshiaki Kobayashi
  • Patent number: 7322098
    Abstract: Various methods and apparatus for simultaneously processing two single-sided hard memory disks is provided. Disks are positioned in pairs, with one surface of one disk positioned adjacent one surface of the second disk, with the disk surfaces touching or with a slight separation between them. In this back-to-back orientation, the disk pairs may be processed using conventional double-sided disk processing equipment and techniques. However, each disk will not have two active surfaces. Because of the positioning of the disks during processing, only one surface of each disk will be subjected to full processing. Therefore, each disk will only have one active side.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: January 29, 2008
    Assignee: Maxtor Corporation
    Inventors: Gerardo Buitron, Clarence Gapay, John Grow, Bruce Hachtmann, Kwang Kon Kim, Huan Nguyen, Tom O'Hare
  • Patent number: 7172981
    Abstract: A sealed type container accommodating a semiconductor substrate is positioned to a load port of a semiconductor manufacturing apparatus. The semiconductor substrate is taken out of the container. An ionizer is used for static-charge-eliminating the semiconductor substrates before and after process treatment in a transport area between the load port and a treatment section. The static-charge-eliminated semiconductor substrate is accommodated in the container positioned to the load port. Thus, it is possible to decrease foreign materials adhering to the semiconductor substrate and errors in handling the semiconductor substrate.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: February 6, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Yoshiaki Kobayashi
  • Patent number: 7168153
    Abstract: Various apparatus and methods are provided for positioning and handling single-sided hard memory disks. A disk carrier is provided with ribs formed on the inside surface of opposing side walls. The ribs form disk receiving grooves or channels. The ribs further comprise an alternating pattern of large and small ribs. The large ribs separate pairs of disks from other pairs, the small ribs separate and maintain spacing of the two disks comprising each pair of disks.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: January 30, 2007
    Assignee: Maxtor Corporation
    Inventors: Gerardo Buitron, Walter Crofton, Bruce Hachtmann, David Newman
  • Patent number: 7112305
    Abstract: A method and system for economically packaging microarrays into sealed reaction chambers and storage vessels. A pocket strip is manufactured as a linear sequence of pockets, or wells, into which microarrays are positioned. A cover strip is then heat sealed to the upper surface of the pocket strip to create a linear sequence of sealed reaction chambers or storage vessels each containing a microarray. Mechanical features or optical features are included along the length of the pocket strip to facilitate mechanical translation and positioning of microarrays embedded within the microarray strip. Septa are affixed to, or embedded within, the cover strip to provide resealable ports through which solutions can be introduced into, or extracted from, the reaction chambers.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: September 26, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: John F. McEntee, Jay K. Bass, Roy H. Kanemoto
  • Patent number: 7059476
    Abstract: A first construction of a tray for electronic parts according to the present invention is provided with an engaging cut-out corner portion which is formed by cutting a corner portion of a table-like flat portion which is arranged diagonally with respect to a-cut-out corner portion. A second construction of a tray for electronic parts according to the present invention is provided with a pawl engaging protruding portion which is formed on a step-like peripheral edge portion above a cut-out portion. In a third construction of a tray for electronic parts according to the present invention, when two trays are stacked up so that the top faces thereof face each other, an engaging first-shaped protrusion which is formed around a predetermined pocket of one tray engages an engaging second-shaped protrusion which is formed around a predetermined pocket of the other tray.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: June 13, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisayoshi Kunii, Koji Koga, Reikichi Hatori
  • Patent number: 6844242
    Abstract: A boat (4) has a recess (5) for supporting a laminated wafer (50). The recess (5) has a first side surface (5a), a first bottom surface (5b), a second side surface (5c), a second bottom surface (5d) and a third side surface (5e). Viewing from an upper surface of the boat (4), the second bottom surface (5d) is located in a position lower than the first bottom surface (5b). The laminated wafer (50) is mounted on the boat (4) in the state that a side surface of a first silicon wafer (1) is not in contact with the second bottom surface (5d) of the recess (5) and a side surface of a second silicon wafer (2) is in contact with the first bottom surface (5b) of the recess (5). A second main surface (2a) of the second silicon wafer (2) is in contact with the first side surface (5a) of the recess (5) and a second main surface (1a) of the first silicon wafer (1) is in contact with the third side surface (5e) of the recess (5).
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: January 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Hideki Naruoka, Nobuyoshi Hattori, Hidekazu Yamamoto
  • Publication number: 20040211701
    Abstract: A wafer carrier opener is provided. The wafer carrier opener may eliminate the use of two separate actuators by using a four-bar linkage mechanism. The wafer carrier opener includes a wafer carrier door receiver, a horizontally stationary member, and a link coupled between the wafer carrier door receiver and the horizontally stationary member so as to allow horizontal movement of the wafer carrier door receiver.
    Type: Application
    Filed: March 5, 2002
    Publication date: October 28, 2004
    Inventor: William Tyler Weaver
  • Patent number: 6475432
    Abstract: A device for use in carrying and supporting a work piece before, during, and after a treatment process. The device can be used for both shipping and treating the work piece, and the device will not adversely affect the work piece during the treatment process. The device comprises at least one plate which has at least one relieved region for holding a work piece. The plate has a density the same as or very similar to the density of the work piece, so that the plate and work piece together have a substantially uniform density.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: November 5, 2002
    Assignee: Ion Beam Applications, Inc.
    Inventor: Victor J. Balmer
  • Publication number: 20020130061
    Abstract: A wafer boat for supporting silicon wafers. The wafer boat includes a ceramic body having at least one wafer support structure sized to support a silicon wafer thereon. A ceramic coating is disposed on a surface of the wafer slot. The ceramic coating has an impurity migration preventing thickness and a wafer contact surface. The wafer contact surface has a post coating surface finish, which substantially prevents slip in the silicon wafers.
    Type: Application
    Filed: June 19, 2001
    Publication date: September 19, 2002
    Inventor: Richard R. Hengst
  • Patent number: 6341935
    Abstract: A wafer boat for securely holding wafers therein during processing in a vertical furnace and a method for loading dummy wafers into a wafer boat without having to remove/reload for each oxidation process have been disclosed. In the wafer boat, a plurality of cavities are formed by horizontal notches in support posts together with horizontal ridges that are integrally formed with the support posts. A raised portion extending upwardly from a top surface of the horizontal ridge such that any possible outward movements of the dummy wafer, even after repeated loading/unloading operations, from the cavity can be prevented. A suitable height of the raised portion is between about 0.2 mm and about 2 mm, a more preferred range for the height is between about 0.2 mm and about 0.5 mm.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: January 29, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Heng-Yi Tseng
  • Publication number: 20010047978
    Abstract: A process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed. The semiconductor wafers lay in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers. The set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set. An item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing. There is also a carrier which is suitable for carrying out the process.
    Type: Application
    Filed: April 4, 2001
    Publication date: December 6, 2001
    Applicant: WACKER SILTRONIC GESELLSCHAFT FUR HALBLEITERMATERIALIEN AG
    Inventors: Guido Wenski, Gerhard Heier, Wolfgang Winkler, Thomas Altmann
  • Patent number: 6074479
    Abstract: This invention anneals a vertical stack of two or more groups of unseparated wafers, with approximately 10 wafers in each group. The invention makes it possible to anneal more wafers in a single annealing operation under a variety of conditions, including: oxygen outer diffusion annealing to form a denuded zone; annealing to control bulk micro defects and provide intrinsic gettering functions; annealing to enhance gate oxide integrity by eliminating crystal-originated particles from the wafer surface and internal grown-in or as-grown defects; and suppression of dislocation and slip in elevated temperature environments.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: June 13, 2000
    Assignee: Sumitomo Metal Industries Ltd.
    Inventors: Naoshi Adachi, Takehiro Hisatomi, Masakazu Sano