Abstract: An apparatus which inserts electronic memory modules into test equipment via direct horizontal insertion eliminating the need for intermediary connectors or adapters. The apparatus incorporates guide rails that maintain precise alignment of the electronic memory modules through the testing apparatus, sensors and microprocessor controlled belt apparatus to clear the automated transport paths of electronic memory module handler apparatus and automatically stacks the tested electronic memory modules.

Abstract: The present invention relates to a SIMM/DIMM board handler, which enables a single test site handling machine to be integrated into an inline, multi-site test cell, and includes an angled conveyor belt, an angled fail tray for transporting and sorting tested circuit boards and an adjustable circuit probe for performing separate testing of circuit boards.

Abstract: The present invention provides a shutter system for use with an automated semiconductor chip handling device. The semiconductor chip handling device includes a track down which semiconductor chips travel. Reliefs are positioned on the track to prevent the semiconductor chips from escaping. A gap in the relief provides access to the semiconductor chips so that they may be removed from the track. A pair of shutters pivot between a first position where they cover the gap and a second position where the gap is uncovered so that chips may be removed from the gap without chips escaping from the track during normal operation.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: A semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer 2 for controlling a plurality of semiconductor device testing apparatus 1A, 1B, and 1C, and a dedicated classifying machine 3. Storage information memory means 4 for storing storage information of each semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and the like is provided in the host computer 2. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in the handler part 11 of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory means.

Abstract: A method for continuous, non lot-based manufacturing of integrated circuit (IC) devices of the type to each have a unique fuse identification (ID) includes: reading the fuse ID of each of the IC devices; advancing multiple lots of the IC devices through, for example, a test step in the manufacturing process in a substantially continuous manner; generating data, such as test data, related to the advancement of each of the IC devices through the step in the process; and associating the data generated for each of the IC devices with the fuse ID of its associated IC device.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: A semiconductor device sorting method and apparatus involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a memory or other semiconductor device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug-in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given device grade.

Abstract: A semiconductor device sorting method and apparatus involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a memory or other semiconductor device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug-in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given device grade.

Abstract: A testing station tests integrated circuits and determines if the integrated circuits pass or fail predefined tests. The integrated circuits are placed in a pass bin if the integrated circuits passed the tests, or a fail bin if the integrated circuits failed the tests. A marking station marks identification information on the integrated circuits in the pass bin. The testing and marking stations are both included in a single, integrated tester-marker system.

Abstract: A stopping device (30) for automation modules of printed circuit boards (PCB) comprises stopping means (31) to stop a PCB (1) advancing on a conveyor (20) of an automation module in a stop position and pressure means (36) to apply pressure on the PCB (1) when it arrives in the vicinity of the stopping position, so as to avoid rebound of the PCB (1) against the stopping means (31) and impart pressure on the PCB (1) when it must be removed from the stopping position, so as to give the PCB a high acceleration.

Abstract: A pad 1051, air cylinder 1052, cylinder control valve 1053, vacuum generator 1054, feed valve 1055, break valve 1056, and pressure sensor 1057 are assembled together to form an IC pickup 105d.

Abstract: A test station with multiple output bins on an output platform receives electronic devices under test. At each of the different output bins on the output platform, replaceable trays which accept the electronic devices are positioned. After testing of a device is completed, an automatic device handler removes a device from the test station and places it at an appropriate bin based on the test results. As the trays at each bin become full, the trays are removed and empty trays are placed at the bin. A unique guide is located near each bin position on the output platform and each tray is shaped to match one of the guides. When a tray is placed at a bin location, it will properly fit at only one bin. In certain embodiments, all the trays are identically shaped and a clip, which attaches to the side of a tray, is used to provide the complementary shape to one of the guides.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: Parametric test data is taken on a sampled set of a particular integrated circuit (IC) using both an Automatic Test Equipment (ATE) tester and a system test motherboard. The parametric test data comprises maximum operating frequency, maximum operating temperature and minimum operating power supply voltage. A maximum operating frequency is determined at a particular fixed operating temperature and power supply voltage. A maximum operating temperature is determined at a particular fixed operating frequency and power supply voltage. Finally, a minimum operating power supply voltage is determined at a particular fixed operating frequency and temperature. Multiple two parameter graphs are plotted and the slope or numerical derivative for each plot is calculated as conversion factors. During a normal production run for the particular IC performance limit data is taken on the ATE tester comprising the same three parameters of maximum operating frequency at a particular temperature and power supply voltage.

Abstract: An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices.

Abstract: An inventive method for sorting integrated circuit (OC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices.

Abstract: A semiconductor device testing system is provided which can efficiently utilize a plurality of semiconductor device testing apparatus. There are provided a host computer 2 for controlling a plurality of semiconductor device testing apparatus 1A, 1B, and 1C, and a dedicated classifying machine 3. Storage information memory means 4 for storing storage information of each semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and the like is provided in the host computer 2. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in the handler part 11 of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory means.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: The invention provides methods for marking packaged ICs. In a first embodiment, only the minimum performance information is first marked on the package, regardless of the actual performance of the IC. This method avoids a second marking step for all ICs sold as low-performance ICs. In another embodiment, only one inking and curing step is required for all ICs. According to this method, all specified performances are marked on the packaged IC at the first marking. The IC is then tested to determine the actual performance, and all performance markings not applicable to the IC are removed, preferably with a laser. Alternatively, all applicable performance markings are identified (e.g., underlined or enclosed with a laser marking).

Abstract: An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices, and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices.

Abstract: A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes.

Abstract: A test handler for automatically testing rambus type semiconductor devices.

Abstract: A semiconductor device sorting method and apparatus involve development of small, self-contained and focused “qualification” or “sort” algorithm test programs or “modules”, each of which modules may test for the validity of a particular, selected grade of a memory or other semiconductor device based on the results of a test pattern associated with, or exhibited by, a particular device under test. Separating the test code from the main flow file of the test program into the aforementioned “plug in” qualification or sort modules permits the test code to be much simpler and facilitates better organization, as each qualification or sort module may be independent of any other qualification or sort module and only determines in response to its associated test pattern whether or not (TRUE or FALSE) a device qualifies in a given device grade.

Abstract: A method for classifying defects includes imaging an inspected object. An image of a defect candidate is extracted from an image obtained by said imaging step. Said extracted defect candidate image is classified into a first category. Said extracted defect candidate image is classified into a second category. Said extracted defect candidate image and information relating to said classification into said first category and information relating to said classification into said second category are displayed on a screen.

Abstract: An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices.

Abstract: The present invention relates to a loading/unloading control apparatus of a semiconductor device and a control method thereof in which a time for loading/unloading a semiconductor device can be saved when a produced semiconductor device is loaded and unloaded to be tested. The present invention provides a loading/unloading control method of a semiconductor device including the steps of: determining whether a semiconductor device for being sorted to an unloading buffer exists by a microprocessor; determining whether a sorting tray has been prepared when the semiconductor device exists to be sorted to the unloading buffer; requiring the sorting tray to be replaced by the microprocessor when the sorting tray has not been prepared; and feeding the semiconductor device served at the unloading buffer to the sorting buffer by a X-Y axis picker during the replacing of sorting tray.

Abstract: A microdevice reject handling system is provided for in a microdevice processing/feeder system. The feeder mechanism is immediately adjacent to the processing mechanism for receiving and moving microdevices away from the processing mechanism. It uses a conveyor which has a dead space in which microdevices cannot be placed by a robotic transport system, which moves microdevices from the processing mechanism to the feeder mechanism. The microdevice reject handling system is partially positioned in the feeder mechanism dead space for receiving rejected microdevices. It includes a reject bin with a storage portion for storing rejected microdevices beside the feeder mechanism and rests on a bracket containing an optical sensor system for determining when the storage portion is full.

Abstract: In a tray conveying apparatus and method for, for instance, semiconductor parts, a main station and substation which have a tray conveying function are driven slidably in a direction perpendicular to a tray conveying line by a station sliding mechanism. When the preparation of a satisfactory-parts tray is required, the sub-station is positioned on the conveying line, and a satisfactory-parts tray is prepared on this sub-station by means of the exchange of parts, etc. Afterward, both main station and sub-station are caused to slide so that the main station is positioned on the conveying line. In this state, the satisfactory-parts tray is positioned in the vicinity of the conveying line, and a tray on the main station is replenished with satisfactory parts from the satisfactory-parts tray. A table sliding mechanism is further provided that has an upper-stage table, which carries a defective-parts tray, and a lower table, which caries a reclaimable-parts tray.

Abstract: A tray transfer arm 205 for transferring one or more customer trays KST which hold semiconductor devices IC, comprises a pair of tray holders 205a, 205b which are provided substantially in the upper and lower direction.

Abstract: A known good die testing apparatus for pre-package testing singulated semiconductor die includes a plurality of test nests for receiving at least one of the singulated semiconductor die, each test nest including first and second portions which are movable away from one another to receive the singulated die, the first portion having a probe card coupled thereto which includes at least one needle for electrically connecting to a first side of the semiconductor die and at least one first edge connector electrically coupled to a respective needle; and at least one test unit in movable communication with respect to the test nests, the test unit being adapted to removably engage the first edge connector of the test nests, the test unit including at least one electrical circuit for performing electrical tests on the semiconductor die.

Abstract: An apparatus in accordance with the present invention includes separate transporting units respectively for good and rejected semiconductor devices. As a result, respective handlings of the rejected and good devices, such as loading of the good devices into a burn-in board or an unloading tray and loading of the rejected devices into a rejecting tray, can be performed separately without interfering each other.

Abstract: Automatic semiconductor part handler. In one aspect the handler includes a source of parts and a transfer mechanism for transferring a part from the source to a belt assembly. The belt assembly includes a belt, a belt displacement controller, and an image forming device for forming an image of the part with respect to a desired end point. The belt displacement controller is coupled to the belt to move the belt based upon the image of the part with respect to the desired end point, thereby positioning the part in a precise location with respect to the direction of motion of the input belt.

Abstract: A method for sorting integrated circuit chips. At least one physical defect is detected in the semiconductor chips. The semiconductor chips are sorted based upon the physical defect.

Abstract: A test control system for controlling overall test procedures which processes test data generated from the final test process and analyzes bin category results. The control system uses testers for testing electrical characteristics of IC devices, a host computer for processing data transmitted from the testers and for creating a number of database structures, and distributed computers for monitoring the test progress and analyzing the test results using the database structures stored in the host computer. A control method using the control system includes the steps of: performing a final test as a lot; monitoring the status of the final test progress while storing test data during the final test; determining if the final test is completed; performing a lot decision after the final test is completed based on bin category limits; and displaying the lot decision result and storing the test data.

Abstract: In a machine for testing and sorting miniature electrical inductors of the type having spaced-apart, opposed first and second metal-terminated ends, wherein the machine includes a feed station having an inlet, an outlet and adapted to receive bulk quantities of inductors, a rotatably mounted transport wheel the wheel having an outer rim portion that includes a plurality of separate, spaced-apart compartments adapted to receive inductors from the feed station whereby each of the compartments has a central axis that is oriented perpendicular to the axis of the wheel, a test station including testing apparatus, and a sorting station operatively connected to the testing apparatus whereby an electrical inductor that is within the sorting station can be directed by a transfer means into one of at least two receiving means based on the testing performed at the test station, wherein when an electrical inductor is located in one of the compartments of the wheel.

Abstract: An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices, and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices.

Abstract: A method for dispensing, receiving, storing, testing or binning packaged integrated circuit devices using at least one vertically-oriented, removable, tubular magazine disposed above a controllably-driven, rod-like indexing element extending from a drive below the magazine. A magazine, with an associated indexing element and drive, is configurable as an individual magazine module. The indexing element, under power of the drive, raises or lowers a vertical stack of devices to a desired level adjacent the top of the magazine to dispense or receive an individual device from a feed mechanism, such as a pick-and-place mechanism. A number of magazine modules may be assembled in a multi-module array, which is particularly suitable for binning tested devices, with a sort category being directed to each magazine.

Abstract: An integrated circuit sorter automatically prevents the binning of a tested integrated circuit into a wrong container, such as a wrong tube, depending on the results of testing the integrated circuit. The automated integrated circuit sorter includes a respective switch for indicating that each output carries one of good or bad integrated circuits. A container identifier at each output identifies the type of container placed at the output. The container is determined to be for carrying good integrated circuits or bad integrated circuits. If the type of container placed at the output does not correspond to the type of integrated circuits at the output, then an integrated circuit stopper automatically blocks the admission of those integrated circuits into that container. The container identifier includes a light emitter and an optical sensor. A data processor determines whether a correct container or a wrong container is at the output.

Abstract: A semiconductor device testing apparatus in which ICs to be tested are transferred to a test tray TST in a loader section, the test tray is transported into a test section to test the ICs, after the completion of the test, the tested ICs on the test tray are transferred from the test tray onto a general-purpose tray in an unloader section, and the test tray which has been emptied of the tested ICs is transported to the loader section, and the above operation is repeated, and which can detect whether there is an IC on the test tray or not is provided. An IC detecting sensor for monitoring whether an IC exists on the test tray or not is provided at at least one of the positions between the unloader section and the loader section, the loader section and the test section, and the test section and the unloader section.

Abstract: An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices, and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices.

Abstract: A handler is provided in which an operator can easily input test conditions for ICs of a lot. The handler includes a test parameter memory part, a parameter set memory part, a schedule memory part, a lot data memory part, a retest data memory part, and a control. The test parameter memory part restores, as the test conditions for the ICs to be tested of each lot, at least parameters of basic conditions of operation, parameters of classifying conditions for the tested devices, at least one parameter of socket selecting conditions in the test section, and parameters of temperature conditions for the constant temperature chamber. The parameter set memory part stores a plurality of parameter sets each set of which is a combination of parameters, one for one condition stored in the test parameter memory part. The schedule memory part stores a name of each lot, and a parameter set and a status corresponding to each lot name in testing sequence. The lot data memory part stores data of the test results for each lot.

Abstract: An IC device transfer method for IC handler accommodates both a tray and a rod-shaped magazine. The tray installs a plurality of IC devices which transport in horizontal directions in the IC handler. The rod-shaped magazine installs a plurality of IC devices which transport in vertical directions in the IC handler. A device reinspection method in the IC test handler reinspects the IC devices stored in the tray or magazine without human intervention, sorts in accordance with the test results, and stores in either the rod-shaped magazine or the tray. For this purpose, a tray supply section transfers a user tray to a test tray, whereas a magazine supply section and a pick carrier section transfer a rod-shaped magazine to the test tray. An inspection setting sets the number of reinspection, the classification of inspection results, and the storage tray/magazine. The IC devices are loaded from the magazine and the user tray to the test tray and are tested.

Abstract: A semiconductor device testing system is provided efficiently utilizes a plurality of semiconductor device testing apparatus. More particularly, a host computer controls a plurality of semiconductor device testing apparatuses and a dedicated classifying machine. A storage information memory stores storage information of each semiconductor device such as a number assigned to each tested semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and is provided in the host computer. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in a handler part of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory.

Abstract: A test control system for controlling overall test procedures which processes test data generated from the final test process and analyzes bin category results. The control system uses testers for testing electrical characteristics of IC devices, a host computer for processing data transmitted from the testers and for creating a number of database structures, and distributed computers for monitoring the test progress and analyzing the test results using the database structures stored in the host computer. A control method using the control system includes the steps of: performing a final test as a lot; monitoring the status of the final test progress while storing test data during the final test; determining if the final test is completed; performing a lot decision after the final test is completed based on bin category limits; and displaying the lot decision result and storing the test data.

Abstract: An apparatus is disclosed for automatically testing electronic memory modules. The electronic memory modules are automatically positioned, one at a time, in a test station position for registration with test contacts of a test connector assembly. The test connector assembly includes a mounting fixture which secures the test contacts, such that first ends of the test contacts are appropriately aligned for registering with surface contacts of the electronic memory modules. Second, opposite ends of the test contacts are mounted to a transition board. The transition board has first and second opposite edges, with the first edge having surface contacts which are closely spaced for registering with the test contacts, and the second edge having surface contacts which are more widely spaced than those on the first edge for registering with connector contacts of a tester module. Conductive traces extend between the surface contacts of the first and second edges of the transition board.

Abstract: A test method for testing an integrated circuit (IC) device, including a step of checking the handler contacts with IC devices to be tested after a test apparatus and a handler are completely set up and before actual testing operations commence. The handler contact check device includes a handler contact check board mounted to the handler, which is provided with a plurality of pins directly contacting outer terminals of the IC devices, and wiring circuits for transferring contact check electrical signals from a test apparatus to the contacts between the plurality of pins and the outer terminals, and for transferring output electrical signals from the contacts to the test apparatus, and a contact check package device having the same shape and outer terminals as the IC devices to be tested.

Abstract: Disclosed is a method for fabricating devices so that several devices at a time can be tested and sorted. The devices are placed in a carrier so that each device occupies a discrete position. The carrier includes an identification marker, and each device is identified by its position in the carrier. The carrier is sent to multiple assembly and/or testing stations, and data for each device is collected and stored in a central data base according to its position in the carrier. Each device may then be sorted according to the collected data and its position in the carrier.

Abstract: This invention is a test methodology that immediately retests failed chips to recover false tester reads with no loss of test floor capacity during multiprobe production testing of integrated circuit chips on a wafer. This method retests a chip a second time prior to the multiprobe going to the next chip on the wafer, thus eliminating lost time in repositioning the multiprobe.