Semiconductor-type Nonmetallic Material Patents (Class 228/123.1)
  • Patent number: 11569151
    Abstract: A composite assembly of three stacked joining partners, and a corresponding method. The three stacked joining partners are materially bonded to one another by an upper solder layer and a lower solder layer. An upper joining partner and a lower joining partner are fixed in their height and have a specified distance from one another. The upper solder layer is fashioned from a first solder agent, having a first melt temperature, between the upper joining partner and a middle joining partner. The second solder layer is fashioned from a second solder agent, having a higher, second melt temperature, between the middle joining partner and the lower joining partner. The upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, to fill the gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 31, 2023
    Assignee: Robert Bosch GmbH
    Inventors: Andreas Krutsch, Christian Schiele, Erik Sueske, Juergen Zipprich, Thomas Suenner
  • Patent number: 11510340
    Abstract: A system may include a thermal source, a thermal sink, and heat-rejecting media comprising flexible graphite thermally coupled between the thermal source and the thermal sink and configured to transfer heat from the thermal source to the thermal sink.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: November 22, 2022
    Assignee: Dell Products L.P.
    Inventors: Steven Embleton, Travis C. North
  • Patent number: 11404286
    Abstract: A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering only top faces on the upper surface side of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 2, 2022
    Assignee: OHKUCHI MATERIALS CO., LTD.
    Inventors: Kaoru Hishiki, Keiichi Otaki, Hidehiko Sasaki, Kotaro Tomeoka
  • Patent number: 11400514
    Abstract: Sintering tool (10) with a cradle for receiving an electronic subassembly (BG) to be sintered, characterized by at least one support bracket (20), arranged at two locations opposite the cradle, for fixing a protective film (30) covering the electronic subassembly (BG).
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: August 2, 2022
    Assignee: Danfoss Silicon Power GmbH
    Inventors: Frank Osterwald, Martin Becker, Lars Paulsen, Jacek Rudzki, Holger Ulrich, Ronald Eisele
  • Patent number: 11315813
    Abstract: A substrate holder having a fixing surface for holding a substrate, a system having such a substrate holder, a use of such a substrate holder, a method for bonding two substrates and a product, particularly a substrate stack, produced using such a method and also a use of such a substrate holder for such a method.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: April 26, 2022
    Assignee: EV Group E. Thallner GmbH
    Inventors: Thomas Wagenleitner, Thomas Plach, Jurgen Michael Suss, Jurgen Mallinger
  • Patent number: 11252811
    Abstract: In one embodiment, an apparatus includes a substrate comprising a first surface and a second surface opposite to the first surface, an integrated circuit attached to the first surface of the substrate, and a cold plate attached to the second surface of the substrate with an electrical path extending through the cold plate for transmitting power from a power component connected to the cold plate, to the integrated circuit.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: February 15, 2022
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Joel Richard Goergen, Jessica Kiefer, Ashley Julia Maker Erickson, Yi Tang, M. Baris Dogruoz, Elizabeth Ann Kochuparambil, Shobhana Punjabi
  • Patent number: 11243127
    Abstract: A pressure/force sensor comprises a diaphragm structure including a sensing element and a lead structure extending from the diaphragm structure and including first and second traces electrically coupled to the sensing element. The diaphragm structure and the lead structure include a circuit assembly comprising a common insulating layer and a common conductor layer on the insulating layer. The conductor layer includes at least a portion of the sensing element and at least the first trace.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: February 8, 2022
    Assignee: Hutchinson Technology Incorporated
    Inventors: Michael W. Davis, Peter F. Ladwig, Matthew S. Lang, Dean E. Myers, Clark T. Olsen, Douglas P. Riemer
  • Patent number: 11177149
    Abstract: Disclosed herein is a wafer jig with an identification mark for use in inspecting the function of an identification mark reading mechanism for reading an identification mark on a device wafer. The wafer jig includes a wafer piece cut from a region of a device wafer where an identification mark is formed, and a circular plate having the same diameter as the device wafer. The wafer piece is fixed to the circular plate such that the identification mark on the wafer piece is positionally aligned with the identification mark on the device wafer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: November 16, 2021
    Assignee: DISCO CORPORATION
    Inventor: Zhong Zhou
  • Patent number: 11094559
    Abstract: A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 17, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Mathias Wendt, Andreas Weimar
  • Patent number: 11081253
    Abstract: There is provided an inexpensive silver particle dispersing solution being usable as a slurry for ink jet, a method for producing the same, and a method for producing a conductive film using the silver particle dispersing solution. In a silver particle dispersing solution containing a silver powder and a solvent, the silver powder has an average primary particle diameter (DSEM) of 0.15 to 0.5 ?m, and the ratio (D50/DSEM) of a particle diameter (D50), which corresponds to 50% of accumulation in volume-based cumulative distribution of the silver powder, to the average primary particle diameter (DSEM) is not less than 1.7, the silver powder having a fatty acid adhered to the surface thereof, and the solvent containing a monohydric higher alcohol having a carbon number of 6 to 12, butyl carbitol or butyl carbitol acetate as the main component thereof.
    Type: Grant
    Filed: June 11, 2017
    Date of Patent: August 3, 2021
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Taku Okano, Noriaki Nogami
  • Patent number: 11033990
    Abstract: A method for depositing a material to join two surfaces of an electronic assembly includes determining, using dimensions of a pad area of a substrate, a deposition pattern for the material that extends across the pad area of the substrate. The method further includes creating a tool to deposit the material in the deposition pattern that extends across the pad area of the substrate.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 15, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Sergio V. Martinez, Jeffrey R. Ogorzalek, Patrick J. Lott
  • Patent number: 11000915
    Abstract: In described examples, a transient liquid phase (TLP) metal bonding material includes a first substrate and a base metal layer. The base metal layer is disposed over at least a portion of the first substrate. The base metal has a surface roughness (Ra) of between about 0.001 to 500 nm. Also, the TLP metal bonding material includes a first terminal metal layer that forms an external surface of the TLP metal bonding material. A metal fuse layer is positioned between the base metal layer and the first terminal metal layer. The TLP metal bonding material is stable at room temperature for at least a predetermined period of time.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 11, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: John Charles Ehmke, Simon Joshua Jacobs
  • Patent number: 10964628
    Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 30, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Martin Gruber, Josef Hoeglauer, Michael Juerss, Josef Maerz, Thorsten Meyer, Bun Kian Tay
  • Patent number: 10900847
    Abstract: Thermal pattern sensor comprising several pixels located on a substrate, each pixel comprising a pyroelectric capacitor, the pyroelectric capacitor comprising a pyroelectric material located between two electrically conducting electrodes, the pyroelectric material comprising a sol-gel matrix in which first particles made of a first material and second particles made of a second material are dispersed. The first material being chosen from among calcium, lanthanum, tantalum, barium, lead and/or strontium oxides, the second material being chosen from among titanium, antimony, tin, zinc, gallium, vanadium and/or manganese oxides.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: January 26, 2021
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Mohammed Benwadih, Christine Revenant-Brizard
  • Patent number: 10886250
    Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 5, 2021
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10854574
    Abstract: A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh, Wen-Chih Chiou
  • Patent number: 10790252
    Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Yang Lei, Szu-Yu Yeh, Yu-Ren Chen, Hung-Jui Kuo, Chung-Shi Liu
  • Patent number: 10754070
    Abstract: An optical device includes: a substrate including plural waveguide cores; and an optical component provided on the substrate, the optical component including plural lenses, each of the plural lenses transmitting light passing through one of the corresponding plural waveguide cores on the substrate. The substrate and the optical component are each provided with a positioning structure. The positioning structure includes plural protrusions and plural recesses provided on the substrate and the optical component. Each of the plural recesses accommodates a corresponding one of the plural protrusions, and an outer surface of each of the plural protrusions contacts a positioning surface of a corresponding one of the plural recesses. The positioning surface is a part of an inner surface of each of the plural recesses having accommodated the corresponding one of the plural protrusions to position the plural lenses relative to the substrate.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Koji Masuda, Alexander Janta-Polczynski, Patrick Jacques, Vincent Langlois, Paul Francis Fortier
  • Patent number: 10748836
    Abstract: The semiconductor laser module 1 has an electrically conductive heat sink 10, a submount 20 disposed above the heat sink 10, a semiconductor laser device 30 disposed above the submount 20, a lower solder layer 50 disposed between the heat sink 10 and the submount 20, and an upper solder layer 60 electrically connected to the semiconductor laser device 30 and the heat sink 10. This upper solder layer 60 has an electric resistivity lower than an electric resistivity of the submount 20 and extends along surfaces 21 and 22 of the submount 20 to the heat sink 10.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: August 18, 2020
    Assignee: FUJIKURA LTD.
    Inventor: Yoshikazu Kaifuchi
  • Patent number: 10700250
    Abstract: The present disclosure provides a light emitting diode (LED) package, which ensures the reliability during use while adopting an LED chip of higher output. The LED package includes an LED chip, which has a front and a back facing opposite sides in the thickness direction z, and a first back electrode provided at the back surface; a first terminal in conduction with the first back electrode; and a first bonding layer, configured to bond the first back electrode and the first terminal 201; wherein the composition of the first bonding layer includes a metal eutectic composition containing Au, and when the LED chip is viewed in the thickness direction z, a first bent portion which is recessed toward the inner side of the periphery of the first back electrode is formed in the first bonding layer.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 30, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Yosuke Taka, Tomoichiro Toyama, Junichi Itai
  • Patent number: 10566305
    Abstract: A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: February 18, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Motoharu Haga, Kaoru Yasuda
  • Patent number: 10483185
    Abstract: A semiconductor device includes a semiconductor chip including a substrate and an element region on the substrate, a heat transfer body made of diamond, and a metal layer between the semiconductor chip and the heat transfer body, wherein the substrate includes an amorphous region on a back surface thereof, the amorphous region and the metal layer are bonded to each other, and the metal layer and the heat transfer body are bonded to each other.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto, Toshihiro Ohki
  • Patent number: 10366936
    Abstract: An electronic device component comprising: a support frame comprising a top surface, a bottom surface, and an opening extending between the top surface and bottom surface of the support frame; a diamond heat spreader comprising a wafer of synthetic diamond material having a top face, a bottom face, wherein the diamond heat spreader is bonded to the support frame so that the diamond heat spreader extends across the opening in the support frame; and one or more semiconductor components mounted on, and bonded to, the top face of the diamond heat spreader, wherein the support frame is formed of an electrically insulating ceramic material to which the diamond heat spreader is bonded.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: July 30, 2019
    Assignee: Element Six Technologies Limited
    Inventor: Julian James Sargood Ellis
  • Patent number: 10325838
    Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes placing a first semiconductor chip on a carrier with the first main surface of the first semiconductor chip facing the carrier. A first layer of soft solder material is provided between the first main surface and the carrier. Heat is applied during placing so that a temperature at the first layer of soft solder material is equal to or higher than a melting temperature of the first layer of soft solder material. A second layer of soft solder material is provided between the first contact area and the second main surface. Heat is applied during placing so that a temperature at the second layer of soft solder material is equal to or higher than a melting temperature of the second layer of soft solder material. The first and second layers of soft solder material are cooled to solidify the soft solder materials.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 18, 2019
    Assignee: Infineon Technologies AG
    Inventors: Abdul Rahman Mohamed, Chu Hua Goh
  • Patent number: 10269754
    Abstract: A semiconductor device includes a semiconductor element having first and second main surfaces spaced apart in a thickness direction. The semiconductor element includes a metal underlying layer on the first main surface, a bonding pad on the metal underlying layer with a wire bonded to the pad, and an insulative protection layer formed on the first main surface and surrounding the bonding pad. The bonding pad includes first and second conductive layers. The first conductive layer covers the metal underlying layer and is made of a metal having a lower ionization tendency than the metal underlying layer. The second conductive layer covers the first conductive layer and is made of a metal having a lower ionization tendency than the first conductive layer. The first and second conductive layers have respective peripheries held in close contact with the protection layer and covering a part of the protection layer.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: April 23, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Motoharu Haga, Kaoru Yasuda
  • Patent number: 10091919
    Abstract: An apparatus for securing electronic devices on a carrier for storing electronic devices during transportation of the electronic devices on the carrier has a guiding track for guiding motion of the carrier when the carrier receives electronic devices. A magnetic track located adjacent to the guiding track attracts the electronic devices onto the carrier with a magnetic attraction force. In particular, the magnetic track has a support surface facing the carrier that has a smaller width than a width of a portion of the magnetic track that is spaced from the support surface.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: October 2, 2018
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Yan Yiu Lam, Shing Kai Yip, Yu Sze Cheung
  • Patent number: 10043732
    Abstract: The heat sink is a body or block of solid-phase gallium having a plurality of sealed cavities defined therein containing an unencapsulated phase change material (other than gallium). The solid-phase gallium may be disposed in a container having at least one open face (contact face) adapted for direct contact with the heat source requiring cooling so that the interface between the heat source and the heat sink includes a region of melted gallium for improved heat transfer. Heat from the heat source is rapidly conducted through the region of melted gallium, then through solid-phase gallium, and is absorbed by the phase change material in the cavities without significant change in temperature, maintaining viability of the heat sink. The heat sink may include inclined tubes through the solid-phase body of gallium, the tubes being open at opposite ends for passage of a cooling medium, such as air or cold water.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 7, 2018
    Assignee: UNITED ARAB EMIRATES UNIVERSITY
    Inventors: Salah Addin Burhan Al Omari, Abdallah Ghazal
  • Patent number: 9893002
    Abstract: A terminal structure of a wiring substrate includes a wiring layer, a protective insulation layer including an opening that partially exposes an upper surface of the wiring layer, and a connection terminal formed on the wiring layer. The connection terminal includes a base portion formed in the opening and a connection portion formed on the base portion. The connection portion projects from an upper surface of the protective insulation layer. A gap is formed between a side surface of the base portion and a wall surface of the opening.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 13, 2018
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Tomoyuki Shimodaira
  • Patent number: 9847308
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Ravindranath V. Mahajan
  • Patent number: 9835648
    Abstract: Embodiments of the invention provide methods for forming electrical connections using liquid metals. Electrical connections that employ liquid metals are useful for testing and validation of semiconductor devices. Electrical connections are formed between the probes of a testing interface and the electronic interface of a device under test through a liquid metal region. In embodiments of the invention, liquid metal interconnects are comprised of gallium or liquid metal alloys of gallium. The use of liquid metal contacts does not require a predetermined amount of force be applied in order to reliably make an electrical connection.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 5, 2017
    Assignee: Intel Corporation
    Inventors: Rajashree Baskaran, Kimin Jun, Ting Zhong, Roy E. Swart, Paul B. Fischer
  • Patent number: 9761507
    Abstract: A rectifier package is provided, which comprises a first rectifier die having an anode and a cathode conductively bonded to a first conductive film on a first surface. The rectifier package also comprises a second rectifier die having an anode and a cathode conductively bonded to the first conductive film on a second surface, which is opposite to the first surface. The first conductive film is in contact with both anodes or both cathodes of the first rectifier die and the second rectifier die.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 12, 2017
    Assignee: Diodes Incorporated
    Inventors: Pin-Hao Huang, Tim C. Chen, Yeng-Liang Lin, Bau Shun Huang
  • Patent number: 9741639
    Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1?1 or N1?2 of first partial layers and a number N2?2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 22, 2017
    Assignee: Infineon Technologies AG
    Inventors: Frank Umbach, Niels Oeschler, Kirill Trunov
  • Patent number: 9735117
    Abstract: Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer of an integrated circuit die. In some implementations, a metal layer in ohmic contact with an intrinsic region of a semiconductor substrate can be partially covered by a passivation layer such as a dielectric layer. An interconnect conductor electrically connected to the metal layer can include an extension that covers an edge of the passivation layer to thereby inhibit the edge from lifting up. In some implementations, the metal layer in combination with a contact pad also in ohmic contact with the intrinsic region can yield a conduction path through the intrinsic region during an electrostatic discharge (ESD) event. In such a configuration, the interconnect conductor can route the ESD charge to a ground.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: August 15, 2017
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Kim Rene Smith, Paul T. DiCarlo, Michael David Hill
  • Patent number: 9721913
    Abstract: A semiconductor package comprises a semiconductor chip having an active surface with a conductive pad thereon; an electroplated Au—Sn alloy bump over the active surface; and a (glass) substrate comprising conductive traces electrically coupling with the electroplated Au—Sn alloy bump, wherein the electroplated Au—Sn alloy bump has a composition from about Au0.35Sn0.15 to about Au0.75Sn0.25 in weight percent uniformly distributed from an end in proximity to the active surface to an end in proximity to the substrate. A method of manufacturing a semiconductor package comprises forming patterns of conductive pads on an active surface of a semiconductor chip; electroplating Au—Sn alloy bump over the conductive pads; and bonding the semiconductor chip on a corresponding conductive trace on a substrate by a reflow operation or a thermal press operation.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: August 1, 2017
    Assignee: CHIPMOS TECHNOLOGIES INC
    Inventors: Tung Bao Lu, Heng-Sheng Wang, Tzu-Han Hsu
  • Patent number: 9721919
    Abstract: Solder-bumped semiconductor substrates (e.g., semiconductor wafers) and methods for forming solder bumped semiconductor substrates are provided, in which solder bumps are formed on a semiconductor substrate using preformed solder balls having different compositions and/or sizes. Two or more solder balls masks are successively utilized to place different types of preformed solder balls (differing in composition and/or size) into corresponding cavities of a solder ball fixture, and thereby form an array of different types of preformed solder balls arranged in the solder ball fixture. The array of preformed solder balls in the solder ball fixture are then transferred to corresponding contact pads of a semiconductor substrate (e.g., semiconductor wafer) using a single solder reflow process. This process allows different types of preformed solder bumps to be bonded to a semiconductor substrate at the same time using a single solder reflow process.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventor: Jae-Woong Nah
  • Patent number: 9646945
    Abstract: Provided is a semiconductor device having a high-reliability solder joint. The semiconductor device includes a high-temperature solder formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. An Sn content of the high-temperature solder is higher than that of the low-temperature solder.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soon-Bum Kim, Tae-Eun Kim, Eun-Hye Park
  • Patent number: 9576913
    Abstract: A semiconductor device that improves noise performance includes a circuit substrate, an enclosing case, and a metal part. A control circuit is mounted on the front surface of the circuit substrate. The enclosing case is a resin case in which semiconductor elements are installed. The metal part, included inside the enclosing case, includes a first mounting portion, a second mounting portion, and a bus bar. The first mounting portion mounts the circuit substrate on the enclosing case, and is connected to a ground pattern of the circuit substrate when mounting. The second mounting portion mounts an external instrument on the enclosing case, and is grounded when mounting. The bus bar connects the first mounting portion and second mounting portion.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: February 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 9502376
    Abstract: A method is provided for connecting parts to be joined. A first layer sequence is applied to a first part to be joined. The first layer sequence contains silver. A second layer sequence is applied to a second part to be joined. The second layer sequence contains indium and bismuth. The first layer sequence and the second layer sequence are pressed together at their end faces respectively remote from the first part to be joined and the second part to be joined through application of a joining pressure at a joining temperature which amounts to at most 120° C. for a predetermined joining time. The first layer sequence and the second layer sequence fuse together to form a bonding layer which directly adjoins the first part to be joined and the second part to be joined and the melting temperature of which amounts to at least 260° C.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: November 22, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Andreas Plöβl
  • Patent number: 9484315
    Abstract: A chip structure includes a chip, a first metal layer, a second metal layer and a bonding wire. The first metal layer is disposed on the chip, and a material of the first metal layer includes nickel or nickel alloy. The second metal layer is disposed on the first metal layer, and a material of the second metal layer includes copper, copper alloy, aluminum, aluminum alloy, palladium or palladium alloy. The bonding wire is connected to the second metal layer, and a material of the bonding wire includes copper or copper alloy.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: November 1, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Po-Chen Lin, Jing-Yao Chang
  • Patent number: 9472520
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Patent number: 9443903
    Abstract: A light emitting diode structure includes a diode region and a metal stack on the diode region. The metal stack includes a barrier layer on the diode region and a bonding layer on the barrier layer. The barrier layer is between the bonding layer and the diode region. The bonding layer includes gold, tin and nickel. A weight percentage of tin in the bonding layer is greater than 20 percent and a weight percentage of gold in the bonding layer is less than about 75 percent. A weight percentage of nickel in the bonding layer may be greater than 10 percent.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: September 13, 2016
    Assignee: Cree, Inc.
    Inventors: Michael John Bergmann, Christopher D. Williams, Kevin Shawne Schneider, Kevin Haberern, Matthew Donofrio
  • Patent number: 9436854
    Abstract: A connector module includes a housing and a conductive lead frame. The housing includes a cover and a base that define a cavity therebetween. The cavity receives a circuit card therein. The base has a top side and a bottom side. The top side faces the cover and defines part of the cavity. Multiple windows extend through the base between the top and bottom sides. The base includes a conductive layer at least partially covered by a non-conductive layer. The conductive lead frame is coupled to the bottom side of the base. The lead frame includes multiple contact beams that extend into the cavity through the windows of the base. The lead frame is electrically isolated from the conductive layer of the base by the non-conductive layer of the base. The lead frame further includes mounting contacts configured to be mounted to conductive components of a circuit board.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: September 6, 2016
    Assignee: TYCO ELECTRONICS CORPORATION
    Inventors: David Bruce Sarraf, Charles Malstrom, Mike Laub, Craig M. Campbell
  • Patent number: 9351436
    Abstract: Presented herein are stud bump bonding techniques for electrically connecting an elongate conductor, such as a wire or pin, to a bonding pad. A plurality of stud bumps are bonded to a surface of a bonding pad and an elongate electrical conductor is positioned in proximity to the plurality of stud bumps. The elongate conductor is bonded to one or more of the stud bumps.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: May 24, 2016
    Assignee: Cochlear Limited
    Inventors: Milind Raje, Robert Bennett, Andrew Mudie, Gary Mark Ignacio
  • Patent number: 9343648
    Abstract: The invention relates to a method of manufacturing a thermoelectric device comprising a plurality of thermoelectric components (4) for creating an electric current from a temperature gradient applied between two faces (3a, 3b) thereof. In the method, a thermally conductive support (30) is provided in contact with a hot or cold source, a thermally conductive and electrically insulating material is thermally sprayed on the support (30) to produce a coating (21), and an electrically conductive material is thermally sprayed onto the coating (21) to form electric conduction tracks (22) which are intended to receive the thermoelectric components (4) via the faces (3a, 3b) thereof. The invention also relates to a thermoelectric device obtained by the method.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 17, 2016
    Assignee: VALEO SYSTEMES THERMIQUES
    Inventors: Gerard Gille, Patrick Boisselle
  • Patent number: 9324566
    Abstract: A reactive material stack is formed above a surface of a base substrate. The reactive material stack includes metals which when subjected to heat energy or electrical energy can undergo a solid state reaction that provides an intermetallic compound. The intermetallic compound that forms has a smaller unit volume than the initial reactive material stack and, as such, induces a tensile stress within the base substrate which, in turn, initiates crack formation within the base substrate. This represents an initial stage of spalling. The crack formation can be propagated along a fracture plane within the base substrate by continued spalling.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Jeehwan Kim, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9314862
    Abstract: Systems and methods for evenly applying a flux coating to any number of different shaped parts with a single machine are described. The systems and methods provide advantages in that the flux coating may be applied accurately within 2% to 4% of desired thickness with 85% to 95% of the total yield of flux being applied, this minimizing waste. Thousands of parts may be batch treated with a single machine without operator input.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: April 19, 2016
    Assignee: Lucas-Milhaupt, Inc.
    Inventor: Daniel J. Jossick
  • Patent number: 9301390
    Abstract: The present invention provides a process for producing a metalized substrate in which a predetermined metal paste composition is applied onto a sintered nitride ceramic substrate (10); the resultant is fired in a heat-resistant container at a predetermined condition; and the substrate (10) and a metal layer (30) are bonded together to each other through a titanium nitride layer (20).
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: March 29, 2016
    Assignee: TOKUYAMA CORPORATION
    Inventors: Naoto Takahashi, Yuichiro Minabe
  • Patent number: 9161485
    Abstract: The system contains a lamination press. The first cavity is formed in a chassis. A film assembly is fitted within the chassis. A buffer mounts over the film assembly and within the chassis. A tool set is shaped to fit within the first cavity. The tool set and chassis are positioned within the lamination press to confer heat and pressure from the lamination press to the film assembly and chassis.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: October 13, 2015
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: John W. Lahood, Edward M. Hardy
  • Patent number: 9159660
    Abstract: A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: October 13, 2015
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chin-Tang Hsieh, Chih-Ming Kuo, Chia-Jung Tu, Shih-Chieh Chang, Chih-Hsien Ni, Lung-Hua Ho, Chaun-Yu Wu, Kung-An Lin
  • Patent number: 9126384
    Abstract: A bonded body 10 includes a plate-shaped alumina or aluminum nitride ceramic member 12 and a Mo or Ti terminal 14 having a Ni coating, a Au coating, or a Ni—Au coating (Au on Ni) and joined to a recess 12a in the ceramic member 12 with a joint layer 16 therebetween. The joint layer 16 contains Au, Ge, Ag, Cu, and Ti and is in contact with at least part of the side surfaces (herein the entire side surfaces) and the bottom surface of the recess 12a. Ti is rich in the joint interface between the joint layer 16 and the ceramic member 12. The percentage (porosity) of the sum of the cross-sectional areas of pores to the cross-sectional area of the joint layer 16 in a cross-section taken across the thickness of the bonded body 10 is 0.1% to 15%.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 8, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomoyuki Minami, Tetsuya Kawajiri