Semiconductor-type Nonmetallic Material Patents (Class 228/123.1)
  • Patent number: 6276599
    Abstract: A method of forming solder bumps on pads formed on a surface of a base material includes the steps of supplying solder to a template having a number of through holes formed to correspond to the pads of the base material respectively so that the through holes are filled with the solder, the template having an upper side and an underside, scraping the sides of the template with doctors to remove an excessive amount of solder, and opposing the template to the base material so that the pads are aligned with the through holes respectively, covering the side of the template opposite to the base material with a pressure housing and increasing pressure in an interior of the pressure housing so that a difference in pressure between an exterior and the interior of the pressure housing extrudes the molten solder from the template to the pad side of the base material.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: August 21, 2001
    Assignee: Noda Screen Co., Ltd.
    Inventor: Hirotaka Ogawa
  • Patent number: 6268069
    Abstract: A process is disclosed for producing a joined article between a ceramic member and another member, which process includes the steps of brazing the ceramic member with another member by using a brazing material composed of 50 to 99 wt % of copper, 0.5 to 20 wt % of aluminum, 0.5 to 5 wt % of at least one kind of active metal selected from the group consisting of titanium, zirconium, hafnium, vanadium and niobium, thereby obtaining a joined body including the ceramic member, another member and a layer of the brazing material, and heating the brazing material layer in an oxidative atmosphere.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: July 31, 2001
    Assignee: NGK Insulators, Ltd.
    Inventors: Tsuneaki Ohashi, Tomoyuki Fujii
  • Patent number: 6264093
    Abstract: The present invention provides a method for soldering components to a printed wiring board. In one embodiment, the method comprises applying a substantially lead-free solder to the printed wiring board, placing an electronic component having lead-free terminals on the solder, and heating the printed wiring board in a substantially oxygen-free atmosphere to a temperature sufficient to reflow the solder. In an alternative embodiment, the method may further comprise applying a tin-based solder. In a particularly advantageous embodiment, the method includes applying a solder alloy of tin and a metal selected from the group consisting of: silver, antimony, copper, and gold.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: July 24, 2001
    Inventors: Raymond W. Pilukaitis, Yi T. Shih, Thang D. Truong, William L. Woods
  • Publication number: 20010008247
    Abstract: The invention encompasses a method of forming a semiconductor chip assembly. A substrate is provided. Such substrate has a pair of opposing surfaces and circuitry formed on one of the opposing surfaces. A semiconductor chip is joined to the substrate. The semiconductor chip has bonding regions thereon. A plurality of wires join to the circuitry and extend over the bonding regions of the semiconductor chip. The wires are pressed down to about the bonding regions of the semiconductor chip with a tool. The tool is lifted from the wires, and subsequently the wires are adhered to the bonding regions of the semiconductor chip. The invention also encompasses an apparatus for forming wire bonds from circuitry on a substrate to a semiconductor chip joined to the substrate. Such apparatus comprises a support for supporting the substrate and the semiconductor chip.
    Type: Application
    Filed: March 2, 2001
    Publication date: July 19, 2001
    Inventors: Michael Bettinger, Ronald W. Ellis, Tracy Reynolds
  • Patent number: 6247637
    Abstract: A method of integrated circuit assembly before encapsulation including at least one step of soldering, under mechanical pressure, a first element on a second element, including temporarily maintaining a predetermined spacing, at least partially without solder paste, between the surfaces to be assembled of the first and second elements.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: June 19, 2001
    Assignee: STMicroelectronics S.A.
    Inventor: Jean-Paul Farroni
  • Patent number: 6216941
    Abstract: A method for forming high frequency connections between a fragile chip and a substrate is described, wherein metal is selectively deposited on a surface of a chip and a surface of a substrate, and corresponding patterns of electrically conductive bumps are selectively evaporated on the surface of the chip and the surface of the substrate over the metal layers, to form a pattern of electrically conductive bumps having spongy and dendritic properties, placing the chip in aligned contact with the substrate where each electrically conductive chip bump mates with each corresponding electrically conductive substrate bump, and selectively applying heat and pressure to the chip and substrate causing each chip bump to fuse together with each corresponding substrate bump to form an electromechanical bond.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: April 17, 2001
    Assignee: TRW Inc.
    Inventors: Karen E. Yokoyama, Gershon Akerling, Moshe Sergant
  • Patent number: 6206269
    Abstract: The present invention relates to a method of soldering a semiconductor chip to a substrate, such as to a capsule in an RF-power transistor, for instance. The semiconductor chip is provided with an adhesion layer consisting of a first material composition. A solderable layer consisting of a second material composition is disposed on this adhesion layer. An antioxidation layer consisting of a third material composition is disposed on said solderable layer. The antioxidation layer is coated with a layer of gold-tin solder. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and chip are exposed to an inert environment to which a reducing gas is delivered and the capsule and chip are subjected to a pressure substantially beneath atmospheric pressure whilst the gold-tin solder is heated to a temperature above its melting point.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: March 27, 2001
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Lars-Anders Olofsson
  • Patent number: 6202299
    Abstract: A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: March 20, 2001
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Gus Karavakis, Zlata Kovac, Craig Mitchell
  • Patent number: 6202916
    Abstract: A method and assembly for preserving solder connections of components mounted on a thin laminate circuit board during wave soldering of leaded components to the circuit board. The method generally entails supporting the circuit board on a pallet with pedestals that contact the surface of the circuit board directly opposite surface-mount components on the board. The pallet also includes an access directly opposite leaded components assembled to the board so that their leads are exposed. The pallet and board assembly are then placed on a wave soldering apparatus and wave soldered while applying and maintaining a force to the circuit board that ensures contact between the pedestals and the surface of the board opposite the surface-mount components, so that the leads of the leaded components are soldered to the circuit board.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: March 20, 2001
    Assignee: Delphi Technologies, Inc.
    Inventors: Theresa Ann Updike, Richard Scott King, Michael Thomas Coles
  • Patent number: 6199743
    Abstract: The invention encompasses a method of forming a semiconductor chip assembly. A substrate is provided. Such substrate has a pair of opposing surfaces and circuitry formed on one of the opposing surfaces. A semiconductor chip is joined to the substrate. The semiconductor chip has bonding regions thereon. A plurality of wires join to the circuitry and extend over the bonding regions of the semiconductor chip. The wires are pressed down to about the bonding regions of the semiconductor chip with a tool. The tool is lifted from the wires, and subsequently the wires are adhered to the bonding regions of the semiconductor chip. The invention also encompasses an apparatus for forming wire bonds from circuitry on a substrate to a semiconductor chip joined to the substrate. Such apparatus comprises a support for supporting the substrate and the semiconductor chip.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: March 13, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Michael Bettinger, Ronald W. Ellis, Tracy Reynolds
  • Patent number: 6189767
    Abstract: The invention provides a method of securing an electric contact of a metal to a layer of a sintered thick-film paste which is situated on an electrically insulating substrate. In this method, a layer of a non-sintered thick-film paste is provided, in accordance with a desired pattern, on an electrically insulating substrate. Subsequently, the layer is provided with a, preferably block-shaped, body of metal, such as an NiFe-alloy. Next, the layer of the thick-film paste is subjected to a temperature treatment, thereby forming the layer of the sintered thick-film paste. Finally, an electric contact is secured to the body, preferably by welding. The connections made by means of the method in accordance with the invention proved to be very reliable, both electrically and mechanically. The invention can be very advantageously used in the manufacture of passive elements, such as resistors and inductors, as well as in the manufacture of heating elements.
    Type: Grant
    Filed: October 24, 1997
    Date of Patent: February 20, 2001
    Assignee: U.S. Philips Corporation
    Inventor: Harold R. M. Haspeslagh