Reducing Gas Patents (Class 228/220)
  • Patent number: 11345121
    Abstract: The disclosure provides an aluminized composite including a base material. The aluminized composite may also include a diffusion layer disposed over the base material. The aluminized composite may further include an aluminum material disposed over the diffusion layer.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: May 31, 2022
    Assignee: Apple Inc.
    Inventors: Yoshihiko Yokoyama, Naoto Matsuyuki, James A. Wright, Brian M. Gable, William A. Counts, Eric W. Hamann
  • Patent number: 10144079
    Abstract: Provided is a soldering system that can raise the work efficiency related to the supply of a soldering target and soldering work, while decreasing the oxygen concentration by maintaining high airtightness in a space surrounding the soldering target. A soldering system includes a soldering device and a robot related to the soldering device, in which the soldering device is equipped with a container having an openable lid and accommodating a soldering target, and the robot performs conveying of the soldering target to the soldering device and opening/closing of the lid. In an embodiment of the soldering device, the container is a double structure in which an inner container is accommodated in an outer container, and a first nitrogen supply pipe and second nitrogen supply pipe, which are inert gas supply parts of separate systems, are respectively connected to the inner container and outer container.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: December 4, 2018
    Assignee: FANUC CORPORATION
    Inventor: Tetsuhisa Takazane
  • Patent number: 9362241
    Abstract: A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takaomi Nishi, Takehiko Saito, Katsuhiro Torii
  • Patent number: 9224517
    Abstract: A paste composition for an electrode, the paste composition comprising: phosphorous-containing copper alloy particles in which the content of phosphorous is from 6% by mass to 8% by mass; glass particles; a solvent; and a resin.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: December 29, 2015
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Shuichiro Adachi, Masato Yoshida, Takeshi Nojiri, Mitsunori Iwamuro, Keiko Kizawa, Takuya Aoyagi, Hiroki Yamamoto, Takashi Naito, Takahiko Kato
  • Publication number: 20150093188
    Abstract: The present invention relates to a method for providing a braze alloy layered product comprising the following steps: —applying at least one silicon source and at least one boron source on at least a part of a surface of a substrate, wherein the at least one boron source and the at least one silicon source are oxygen free except for inevitable amounts of contaminating oxygen, and wherein the substrate comprises a parent material having a solidus temperature above 1100° C.; —heating the substrate having the applied boron source and the applied silicon source to a temperature lower than the solidus temperature of the parent material of the substrate; and cooling the substrate having the applied boron source and the applied silicon source, and obtaining the braze alloy layered product. The present invention relates further to a braze alloy layered product, a method for providing a brazed product, a method for providing a coated product, and uses of the braze alloy layered product.
    Type: Application
    Filed: March 27, 2013
    Publication date: April 2, 2015
    Applicant: ALFA LAVAL CORPORATE AB
    Inventors: Per Sjödin, Kristian Walter
  • Publication number: 20150086776
    Abstract: The present invention relates to a blend of at least one boron source and at least one silicon source, wherein the blend comprises boron and silicon in a weight ratio boron to silicon within a range from about 5:100 to about 2:1, wherein silicon and boron are present in the blend in at least 25 wt %, and wherein the at least one boron source and the at least one silicon source are oxygen free except for inevitable amounts of contaminating oxygen, and wherein the blend is a mechanical blend of powders, and wherein particles in the powders have an average particle size less than 250 ?m. The present invention relates further to a composition comprising the blend a substrate applied with the blend, a method for providing a brazed product, and uses.
    Type: Application
    Filed: March 27, 2013
    Publication date: March 26, 2015
    Applicant: ALFA LAVAL CORPORATE AB
    Inventors: Per Sjödin, Kristian Walter
  • Publication number: 20150053389
    Abstract: The present invention relates to a method of brazing articles of stainless steel, which method comprises the following steps: step (i) applying an iron-based brazing filler material to parts of stainless steel; step (ii) optionally assembling the parts; step (iii) heating the parts from step (i) or step (ii) to a temperature of at least about 1000° C. in a non-oxidizing atmosphere, a reducing atmosphere, vacuum or combinations thereof, and heating the parts at the temperature of at least about 1000° C. for at least about 15 minutes; step (iv) providing articles having an average hardness of less than about 600 HV1 of the obtained brazed areas. The present invention relates also to brazed articles of stainless steel.
    Type: Application
    Filed: September 10, 2014
    Publication date: February 26, 2015
    Applicant: Alfa Laval Corporate AB
    Inventors: Per Erik Sjodin, Jens Rassmus
  • Patent number: 8944310
    Abstract: A soldering method achieves little void and good joint condition in soldering an insulated circuit board and a semiconductor chip using a tin-high antimony solder material. A method of manufacturing a semiconductor device includes the steps of preparing a solder plate having a U-shape; mounting the solder plate on a substrate; mounting a semiconductor chip on the solder plate; fusing the solder plate in a reducing gas atmosphere; and reducing a pressure of the reducing gas atmosphere to a pressure lower than the atmospheric pressure when melting the solder plate.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 3, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takeshi Matsushita, Eiji Mochizuki, Tatsuo Nishizawa, Shunsuke Saito
  • Publication number: 20150001282
    Abstract: Provide is an apparatus for thermal melting processes that is capable of directly cooling the process object without requiring a separate cooling plate. The apparatus for thermal melting process according to the present invention is an apparatus 1 for thermal melting process that thermally melts objects 100 including solder in an atmosphere containing carbonic acid vapor, and the hand part 4 for carrying and transferring the thermally melted process objects 100 is used as a cooling plate as well.
    Type: Application
    Filed: September 12, 2014
    Publication date: January 1, 2015
    Applicant: AYUMI INDUSTRY CO., LTD.
    Inventor: Hideyuki Abe
  • Publication number: 20140374470
    Abstract: Provided is a soldering method through nickel plating layer to reduce void occurrence rate and a method of manufacturing semiconductor device by using the soldering method. By heating a copper base plate having a nickel plating layer at a temperature range of 300° C. to 400° C. in an inert gas atmosphere beforehand, void occurrence rate can be reduced in soldering the copper base plate to an insulating circuit board.
    Type: Application
    Filed: June 11, 2014
    Publication date: December 25, 2014
    Inventor: Akira ISO
  • Publication number: 20140193658
    Abstract: Methods and apparatus are provided for attaching a heat spreader to a die and includes disposing a solder thermal interface material between a first surface of a die and a first surface of a heat spreader without disposing a liquid flux between the die and the heat spreader to form an assembly, wherein at least one of the first surface of the die and a first surface of the heat spreader have disposed thereon a metallization structure comprising a transition layer and a sacrificial metallization layer, the sacrificial metallization layer disposed as an outer layer to the metallization structure adjacent the solder thermal interface material; and heating the assembly to melt the thermal interface and attach the die to the heat spreader.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 10, 2014
    Applicant: Indium Corporation
    Inventors: Jordan Peter Ross, Amanda Hartnett, Robert Norman Jarrett
  • Patent number: 8757474
    Abstract: A soldering method capable of alleviating positional displacement between substrates even though a step of removing flux can be omitted is provided. A temporary bonding agent 55 is applied onto multiple substrates 50a, 50b, and a heater 33 heats the substrates while the substrates are temporarily bonded with the temporary bonding agent 55 interposed therebetween, and before the solder 54 is melted or while the solder 54 is melted, the temporary bonding agent 55 is evaporated, and the substrates 50a, 50b are bonded with solder with the melted solder 54 interposed therebetween.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: June 24, 2014
    Assignee: Ayumi Industry Co., Ltd.
    Inventors: Hideyuki Abe, Kazuaki Mawatari
  • Patent number: 8561880
    Abstract: A process and tools for forming and/or releasing metal preforms, metal shapes and solder balls is described incorporating flexible molds or sheets, injection molded metal such as solder and in the case of solder balls, a liquid or gaseous environment to reduce or remove metal oxides prior to or during metal (solder) reflow to increase surface tension to form spherical or substantially spherical solder-balls.
    Type: Grant
    Filed: February 11, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Peter Alfred Gruber, Paul Alfred Lauro, Jae-Woong Nah
  • Patent number: 8490857
    Abstract: A reflow apparatus, where formic acid is used for cleaning a surface of a solder electrode on a processing target, is disclosed. The reflow apparatus includes a processing chamber, a formic acid introduction mechanism for supplying an atmosphere gas containing formic acid to the processing chamber, and a shielding member that is made of a material having corrosion resistance against formic acid. The shielding member is arranged between a reflow processing section of the processing chamber and an inner wall of the processing chamber. In place of or in addition to the shielding member, the reflow apparatus may include a heater for decomposing residual formic acid.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: July 23, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Matsui, Hirohisa Matsuki, Koki Otake
  • Patent number: 8342385
    Abstract: A transfer process for bonding a solderable device to a solderable firsl substrate having a first oxidized surface comprises placing the solderable device proximate to the first substrate in a reducing chamber, where the first surface cannot be visually observed. We place a second substrate having a second oxidized surface in the chamber in a way to visually observe the second surface. Selecting the first substrate and the second substrate so that the reduction of the second surface correlates with the reduction of the first surface provides an indication of the degree of reduction of the first surface. Introducing a reducing agent into the chamber under reducing conditions reduces the surfaces which we track by irradiating and observing the second surface; evaluate any change in the second surface during irradiation and correlate the change with first surface reduction. When sufficiently reduced, we solder the first substrate to the device.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Raymond R. Horton, Robert J. Polastre
  • Patent number: 8336756
    Abstract: A reflow apparatus, where formic acid is used for cleaning a surface of a solder electrode on a processing target, is disclosed. The reflow apparatus includes a processing chamber, a formic acid introduction mechanism for supplying an atmosphere gas containing formic acid to the processing chamber, and a shielding member that is made of a material having corrosion resistance against formic acid. The shielding member is arranged between a reflow processing section of the processing chamber and an inner wall of the processing chamber. In place of or in addition to the shielding member, the reflow apparatus may include a heater for decomposing residual formic acid.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Matsui, Hirohisa Matsuki, Koki Otake
  • Patent number: 8302843
    Abstract: A process for producing a semiconductor device, includes: first melting by heating only a superior portion of a bump formed on an electrode on one principle surface of a semiconductor substrate; and second melting the entire bump by also heating an inferior portion of the bump.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 6, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Matsui, Yutaka Makino, Yoshito Akutagawa
  • Publication number: 20110250465
    Abstract: The present invention relates to the development of variants of multilayer structural materials with enhanced corrosion resistance, including successively connected outer main layers which directly contact corrosive operating environments on one or both sides of the multilayer material and, disposed therebetween, alternating internal main and internal sacrificial layers. The main layers are made of metallic materials which are characterized by a state of passivity over a prolonged period with subsequent development therein of pitting-type corrosion, while the internal sacrificial layers, which contact the corrosive operating environment as deep foci of pitting corrosion develop in the preceding outer and internal main layers, are characterized by the development of general corrosion and have a protective action in relation to the outer and internal main layers. Methods for preparing such materials are proposed.
    Type: Application
    Filed: September 26, 2008
    Publication date: October 13, 2011
    Inventors: Andrei Evgenievich Rozen, Irina Sergeevna Los, Leonid Borisovich Pervukhin, Jury Petrovich Perelygin, Jury Alexandrovich Gordopolov, Olga Leonidovna Pervukhina, Gennady Vladimirovich Kiry, Pavel Ivanovich Abramov, Sergei Gennadievich Usaty, Dmitry Borisovich Kryukov, Igor Vladimirovich Denisov, Andrei Andreevich Rozen
  • Patent number: 7845546
    Abstract: Method for producing a vacuum measuring cell having a pressure transducer diaphragm with housing plates sealed on opposite sides to form reference and measuring vacuum chambers. An opening in one plate communicates with the measuring vacuum chamber and has a sealed connection for joining to medium to be measured. The diaphragm and plates are aluminum oxide ceramic and at least one of the seals is aluminum with a thickness of 0.5 ?m to 30 ?m. The ceramic parts are pressed together at increased temperature of 600° C. to 680° C. in a process gas atmosphere including a reducing gas, during a time of 30 to 90 minutes, and subsequently a tempering step is carried out in a second process gas atmosphere including oxygen, tempering taking place at a temperature of 450° C. to 575° C. such that the metallic aluminum is oxidized into aluminum oxide.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: December 7, 2010
    Assignee: Inficon GmbH
    Inventors: Dietmar Bertsch, Klaus Dietrich, Nico Onda, Martin Wüest
  • Publication number: 20100215983
    Abstract: The present invention discloses abrasion resistant claddings for cast iron substrates comprising hard particles and nickel-based braze alloys. The cladding material can be brazed on cast iron substrates at lower temperatures than conventional cladding materials, providing highly increased abrasion resistance to the cast iron substrate materials without adversely affecting the physical properties and structural integrity of such substrates.
    Type: Application
    Filed: February 20, 2009
    Publication date: August 26, 2010
    Applicant: Kennametal Inc.
    Inventors: Vaishalibahen Bhagwanbhai Patel, James Aaron Faust
  • Publication number: 20100213247
    Abstract: The invention relates to a coated boron or nitrogen containing superhard abrasive material selected from cBN, boron suboxide and boron carbide comprising: cBN, boron suboxide and/or boron carbide superhard abrasive material substrate; a primary layer of a carbide/nitride/boride forming metal, such metal preferably being Ti and preferably being substantially in the form of the carbide, nitride or boride; a secondary layer of a high melting point metal selected from W, Mo, Cr, Ni, Ta, Au, Pt, Pd and alloys thereof; and an overcoat of Ag, Ni, Cu, Au, Pd, Pt, Rh, Os, Ir, Re, combinations and alloys thereof such as bronze (Cu/Sn), silver/bronze and silver/tin, the metal of the secondary layer being different to the metal of the overcoat. The invention further relates to methods for the manufacture of such material, use of such materials in tools and tools including such material.
    Type: Application
    Filed: May 22, 2008
    Publication date: August 26, 2010
    Inventors: David Patrick Egan, Kieran Greene
  • Publication number: 20100170939
    Abstract: A joining method includes melting a hot melt joining material provided between a board and a component to be joined to the board; and reducing the pressure of the ambient atmosphere of the hot melt joining material and tilting the board while the hot melt joining material is in a molten state.
    Type: Application
    Filed: December 21, 2009
    Publication date: July 8, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuji ISHIKAWA
  • Publication number: 20100078464
    Abstract: A wire bonding apparatus including a capillary having a through-hole through which a wire is inserted; an inert gas feed section for feeding inert gas containing reducing gas to a region on the tip end side of the bonding tool; and a gas blowing nozzle for blowing out inert gas containing reducing gas along a base end surface of the capillary including an opening of the through-hole. The pressure in the through-hole is made lower than the ambient pressure by the gas blown out of the gas blowing nozzle toward the opening of the base end of the capillary, so that the inert gas containing reducing gas blown out of the inert gas feed section flows through the tip end into the through-hole, thus preventing oxidation of the part of the wire inside the through-hole of the capillary.
    Type: Application
    Filed: October 1, 2008
    Publication date: April 1, 2010
    Inventor: Shinichi Nishiura
  • Publication number: 20100055495
    Abstract: The present invention relates to a brazing material comprising an alloy containing essentially of: 15 to 30 wt % chromium (Cr); 0.1 to 5.0 wt % manganese (Mn); 9 to 20 wt % nickel (Ni); 0 to 4.0 wt % molybdenum (Mo); 0 to 1.0 wt % nitrogen (N); 1.0 to 7.0 wt % silicone (Si); 0 to 0.2 wt % boron (B); 1.0 to 7.0 wt % phosphorus (P); optionally 0.0 to 2.5 wt % of each of one or more of elements selected from the group consisting of vanadium (V), titanium (Ti), tungsten (W), aluminum (Al), niobium (Nb), hafnium (Hf) and tantalum (Ta); the alloy being balanced with Fe, and small inevitable amounts of contaminating elements; and wherein Si and P are in amounts effective to lower melting temperature. The present invention relates further to a method of brazing, a product brazed with the brazing material.
    Type: Application
    Filed: November 14, 2007
    Publication date: March 4, 2010
    Applicant: ALFA LAVAL CORPORATE AB
    Inventor: Per Sjödin
  • Patent number: 7658313
    Abstract: A ball forming device and method used in a bonding apparatus, including a bonding arm, a capillary attached to the bonding arm, an electronic flame off prove for forming a ball at the tip of a wire passing through the capillary, and a gas atmosphere forming unit for bringing the vicinity of the tip end of the wire into a gas atmosphere. The gas atmosphere forming unit is made of an inner wall element and an outer wall element with a hollow space section in between. The bonding arm side of the inner wall element has an inside open space which is wider than the portion of the bonding arm where the capillary is attached, and gas ejection ports are formed in the inner wall element. A gas supply pipe is connected to the outer wall element to supply, for instance, a reducing gas into the hollow space section.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: February 9, 2010
    Assignee: Kabushiki Kaisha Shinkawa
    Inventors: Shinichi Nishiura, Fumio Miyano
  • Patent number: 7644852
    Abstract: A ball forming device and method used in a bonding apparatus, including a bonding arm, a capillary attached to the bonding arm, an electronic flame off probe for forming a ball at the tip of a wire passing through the capillary, and a gas atmosphere forming unit for bringing the vicinity of the tip end of the wire into a gas atmosphere. The gas atmosphere forming unit is made of an inner wall element and an outer wall element with a hollow space section in between. The bonding arm side of the inner wall element has an inside open space which is wider than the portion of the bonding arm where the capillary is attached, and gas ejection ports are formed in the inner wall element. A gas supply pipe is connected to the outer wall element to supply, for instance, a reducing gas into the hollow space section.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: January 12, 2010
    Assignee: Kabushiki Kaisha Shinkawa
    Inventors: Shinichi Nishiura, Fumio Miyano, Masayuki Horino
  • Patent number: 7611041
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: November 3, 2009
    Assignee: NEC Corporation
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Patent number: 7556189
    Abstract: Nano-structured interconnect formation and a reworkable bonding process using solder films. Large area fabrication of nano-structured interconnects is demonstrated at a very fine pitch. This technology can be used for pushing the limits of current flip chip bonding in terms of pitch, number of I/Os, superior combination of electrical and mechanical properties as well as reworkability. Sol-gel and electroless processes were developed to demonstrate film bonding interfaces between metallic pads and nano interconnects. Solution-derived nano-solder technology is an attractive low-cost method for several applications such as MEMS hermetic packaging, compliant interconnect bonding and bump-less nano-interconnects.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: July 7, 2009
    Assignee: Georgia Tech Research Corporation
    Inventors: Ankur Aggarwal, Isaac Robin Abothu, Pulugurtha Markondeya Raj, Rao R. Tummala
  • Patent number: 7434719
    Abstract: A method of detecting and calibrating dry fluxing metal surfaces of one or more components to be soldered by electron attachment using a gas mixture of reducing gas comprising hydrogen and deuterium, comprising the steps of: a) providing one or more components to be soldered which are connected to a first electrode as a target assembly; b) providing a second electrode adjacent the target assembly; c) providing a gas mixture comprising a reducing gas comprising hydrogen and deuterium between the first and second electrodes; d) providing a direct current (DC) voltage to the first and second electrodes to form an emission current between the electrodes and donating electrons to the reducing gas to form negatively charged ionic reducing gas and molecules of hydrogen bonded to deuterium; e) contacting the target assembly with the negatively charged ionic reducing gas and reducing oxides on the target assembly. Related apparatus is also disclosed.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: October 14, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Chun Christine Dong, Eugene Joseph Karwacki, Jr., Richard E. Patrick
  • Patent number: 7413109
    Abstract: A method for utilizing superplastic deformation with or without a novel joint compound that leads to the joining of advanced ceramic materials, intermetallics, and cermets. A joint formed by this approach is as strong as or stronger than the materials joined. The method does not require elaborate surface preparation or application techniques.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: August 19, 2008
    Assignee: UChicago Argonne, LLC
    Inventors: Kenneth C. Goretta, Jules L. Routbort, Felipe Gutierrez-Mora
  • Patent number: 7353982
    Abstract: This invention relates to a method of bonding a metallic membrane with metallic part involving pressing a smooth surface of the metallic membrane against the smooth surface of the metallic part, and heating the metallic membrane and metallic part to a temperature above the half melting point of the metallic membrane while subjecting the metallic membrane and metallic part to a controlled environment of a proper gas atmosphere. The metallic membrane can comprise palladium and the pressurized gas can comprise one of hydrogen, an inert gas or their mixture.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: April 8, 2008
    Assignee: Membrane Reactor Technologies Ltd.
    Inventor: Anwu Li
  • Patent number: 7347355
    Abstract: A method for brazing two or more of stainless steel components for use in medical equipment, in which one component is joined to other component using a brazing material containing Au of which amount is 62.5 wt % or higher, the method comprising the steps of: a first step in which the components are subjected to a heat treatment at a temperature of 1,050 to 1,200° C. in a hydrogen containing atmosphere or in a vacuum; a second step in which one of the components is allowed to close to the other component so as to form a gap therebetween; and a third step in which the brazing material in a molten state is supplied into the gap to join the components together to manufacture a metal assembly. The joint portions formed in the metal assembly have excellent chemical resistance and corrosion resistance, and thus the metal assembly is suitably used in an endoscope.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: March 25, 2008
    Assignees: PENTAX Corporation, Shinwa Heat Treatment Co., Ltd.
    Inventors: Yasuyuki Sato, Yoshihiro Obata, Wataru Murai, Ryoji Tokieda, Naoki Kamiya, Hideo Shimizu
  • Patent number: 7328830
    Abstract: An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 12, 2008
    Assignee: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant
  • Publication number: 20070193026
    Abstract: This invention is directed to a method of forming electrical conductors comprised of conductive metals generally carried on a substrate. In the method, a conductor formulation generally comprised of metal particles or metal precursor or mixture thereof, typically in the form of an ink or paste, is applied to the substrate and converted into a conductive metal by application of sufficient heat and for a sufficient time to effect sintering thereof while in the presence of a negatively charged ionic reducing gas.
    Type: Application
    Filed: July 6, 2006
    Publication date: August 23, 2007
    Inventors: Chun Christine Dong, Eugene Joseph Karwacki, Richard E. Patrick, David Allen Roberts, Robert Krantz Pinschmidt, John Anthony Thomas Norman, John Christopher Ivankovits
  • Patent number: 7181821
    Abstract: A method of joining expandable tubulars includes joining the tubulars by forge welding and flushing a reducing flushing gas around the heated tubular ends during at least part of the forge welding operation such that oxides are removed from the forge welded tubular ends and the amount of irregularities between the forge welded tubular ends is limited.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: February 27, 2007
    Assignee: Shell Oil Company
    Inventors: Mark Wilson Anderson, Johannis Josephus Den Boer, Anthony Thomas Cole, Klisthenis Dimitriadis, Jan Erik Vollebregt, Djurre Hans Zijsling
  • Patent number: 7134199
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: November 14, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
  • Patent number: 7128980
    Abstract: A highly heat-resistant laminated component for a fusion reactor has at least of a plasma-facing area made of tungsten or a tungsten alloy, a heat-dissipating area of copper or a copper alloy with a mean grain size of more than 100 ?m, and an interlayer of a refractory metal-copper-composite. The refractory metal-copper-composite has a macroscopically uniform copper and refractory-metal concentration progression and a refractory metal concentration of between 10 vol. % and 40 vol. % over its entire thickness.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: October 31, 2006
    Assignee: Plansee SE
    Inventors: Bertram Schedler, Thomas Granzer, Thomas Huber, Karlheinz Scheiber, Dietmar Schedle, Hans-Dieter Friedle, Thomas Friedrich, Anton Zabernig
  • Patent number: 7021521
    Abstract: A bump connection is formed by stacking at least two metallic balls of different kinds of metals on a conductor of an electronic component such as a semiconductor device. The bump connection is obtained by forming the metallic balls using metallic wires. An apparatus for forming the connection includes a support, capillary member for having a wire pass therethrough, a pair of clamps for clamping the wire, and a “torch” (e.g., electrode, gas flame) which heats the tip of the wire, forming the ball. Successive balls can be formed by this apparatus atop the initially formed ball to provide a stacked configuration.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: April 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Sakurai, Keizo Sakurai
  • Patent number: 6905063
    Abstract: A semiconductor device can be formed with fewer voids in the solder bonding a laminate of a silicon chip, an insulator substrate, and a metal base, with a solder layer positioned between the layers. After placing the laminate in a furnace, it is evacuated and then pressurized with hydrogen gas, and then heated to melt the solder. While maintaining the heat, the furnace is again evacuated to remove voids in the solder, and then the furnace is positively pressurized again with hydrogen gas to prevent holes produced by the voids traveling in the solder, and to obtain a uniform solder fillet shape. Thereafter the laminate is rapidly cooled to obtain a finer grain solder to increase the rate of creep to quickly remove the warping of the laminate to the original state.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: June 14, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akira Morozumi, Tadashi Miyasaka, Katsumi Yamada, Eiji Mochizuki
  • Patent number: 6805279
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4, SF4, and H2 and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: October 19, 2004
    Assignee: Taiwan SEmiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yeng-Ming Chen, Kai-Ming Chin, Li-Chi Chen, Hao-Chih Tien
  • Publication number: 20040182915
    Abstract: An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.
    Type: Application
    Filed: December 19, 2003
    Publication date: September 23, 2004
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant
  • Patent number: 6776330
    Abstract: A method of dry fluxing metal surfaces of one or more components to be soldered, comprising the steps of: a) providing one or more components to be soldered which are connected to a first electrode as a target assembly; b) providing a second electrode adjacent the target assembly; c) providing a gas mixture comprising a reducing gas between the first and second electrodes; d) providing a direct current (DC) voltage to the first and second electrodes and donating electrons to the reducing gas to form negatively charged ionic reducing gas; e) contacting the target assembly with the negatively charged ionic reducing gas and reducing oxides on the target assembly.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: August 17, 2004
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Chun Christine Dong, Wayne Thomas McDermott, Richard E. Patrick, Brenda F. Ross
  • Patent number: 6742702
    Abstract: After a reducing gas is mixed with an inert gas by a mixer, a resultant mixed gas is heated by a heater and made to a hot mixed gas which is dehumidified and dried and the temperature of which is increased. The mixed gas is injected to a subject from an injection port formed in a soldering iron, and thereby soldering is performed by heating and melting solder with the soldering iron in the atmosphere of the mixed gas.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: June 1, 2004
    Assignee: Japan Unix Co., Ltd.
    Inventor: Shigeru Abe
  • Patent number: 6739204
    Abstract: Velocity/flow measuring of purge gas when welding pipe, is accomplished by providing a controllably fixed orifice at the distal end of the pipe being welded. The purge gas passes through a pressure regulator, a flow meter, and a purifier. An isolation/control valve is used to control access to the purge gas. The purge gas then passes through a header connected to the input end of the first pipe. A second pipe is positioned adjacent to the first pipe. A pressure clamp, tape or other sealing means seals the circumferential weld area between the first pipe and the second pipe. A second pressure gauge monitors the gas pressure at the pressure clamp. The purge gas passes through the weld area, to a manifold in fluid communication with a first pressure gauge, a back pressure control means and to a weld purge orifice fitting, having a selected orifice size.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: May 25, 2004
    Inventor: Byron Barefoot
  • Patent number: 6712260
    Abstract: A method of forming reflowed bumps comprising the following sequential steps. A wafer is provided. A series of spaced initial bumps is formed upon the wafer. The initial bumps having exposed side walls and top surfaces and organic residue over the initial bump side walls and/or the initial bump top surfaces. The organic residue is simultaneously removed from the initial bump side walls and top surfaces with the forming a surface oxide layer over the initial bump side walls and top surfaces. The surface oxide layer is stripped from the initial bump top surfaces and an upper portion of the initial bump side walls to form partially exposed bumps. The partially exposed bumps are heat treated to melt the partially exposed bumps to form the reflowed bumps.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: March 30, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Wen-Chang Kuo, Chia-Fu Lin, Sheng-Liang Pan, Szu-Yao Wang, Cheng-Yu Chu
  • Publication number: 20040000580
    Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4, SF4, and H2 and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yeng-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Hao-Chih Tien
  • Publication number: 20030178474
    Abstract: A method for assembling chips onto substrates includes applying a flux-free, no-flow underfill material. In an embodiment, the method includes removing oxide from interconnects without the use of a flux and applying a flux-free, no-flow underfill. In an embodiment, the method includes removing oxide from bumps, applying no-flow underfill to a substrate, and fluxlessly connecting the bumps to pads on the substrate. In an embodiment, oxide is removed from the bumps by a plasma treatment. In an embodiment, oxide is removed from the bumps by a subjecting the bumps to an oxide reduction process. The assembly of the chips and substrate is free from flux residue and/or flux cleaning solution residue.
    Type: Application
    Filed: March 25, 2002
    Publication date: September 25, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Tsuyoshi Yamashita
  • Publication number: 20030127498
    Abstract: After a reducing gas is mixed with an inert gas by a mixer, a resultant mixed gas is heated by a heater and made to a hot mixed gas which is dehumidified and dried and the temperature of which is increased. The mixed gas is injected to a subject from an injection port formed in a soldering iron, and thereby soldering is performed by heating and melting solder with the soldering iron in the atmosphere of the mixed gas.
    Type: Application
    Filed: January 7, 2002
    Publication date: July 10, 2003
    Applicant: Japan Unix Co., Ltd.
    Inventor: Shigeru Abe
  • Publication number: 20030047591
    Abstract: The present invention is a method of dry fluxing metal surfaces of one or more components to be soldered, comprising the steps of: a) providing one or more components to be soldered which are connected to a first electrode as a target assembly; b) providing a second electrode adjacent the target assembly; c) providing a gas mixture comprising a reducing gas between the first and second electrodes; d) providing a direct current (DC) voltage to the first and second electrodes and donating electrons to the reducing gas to form negatively charged ionic reducing gas; e) contacting the target assembly with the negatively charged ionic reducing gas and reducing oxides on the target assembly.
    Type: Application
    Filed: September 10, 2001
    Publication date: March 13, 2003
    Inventors: Chun Christine Dong, Wayne Thomas McDermott, Richard E. Patrick, Brenda F. Ross
  • Publication number: 20020092898
    Abstract: A process for connecting a winding wire of a coil with a terminal pin of a casing for surface mounting is introduced, whereby one end section of the winding wire is wound around the terminal pin. The area of the terminal pin wound with the end section of the winding wire is soft-soldered, and the soft-solder is then blown off of the partial area of the area wound, which forms the soldering application surface for surface mounting. The inventive process can be used in the manufacture of inductive SMD components, the terminal pins of which possess excellent coplanarity, particularly if terminal pins bent in a wing-shape are used.
    Type: Application
    Filed: November 2, 2001
    Publication date: July 18, 2002
    Inventors: Dieter Proksch, Norbert Nykrake, Dietmar Tempel, Harald Hundt