Abstract: A multiplying method with a negative/positive symmetrical round-off function and circuitry therefor are disclosed. When a product is positive, a value having a (logical) ONE at the uppermost one of bits to be rounded and ZEROs at the lower bits is rounded up. When a product is negative, a value having a (logical) ONE at the uppermost one of bits to be rounded and ZEROs at the lower bits is rounded down. This rounds off the product such that a mean accumulative error when the product is positive and a mean cumulative error when it is negative cancel each other. When a product is positive, a correction term having a ONE at the uppermost one of the bits to be rounded and ZEROs at the lower bits is applied to a subproduct adder and an adder. For a negative product, the correction term has a ZERO at the above uppermost bit and ZEROs at the lower bits.