Abstract: A method is provided for modifying a strain state of a block of a semiconducting material including steps in the following order: a) making a lower region of the block of the semiconducting material resting on a substrate amorphous, while a crystalline structure of an upper region of the block in contact with the lower region is maintained, then b) forming a stressing zone on the block of the semiconducting material, then c) making at least one creep annealing with a suitable duration and temperature to enable creep of the lower region without recrystallizing a material of the lower region, and then d) making at least one recrystallization annealing of the lower region of the block.

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Abstract: A stacked, monolithic, upright metamorphic, terrestrial concentrator solar cell having exactly five subcells and having a metamorphic buffer, wherein a first subcell has a first lattice constant G1 and consists essentially of germanium, a second subcell has a second lattice constant and GaInAs, a third subcell has the second lattice constant G2 and AlGaInAs, a fourth subcell has the second lattice constant G2 and InP, a fifth subcell has the second lattice constant G2 and InP, G1<G2 applies to the lattice constants, the metamorphic buffer is arranged between the first subcell and the second subcell and has the first lattice constant G1 on a bottom side facing the first subcell and the second lattice constant G2 on a top side facing the second subcell, and all of the semiconductor layers of the concentrator solar cell arranged above the first subcell are epitaxially produced on the preceding subcell.

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

Abstract: A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

Abstract: A ferromagnetic layer is capped with a metallic oxide (or nitride) layer that provides a perpendicular-to-plane magnetic anisotropy to the layer. The surface of the ferromagnetic layer is treated with a plasma to prevent diffusion of oxygen (or nitrogen) into the layer interior. An exemplary metallic oxide layer is formed as a layer of metallic Mg that is plasma treated to reduce its grain size and enhance the diffusivity of oxygen into its interior. Then the plasma treated Mg layer is naturally oxidized and, optionally, is again plasma treated to reduce its thickness and remove the oxygen rich upper surface.

Abstract: Terahertz device includes first resin layer, columnar conductor, wiring layer, terahertz element, second resin layer, and external electrode. Resin layer includes first resin layer obverse face and first resin layer reverse face. Columnar conductor includes first conductor obverse face and first conductor reverse face, penetrating first resin layer in z-direction. Wiring layer spans between first resin layer obverse face and first conductor obverse face. Terahertz element includes element obverse face and element reverse face, and converts between terahertz wave and electric energy. Second resin layer includes second resin layer obverse face and second resin layer reverse face, and covers wiring layer and terahertz element. External electrode, disposed offset in a direction first resin layer reverse face faces with respect to first resin layer, is electrically connected to columnar conductor. Terahertz element is conductively bonded to wiring layer.

Abstract: A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

Abstract: The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

Abstract: A device includes a diode that includes a first group III-nitride (III-N) material and a transistor adjacent to the diode, where the transistor includes the first III-N material. The diode includes a second III-N material, a third III-N material between the first III-N material and the second III-N material, a first terminal including a metal in contact with the third III-N material, a second terminal coupled to the first terminal through the first group III-N material. The device further includes a transistor structure, adjacent to the diode structure. The transistor structure includes the first, second, and third III-N materials, a source and drain, a gate electrode and a gate dielectric between the gate electrode and each of the first, second and third III-N materials.

Abstract: A vertical-cavity surface-emitting laser device including a lower mirror, an upper mirror disposed over the lower mirror, an active region disposed between the lower mirror and the upper mirror, a lower n-type cladding layer disposed between the active region and the lower mirror, an upper n-type cladding layer disposed between the active region and the upper mirror, a heavily doped p-type semiconductor layer disposed between the active region and the upper n-type cladding layer, and a heavily doped n-type semiconductor layer disposed between the heavily doped p-type semiconductor layer and the upper n-type cladding layer to form a tunnel junction with the heavily doped p-type semiconductor layer.

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

Abstract: A semiconductor structure, the semiconductor structure including a channel connecting a source on the semiconductor substrate and a drain on the semiconductor substrate, wherein the channel comprises a plasmonic resonator. A sensor including a plasmonic film, wherein the plasmonic film includes a sensitivity to a known analyte, a semiconductor structure including a source and a drain of a field effect transistor, and an electrical connection between the plasmonic film and a gate of the semiconductor structure. A method of forming a sensor including forming a field effect transistor (“FET”) on a semiconductor substrate, the field effect transistor including a source, a drain, and a gate, where the gate includes a plasmonic resonator.

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

Abstract: Embodiments relate to an apparatus for nano-scale energy converters and electric power generators. The apparatus include two electrodes with a cavity formed therebetween. The first electrode is an emitter electrode that includes a first base material with a first work function value. A second material is deposited on the first base material to modify the first work function value to a second work function value. The second electrode is a collector electrode that includes a second base material with a third work function value. A fourth material is deposited on the second base material to modify the third work function value to a fourth work function value. The emitter and collector electrodes are designed such that the second work function value is greater than the fourth work function value.

Abstract: The present invention relates to a vertical cavity surface emitting laser (VCSEL) and a manufacturing method thereof, and more specifically, to a high-efficiency oxide VCSEL which emits laser beams having a peak wavelength of 860 nm, and a manufacturing method thereof.

Abstract: The thermal impedance of p-i-n diodes integrated on semiconductor-on-insulator substrates can be reduced with thermally conducting vias that shunt heat across thermal barriers such as, e.g., the thick top oxide cladding often encapsulating the p-i-n diode. In various embodiments, one or more thermally conducting vias extend from a top surface of the intrinsic diode layer to a metal structure connected to the doped top layer of the diode, and/or from that metal structure down to at least the semiconductor device layer of the substrate.

Abstract: An input device includes a first substrate, a first light-emitting element unit, and a third electrode unit. The first substrate has a first surface and a second surface. The first light-emitting element includes a first electrode unit formed on the second surface, a second electrode unit formed in a layer different from that of the first electrode unit, and a luminescent layer electrically in contact with at least a part of the first electrode unit and a part of the second electrode unit, and formed between the first electrode unit and the second electrode unit. The third electrode unit is insulated from the first electrode unit and detects a change in an electric field between the first electrode unit and the third electrode unit depending on coordinates of a proximity object present at a position overlapping with the first surface in planar view.

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

Abstract: A semiconductor device is provided, including: a semiconductor substrate having an active area and an edge termination region; an upper electrode; an insulating film provided between the semiconductor substrate and the upper electrode and having a contact hole; a first conductivity-type drift region; a second conductivity-type base region; a second conductivity-type well region; and a second conductivity-type extension region formed extending in a direction toward the well region from the base region and separated from the upper electrode by the insulating film, wherein a sum of a first distance from an end portion of the contact hole closer to the well region to an end portion of the extension region closer to the well region and a second distance from the end portion of the extension region closer to the well region to the well region is smaller than a thickness of the semiconductor substrate in the active area.

Abstract: A high electron mobility transistor includes a III-V compound layer, a nitride layer, a source electrode, a drain electrode, a gate electrode, a surface plasma treatment region, and at least one moat. The nitride layer is disposed on the III-V compound layer. The source and the drain electrodes are disposed above the III-V compound layer. The gate electrode is disposed above the nitride layer. The moat is at least partially disposed in the nitride layer and between the source and the drain electrodes. The surface plasma treatment region is at least partially disposed in the nitride layer. The surface plasma treatment region is at least partially disposed at a top surface of the nitride layer between the moat and the drain electrode, a top surface of the nitride layer between the moat and the source electrode, and/or a top surface of the nitride layer under the moat.

Abstract: Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Abstract: A group III nitride based laser light emitting device includes an n-side group III nitride based semiconductor region, a p-side group III nitride based semiconductor region, and a group III nitride based active region between the p-side group III nitride based semiconductor region and n-side group III nitride based semiconductor region. The group III nitride based active region includes first and second quantum well layers and a barrier layer between the first and second quantum well layers, the respective compositions of the first and second quantum well layers comprising different respective amounts of indium. The first quantum well is closer to the n-side group III nitride based semiconductor region than the second quantum well, the second quantum well is closer to the p-side group III nitride based semiconductor region than the first quantum well, and the first quantum well has a larger band gap than the second quantum well.

Abstract: A first architecture for a volatile resistive-switching device with a selector layer (e.g., a highly resistive layer such as a resistive switching medium) non-planar surfaces is detailed. For example, the selector layer can have a first surface that intersects a second surface at an angle (e.g., oblique angle). The angle can be adjusted to control current-voltage response for the volatile resistive-switching device. A second architecture for volatile resistive-switching device with a first terminal having a high particle diffusivity and a second terminal having a low particle diffusivity. The second architecture can provide diode-like current-voltage responses at a sizes (e.g., sub-20 nanometers) in which conventional diodes do not scale.

Abstract: Provided is a III-nitride semiconductor light-emitting device having excellent device lifetime as compared with conventional devices and a method of producing the same. A III-nitride semiconductor light-emitting device 100 has an n-type semiconductor layer 30, a light emitting layer 40 containing at least Al, an electron blocking layer 50, and a p-type semiconductor layer 60 in this order. The light emitting layer 40 has a quantum well structure having well layers 41 and barrier layers 42. The electron blocking layer 50 is adjacent to the light emitting layer 40 and is formed from a layer having an Al content higher than that of the barrier layers 42 and the p-type semiconductor layer 60. The electron blocking layer 50 has a Si-based doped region layer 50a.

Abstract: An input device includes a first substrate, a light-emitting element unit, and third conductive layers. The first substrate includes first and second surfaces. The light-emitting element unit includes: first conductive layers formed in one layer on the second surface side; second conductive layers formed in one layer on the second surface side different from the layer of the first conductive layers; and a luminescent layer provided between the first and the second conductive layers and electrically in contact therewith. The third conductive layers are formed to be insulated from the first and the second conductive layers and not to intersect with the second conductive layers in planar view, and are configured to detect a change in an electric field between the first and the third conductive layers depending on coordinates of a proximity object at a position overlapping with the first conductive layers and the first surface in planar view.

Abstract: A method for forming a semiconductor device includes implanting a predefined dose of protons into a semiconductor substrate. Further, the method comprises controlling a temperature of the semiconductor substrate during the implantation of the predefined dose of protons so that the temperature of the semiconductor substrate is within a target temperature range for more than 70% of an implant process time used for implanting the predefined dose of protons. The target temperature range reaches from a lower target temperature limit to an upper target temperature limit. Further, the lower target temperature limit is equal to a target temperature minus 30° C. and the upper target temperature limit is equal to the target temperature plus 30° C. and the target temperature is higher than 80° C.

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

Abstract: A SRAM memory bit cell is provided that includes a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); and a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains). The control circuit is configured to provide, during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p TFET. The control circuit is further configured to provide, during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.

Abstract: A drift region has a first conductivity type. A well region is at least partially included in an interface area, has an end portion between the interface area and an edge termination area, and has a second conductivity type. An extension region extends outward from the well region, is shallower than the well region, and has the second conductivity type. A plurality of field-limiting rings are provided outside the extension region in the edge termination area. Each of the field-limiting rings together with the drift region located on the inner side forms a unit structure. The field-limiting ring located closer to the outside has a lower proportion of a width to a width of the unit structure. The unit structure located closer to the outside has a lower average dose.

Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.

Abstract: Provided is a bridge diode according to an embodiment of the inventive concept. The bridge diode includes a first structure including a first lower nitride film and a first upper nitride film, which are laminated on the substrate, a second structure including a second lower nitride film and a second upper nitride film, which are laminated on the substrate, a first electrode structural body disposed on the first structure, and a second electrode structural body disposed on the second structure.

Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

Abstract: A semiconductor device may include a gate electrode, an insulating layer, a first channel member, and a second channel member. The insulating layer may overlap the gate electrode. The first channel member may be positioned between the gate electrode and the insulating layer. The second channel member may be positioned between the gate electrode and the first channel member. A semiconductor material of the second channel member may be different from a semiconductor material of the first channel member.

Abstract: An optoelectronic component and a method for the producing an optoelectronic component are disclosed.

Abstract: A single memory cell has the functions of a storage element and a selector. The memory cell includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. The tunneling structure is a stack structure including a first material layer, a second material layer and a third material layer. By adjusting a bias voltage that is applied to the P-type layer and the N-type layer, the tunneling structure is controlled to be in the amorphous state or the crystalline state. Consequently, the memory cell has the memorizing and storing functions. The memory cell has the P-type layer, the tunneling structure and the N-type layer. By adjusting the bias voltage, the function of the selector is achieved.

Abstract: A Magnetic Czochralski semiconductor wafer having opposing first and second sides arranged distant from one another in a first vertical direction is treated by implanting first particles into the semiconductor wafer via the second side to form crystal defects in the semiconductor wafer. The crystal defects have a maximum defect concentration at a first depth. The semiconductor wafer is heated in a first thermal process to form radiation induced donors. Implantation energy and dose are chosen such that the semiconductor wafer has, after the first thermal process, an n-doped semiconductor region arranged between the second side and first depth, and the n-doped semiconductor region has, in the first vertical direction, a local maximum of a net doping concentration between the first depth and second side and a local minimum of the net doping concentration between the first depth and first maximum.

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.

Abstract: A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

Abstract: A semiconductor device is provided. On one main surface side of an n-type semiconductor substrate, a p-type diffusion region to serve as an anode of a diode is formed. A guard ring formed of a p-type diffusion region is formed to surround the anode. On the other main surface side, an n-type ultrahigh-concentration impurity layer and an n-type high-concentration impurity layer to serve as a cathode are formed. In a guard-ring opposed region located in the cathode and opposite to the guard ring, a cathode-side p-type diffusion region is formed. Accordingly, concentration of the electric current on an outer peripheral end portion of the anode is suppressed.

Abstract: A nitride semiconductor light emitting device includes a substrate as a base and an n-type semiconductor layer grown on a surface side of the substrate. Antimony (Sb) is added to the n-type semiconductor layer so that a molar fraction is not less than 0.1% and is less than 1%. A concentration of an n-type impurity in the n-type semiconductor layer is lower than an electron concentration.

Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

Abstract: A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.

Abstract: A semiconductor device is disclosed. In a surface layer of a front surface of an n-type semiconductor substrate, an anode layer is provided in an element activation portion and an annular p-type guard ring and an n-type high-concentration surface region are provided in an annular termination breakdown voltage region which surrounds the outer circumference of the anode layer. The impurity concentration of the n-type high-concentration surface region is higher than that of the semiconductor substrate and is lower than that of the p-type guard ring. The depth of the n-type high-concentration surface region is less than that of the guard ring. The anode layer and the guard ring are formed while the oxygen concentration of the semiconductor substrate is set to be equal to or more than 1×1016/cm3 and equal to or less than 1×1018/cm3.

Abstract: A device for detecting a surface plasmon and polarization includes: a topological insulating layer formed on a substrate; first and second electrodes formed on the topological insulating layer; and a waveguide connected to the topological insulating layer between the first and second electrodes.

Abstract: A semiconductor module includes a semiconductor element having a gate electrode and source electrode on the front surface, and a drain electrode on the rear surface, the drain electrode being electrically connected to the front surface of a drain plate; a laminated substrate having, on the front surface of an insulating plate, a first circuit plate to which the gate electrode is electrically connected, and a second circuit plate to which the source electrode is electrically connected, and which is disposed on the front surface of the drain plate; a gate terminal disposed on the first circuit plate; a source terminal disposed on the second circuit plate; and a cover disposed opposite to the front surface of the drain plate, and having an opening in which the gate terminal and the source terminal are positioned and a guide groove contacting the opening and extending to the outer peripheral portion.

Abstract: A p-type anode layer (2) provided on an n-type drift layer (1) in the active region. A p-type diffusion layer (3) is provided on the n-type drift layer (1) in a termination region outside the active region. An oxide film (4) covers an outer periphery of the p-type anode layer (2). An anode electrode (5) is connected to a portion of the p-type anode layer (2) not covered with the oxide film (4). An n+-type cathode layer (7) is provided below the n-type drift layer (1). A cathode electrode (8) is connected to the n+-type cathode layer (7). An area of a portion of the p-type anode layer (2) covered with the oxide film (4) is 5 to 30% of a total area of the p-type anode layer (2).

Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.