With Means To Increase Reverse Breakdown Voltage Patents (Class 257/129)
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Patent number: 11804835Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: injecting charge carriers at a first rate into an upper base of the transistor, the injecting at the first rate results in current flow through the transistor from an upper collector-emitter to a lower collector-emitter, and the current flow results in first voltage drop measured across the upper collector-emitter and the lower collector-emitter; and then, within a predetermined period of time before the end of a first conduction period of the transistor, injecting charge carriers into the upper base at a second rate lower than the first rate, the injecting at the second rate results in second voltage drop measured across the upper collector-emitter and the lower collector-emitter, the second voltage drop higher than the first voltage drop; and then making the transistor non-conductive at the end of the conduction period.Type: GrantFiled: November 19, 2021Date of Patent: October 31, 2023Assignee: IDEAL POWER INC.Inventor: Alireza Mojab
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Patent number: 11646141Abstract: A solenoid valve includes a valve portion and a solenoid portion. The valve portion has a sleeve and a valve body. The solenoid portion includes a tubular coil portion, a magnetic yoke having a side surface portion and a bottom portion, a columnar plunger, a shaft, a stator core having a core shaft hole for sliding the plunger in the axial direction, and a base portion having a base shaft hole. In a radial thickness of the sleeve, a thickness of a part corresponding to an end outer peripheral surface is smaller than a thickness of a sliding portion of an inner peripheral surface of the sleeve, which is a portion on which the valve body slides.Type: GrantFiled: September 14, 2021Date of Patent: May 9, 2023Assignee: DENSO CORPORATIONInventors: Shinichi Kondou, Kazuhiro Sasao, Masato Arai
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Patent number: 11462624Abstract: A vertical semiconductor triode includes a first layer of semiconductor material, the first layer including first and second surfaces, the first surface being in contact with a first electrode forming a Schottky contact.Type: GrantFiled: December 21, 2018Date of Patent: October 4, 2022Assignee: STMICROELECTRONICS (TOURS) SASInventor: Samuel Menard
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Patent number: 10707302Abstract: A semiconductor device manufacturing method includes: a pretreatment step of performing a hydrophobic treatment on a first exposed region of an exposed surface, an n-type semiconductor layer being exposed from the first exposed region, and a pn junction being exposed from the exposed surface; an impurity supplying step of supplying an n-type impurity to the first exposed region; a channel stopper forming step of irradiating the first exposed region with a laser beam to introduce the n-type impurity into the n-type semiconductor layer, thus forming a channel stopper; and a glass layer forming step of forming a glass layer using a glass composition so as to cover the exposed surface.Type: GrantFiled: November 25, 2016Date of Patent: July 7, 2020Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Atsushi Ogasawara, Fumihiro Homma
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Patent number: 10566462Abstract: A bipolar semiconductor device and method are provided. One embodiment provides a bipolar semiconductor device including a first semiconductor region of a first conductivity type having a first doping concentration, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, and a plurality of third semiconductor regions of the first conductivity type at least partially arranged in the first semiconductor region and having a doping concentration which is higher than the first doping concentration. Each of the third semiconductor regions is provided with at least one respective junction termination structure.Type: GrantFiled: July 30, 2009Date of Patent: February 18, 2020Assignee: Infineon Technologies Austria AGInventors: Hans-Joachim Schulze, Frank Pfirsch, Franz-Josef Niedernostheide
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Patent number: 10211283Abstract: Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.Type: GrantFiled: January 11, 2018Date of Patent: February 19, 2019Assignee: Ideal Power Inc.Inventors: William C. Alexander, Richard A. Blanchard
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Patent number: 9941356Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.Type: GrantFiled: April 20, 2017Date of Patent: April 10, 2018Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
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Patent number: 9722036Abstract: According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm.Type: GrantFiled: August 28, 2015Date of Patent: August 1, 2017Assignee: Infineon Technologies Austria AGInventors: Franz Hirler, Oliver Blank, Ralf Siemieniec
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Patent number: 9722020Abstract: A super junction semiconductor device includes a semiconductor portion with first and second surfaces parallel to one another and including a doped layer of a first conductivity type formed at least in a cell area. Columnar first super junction regions of a second conductivity type extend in a direction perpendicular to the first surface and are separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A first electrode structure directly adjoins the first surface and a second electrode structure directly adjoins the second surface. The first electrode structure has a first thickness and the second electrode structure has a second thickness. A sum of the first and second thicknesses is at least 20% of the thickness of the semiconductor portion between the first and second surfaces.Type: GrantFiled: May 20, 2016Date of Patent: August 1, 2017Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Franz Hirler, Hans-Joachim Schulze, Uwe Wahl, Winfried Kaindl
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Patent number: 9356116Abstract: There is provided a power semiconductor device, including a first conductive type drift layer; a second conductive type body layer formed on the drift layer, a second conductive type collector layer formed below the drift layer; a first gate formed by penetrating through the body layer and a portion of the drift layer, a first conductive type emitter layer formed in the body layer and formed to be spaced apart from the first gate, a second gate covering upper portions of the body layer and the emitter layer and formed as a flat type gate on the first gate, and a segregation stop layer formed between contact surfaces of the first and second gates with the body layer, the emitter layer, and the drift layer.Type: GrantFiled: May 9, 2013Date of Patent: May 31, 2016Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jaehoon Park, In Hyuk Song, Dong Soo Seo, Kwang Soo Kim, Kee Ju Um
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Patent number: 9318589Abstract: There is provided an insulated gate bipolar transistor including: a first semiconductor area of a first conductivity type; a second semiconductor area of a second conductivity type formed on one surface of the first semiconductor area; third semiconductor areas of the first conductivity type continuously formed in a length direction on one surface of the second semiconductor area; a plurality of trenches formed between the third semiconductor areas, extending to an inside of the second semiconductor area, and being continuous in the length direction; a fourth semiconductor area of the second conductivity type formed on one surface of the third semiconductor areas, insulation layers formed inside the trenches; gate electrodes buried inside the insulation layers; and a barrier layer formed in at least one of locations corresponding to the third semiconductor areas inside the second semiconductor area.Type: GrantFiled: January 28, 2013Date of Patent: April 19, 2016Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jaehoon Park, Chang Su Jang, In Hyuk Song, Kee Ju Um, Dong Soo Seo
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Patent number: 9035350Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.Type: GrantFiled: September 8, 2014Date of Patent: May 19, 2015Assignee: Ideal Power Inc.Inventors: Richard A. Blanchard, William C. Alexander
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Patent number: 9029909Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.Type: GrantFiled: June 24, 2014Date of Patent: May 12, 2015Assignee: Ideal Power Inc.Inventors: Richard A. Blanchard, William C. Alexander
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Patent number: 8847278Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.Type: GrantFiled: January 16, 2012Date of Patent: September 30, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Manabu Takei, Yusuke Kobayashi
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Publication number: 20140217462Abstract: A high-voltage vertical power component including a silicon substrate of a first conductivity type, and a first semiconductor layer of the second conductivity type extending into the silicon substrate from an upper surface of the silicon substrate, wherein the component periphery includes: a porous silicon ring extending into the silicon substrate from the upper surface to a depth deeper than the first layer; and a doped ring of the second conductivity type, extending from a lower surface of the silicon surface to the porous silicon ring.Type: ApplicationFiled: February 7, 2013Publication date: August 7, 2014Applicants: Universite Francois Rabelais, STMicroelectronics (Tours) SASInventors: Samuel Menard, Gaƫl Gautier
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Patent number: 8093621Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.Type: GrantFiled: December 23, 2008Date of Patent: January 10, 2012Assignee: Power Integrations, Inc.Inventors: Vijay Parthasarathy, Sujit Banerjee
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Patent number: 7902570Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.Type: GrantFiled: October 9, 2009Date of Patent: March 8, 2011Assignee: Princeton Lightwave, Inc.Inventors: Mark Allen Itzler, Rafael Ben-Michael, Sabbir Sajjad Rangwala
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Patent number: 7898065Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.Type: GrantFiled: December 10, 2009Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
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Patent number: 7897998Abstract: A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions.Type: GrantFiled: September 6, 2007Date of Patent: March 1, 2011Assignee: International Rectifier CorporationInventor: Robert Beach
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Patent number: 7863645Abstract: A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate may be a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. Because an individual junction gate has an intrinsically high breakdown voltage, the breakdown voltage of the double-gate semiconductor device is greater than the breakdown voltage of an individual MOS gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices.Type: GrantFiled: February 13, 2008Date of Patent: January 4, 2011Assignee: ACCO Semiconductor Inc.Inventors: Denis A. Masliah, Alexandre G. Bracale, Francis C. Huin, Patrice J. Barroul
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Patent number: 7821028Abstract: A power semiconductor component and a method for producing such a component. The component comprises a semiconductor base body having a first doping. A pn junction is formed in the base body by a contact region having a second doping with a first doping profile. A field ring structure has a second doping with a second doping profile. The contact region and the field ring structure are arranged at respectively assigned first and second partial areas of a first surface of the base body. Both extend into the base body, wherein the base body has, for the field ring structure, a trench-type cutout assigned to each respective field ring, the surface of said cutout following the contour of the assigned doping profile.Type: GrantFiled: December 22, 2008Date of Patent: October 26, 2010Assignee: SEMIKRON Elektronik GmbH & Co. KGInventor: Bernhard Kƶnig
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Patent number: 7626193Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.Type: GrantFiled: March 27, 2006Date of Patent: December 1, 2009Assignee: Princeton Lightwave, Inc.Inventors: Mark Allen Itzler, Rafael Ben-Michael, Sabbir Sajjad Rangwala
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Publication number: 20090179224Abstract: A power semiconductor component and a method for producing such a component. The component comprises a semiconductor base body having a first doping. A pn junction is formed in the base body by a contact region having a second doping with a first doping profile. A field ring structure has a second doping with a second doping profile. The contact region and the field ring structure are arranged at respectively assigned first and second partial areas of a first surface of the base body. Both extend into the base body, wherein the base body has, for the field ring structure, a trench-type cutout assigned to each respective field ring, the surface of said cutout following the contour of the assigned doping profile.Type: ApplicationFiled: December 22, 2008Publication date: July 16, 2009Inventor: Bernhard Konig
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Patent number: 7485921Abstract: This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.Type: GrantFiled: February 13, 2007Date of Patent: February 3, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kawaguchi, Yoshihiro Yamaguchi, Syotaro Ono, Miwako Akiyama
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Patent number: 7205194Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.Type: GrantFiled: June 24, 2004Date of Patent: April 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sun Lee, Jae-Min Yu, Don-Woo Lee, Jung-Hun Cho, Chul-Soon Kwon, Jung-Ho Moon, In-Gu Yoon, Jae-Hyun Park
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Patent number: 7154129Abstract: A semiconductor system (200), particularly a diode, having a p-n junction is proposed, that is formed as a chip having an edge area, which includes a first layer (2) of a first conductivity type and a second layer (1, 3) of a second conductivity type; the second layer (1, 3) including at least two sublayers (1, 3); both sublayers (1, 3) forming a p-n junction with the first layer (2); the p-n junction of the first layer (2) with the first sublayer (3) being provided exclusively in the interior of the chip, and the p-n junction between the first layer (2) and the second sublayer (1) being provided in the edge area of the chip; for each cross-section of the chip area parallel to the chip plane, the first sublayer (3) corresponding only to a part of such a cross-section.Type: GrantFiled: November 27, 2002Date of Patent: December 26, 2006Assignee: Robert Bosch GmbHInventor: Alfred Goerlach
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Patent number: 6967356Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone (1) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall (2) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer (3) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer (21) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.Type: GrantFiled: October 11, 2001Date of Patent: November 22, 2005Assignee: STMicroelectronics S.A.Inventor: GĆ©rard Auriel
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Patent number: 6838729Abstract: The invention relates to a semiconductor component with enhanced avalanche ruggedness. At the nominal current of this semiconductor component, in the event of an avalanche the voltage applied between two electrodes is 6 % or more above the static reverse voltage at the same temperature.Type: GrantFiled: April 29, 2002Date of Patent: January 4, 2005Assignee: Infineon Technologies AGInventors: Andreas Schlƶgl, Markus Schmitt, Hans-Joachim Schulze, Markus VossebĆ¼rger, Armin Willmeroth
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Patent number: 6815790Abstract: The present invention improves the resolution and accuracy of the presently known two-dimensional position sensing detectors and delivers improved performance in the 1.3 to 1.55 micron wavelength region. The present invention is an array of semiconductor layers with four electrodes, the illustrative embodiment comprising a semi-insulating substrate semiconductor base covered by a semiconductor buffered layer, the buffered layer further covered by a semiconductor absorption layer and the absorption layer covered with a semiconductor layer. Four electrodes are placed on this semiconductor array: two on the top layer parallel to each other and near the ends of opposite edges, and two etched in the buffered layer, parallel to each other and perpendicular to the first set. The layers are doped as to make a p-n junction in the active area. Substantially all the layers, excepting the semi-insulating substrate layer, are uniformly resistive.Type: GrantFiled: January 10, 2003Date of Patent: November 9, 2004Assignee: Rapiscan, Inc.Inventors: Peter S. Bui, Narayan Dass Taneja
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Patent number: 6803627Abstract: A reverse-blocking power semiconductor component includes a drift path subdivided into a source-side area and a drain-side area by a region with opposite doping. Provided above this region is a gate. Alternatively, the body zone of the one conduction type is subdivided into a source-side part and a drain-side part by a region of the other conduction type. This region acts as an electron collector. The reverse-blocking power semiconductor component can be incorporated in compensation components, and power transistors. Methods for producing power semiconductor components are also provided.Type: GrantFiled: January 15, 2004Date of Patent: October 12, 2004Assignee: Infineon Technologies AGInventor: Frank Pfirsch
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Patent number: 6727527Abstract: A power device includes a semiconductor substrate of first conductivity type. The semiconductor substrate includes a front-side surface, a backside surface, and a scribe region. The substrate has a first well of second conductivity type whereon an active cell is defined. The first well has a first impurity type of a first mobility. A continuous diffusion region of second conductivity type extends from the front-side surface to the backside surface. The continuous diffusion region includes a second impurity type of a second mobility that has been diffused vertically into the substrate from a selected location of the backside surface. The second mobility is higher than the first mobility. A lower portion of the continuous diffusion region corresponds to the selected location of the continuous diffusion region.Type: GrantFiled: July 17, 2000Date of Patent: April 27, 2004Assignee: IXYS CorporationInventor: Nathan Zommer
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Patent number: 6583453Abstract: A semiconductor device providing an improved effect of suppressing variation with time of reverse breakdown voltage applied to PN junction, particularly, a voltage-regulator device, is provided. The semiconductor device includes an impurity diffusion layer 15 formed on a surface of a certain-conductivity-type semiconductor substrate or well, the impurity diffusion layer having a conductivity opposite to that of the semiconductor substrate or well, and a device separating insulation film 12 formed at a distance from the impurity diffusion layer, and a distance between an end of the impurity diffusion layer and an end of the device separating insulation film is defined to be not less than 1.2 &mgr;m.Type: GrantFiled: November 6, 2001Date of Patent: June 24, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirotsugu Honda, Masafumi Doi
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Patent number: 6576935Abstract: A bidirectional semiconductor device facilitates making a current flow from the first MOSFET to the second MOSFET and vice versa across low on-resistance and exhibits a high breakdown voltage. The bidirectional semiconductor device includes a first n-channel MOSFET including base regions, a second n-channel MOSFET including base regions, and an alternating conductivity type layer formed of drift region and partition regions arranged alternately. Partition regions are isolated from base regions by a high resistivity region and from base regions by a high resistivity region to maintaining a high breakdown voltage between first MOSFET and the second MOSFET. By connecting high resistivity regions and via drift regions to each other, a current is made flow from the first MOSFET to the second MOSFET and vice versa and the on-voltage is reduced.Type: GrantFiled: June 28, 2001Date of Patent: June 10, 2003Assignee: Fuji Electric Co., Ltd.Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
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Patent number: 6538266Abstract: A semiconductor device for lowering a triggering voltage includes a semiconductor substrate with a first conductivity; a semiconductor region formed in the substrate having a second conductivity; a first region formed in the substrate, having the first conductivity and being apart from the semiconductor region; a second region formed in the substrate having the second conductivity and being spaced apart from the semiconductor region and first region; a third region formed in the substrate, having the second conductivity and being spaced apart from the semiconductor region, the first and second regions; a fourth region formed in the semiconductor region, having the second conductivity and being connected to the third region through a conductive material; a fifth region formed in the semiconductor region, having the first conductivity and being spaced apart from the fourth region; and a sixth region formed in the semiconductor region, having the second conductivity and being spaced apart from the fourth and fifType: GrantFiled: May 24, 2001Date of Patent: March 25, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Jung Lee, Yong-Ha Song
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Patent number: 6521520Abstract: A method of processing a semiconductor wafer and an associated semiconductor wafer arrangement which inhibits “punch through” and increases the yield of functional semiconductor wafers during the fabrication thereof is disclosed. A method of forming a semiconductor with a substrate and a feature on the surface of the substrate is disclosed: Forming a spacer layer that contacts the feature. A barrier layer of silicon nitride can be deposited on the surface. Contacting the barrier layer with the spacer layer, prior to removing the barrier layer. Align a contact void with the barrier layer and spacer layer. Align a contact void such that the etch properties of the barrier layer prevents “punch through”.Type: GrantFiled: August 30, 2001Date of Patent: February 18, 2003Assignee: LSI Logic CorporationInventors: Charles E. May, Hemanshu Bhatt
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Patent number: 6307232Abstract: A diode having a p+ semiconductor region, an n− drift region and an n+ semiconductor region is formed in an SOI layer. An SiC layer is formed in the bottom surface of a semiconductor layer. Further, a capacitive coupled multiple field plate including conductive layers is formed between cathode and anode electrodes. As a result, a semiconductor device with a lateral high breakdown voltage element having extremely high breakdown voltage which is never restricted by electric field concentration in the surface of the SOI layer can be achieved.Type: GrantFiled: November 25, 1997Date of Patent: October 23, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hajime Akiyama, Yoichiro Tarui
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Patent number: 6218217Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n− silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.Type: GrantFiled: July 18, 2000Date of Patent: April 17, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akio Uenishi, Katsumi Nakamura
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Patent number: 6023078Abstract: Silicon carbide power devices include a semiconductor substrate of first conductivity type (e.g., N-type) having a face thereon and a blocking voltage supporting region of first conductivity type therein extending to the face. The voltage supporting region is designed to have a much lower majority carrier conductivity than an underlying and highly conductive "bypass" portion of the semiconductor substrate. This bypass portion of the substrate supports large lateral currents with low on-state voltage drop. First and second semiconductor devices are also provided having respective first and second active regions of first conductivity type therein. These first and second active regions extend on opposing sides of the voltage supporting region and are electrically coupled to the bypass portion of the semiconductor substrate which underlies and extends opposite the voltage supporting region relative to the face of the substrate.Type: GrantFiled: April 28, 1998Date of Patent: February 8, 2000Assignee: North Carolina State UniversityInventor: Bantval Jayant Baliga
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Patent number: 5894149Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.31 silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.Type: GrantFiled: December 9, 1996Date of Patent: April 13, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akio Uenishi, Katsumi Nakamura
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Patent number: 5455434Abstract: A thyristor includes a semiconductor body with a surface. The semiconductor body has an inner zone of a first conduction type; a cathode-side base zone of a second conduction type opposite the first type, the base zone having a recess formed therein; a layer of the second conduction type being disposed on the surface of the semiconductor body, being disposed in the cathode-side base zone, being thinner than the cathode-side base zone, and being joined to the cathode-side base zone; and an additional zone of the second conduction type being disposed in the recess, being joined to the layer, being thicker than the layer, and being spaced apart from the cathode-side base zone.Type: GrantFiled: August 8, 1994Date of Patent: October 3, 1995Assignee: Siemens AktiengesellschaftInventor: Frank Pfirsch
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Patent number: 5293051Abstract: A switching device includes a thyristor and a MOSFET, and a voltage clamp circuit. The voltage clamp circuit includes an N.sup.+ type contact region formed in a surface layer of a N type substrate and electrically connected to a gate electrode of a MOSFET, and a P type guard ring surrounding the contact region.Type: GrantFiled: February 11, 1993Date of Patent: March 8, 1994Assignee: Sharp Kabushiki KaishaInventors: Mitsuru Mariyama, Nobuyuki Kato