With Resistive Region Connecting Separate Sections Of Device Patents (Class 257/154)
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Patent number: 11963412Abstract: A display device including: a panel including pixels, a pixel including; an LED; a capacitor between a first voltage line and a node; a first transistor between the first voltage line and a first electrode of the LED; a second transistor between a data line and a source of the first transistor; a third transistor between the node and a drain of the first transistor; a fourth transistor between the node and a second voltage line; a fifth transistor between the first voltage line and the source of the first transistor; a sixth transistor between the first electrode and the drain of the first transistor; and a seventh transistor between the second voltage line and the first electrode, the third and fourth transistor including: an active area including metal oxide; first and second gates above the active area; and a pattern below the active area.Type: GrantFiled: June 21, 2022Date of Patent: April 16, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Suyeon Yun, Sunghoon Kim, Anna Ryu
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Patent number: 11749738Abstract: A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.Type: GrantFiled: February 7, 2022Date of Patent: September 5, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Hsien-Wen Wan, Yi-Ting Cheng, Ming-Hwei Hong, Juei-Nai Kwo, Bo-Yu Yang, Yu-Jie Hong
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Patent number: 11705462Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.Type: GrantFiled: August 17, 2020Date of Patent: July 18, 2023Assignee: Au Optronics CorporationInventors: Ya-Ling Hsu, Min-Tse Lee, Ti-Kuei Yu, Yueh-Chi Wu, Shu-Wen Liao, Hung-Chia Liao, Yueh-Hung Chung, Jia-Hong Wang, Ping-Wen Chen, Sheng-Yen Cheng, Chen-Hsien Liao
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Patent number: 11296221Abstract: A power semiconductor device includes: a semiconductor layer including a main cell region, a sensor region, and an insulation region between the main cell region and the sensor region; a plurality of power semiconductor transistors disposed on the main cell region; a plurality of current sensor transistors disposed on the sensor region; and a protection resistance layer disposed on the semiconductor layer across the insulation region so that at least a portion of the plurality of power semiconductor transistors and at least a portion of the plurality of current sensor transistors are connected to each other under an abnormal operation condition.Type: GrantFiled: April 30, 2020Date of Patent: April 5, 2022Assignee: HYUNDAI MOBIS CO., LTD.Inventors: Ju-Hwan Lee, Tae-Young Park, Seong-hwan Yun
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Patent number: 11257807Abstract: A semiconductor device of electrostatic discharge (ESD) protection is provided, including a deep N-type region, disposed in a substrate; a deep P-type region, disposed in the substrate; a first P-type well, disposed in the deep N-type region; a first N-type well, abutting to the first P-type well, disposed in the deep N-type region. Further, a second P-type well abutting to the first N-type well is disposed in the deep P-type region. A second N-type well abutting to the second P-type well is disposed in the deep P-type region. A side N-type well is disposed in the deep N-type region at an outer side of the first P-type well. A side P-type well is disposed in the deep P-type region at an outer side of the second N-type well.Type: GrantFiled: December 3, 2020Date of Patent: February 22, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ting-Yao Lin, Chun Chiang, Ping-Chen Chang, Tien-Hao Tang
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Patent number: 10199368Abstract: An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor.Type: GrantFiled: February 19, 2017Date of Patent: February 5, 2019Assignee: STMicroelectronics (Rousset) SASInventor: François Tailliet
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Patent number: 9997704Abstract: A cross bar array device includes first electrodes arranged adjacent to each other and extending in a first direction, the first electrodes including a main electrode layer and a scalable electrode layer. Second electrodes are arranged transversely to the first electrodes, the second electrodes including a main electrode layer and a scalable electrode layer. An electrolyte layer is disposed between the scalable electrode layers of the first electrodes and the second electrodes. A scalable electrode is formed from a scalable electrode layer and includes an undercut having a side laterally recessed from a width of a corresponding main electrode.Type: GrantFiled: January 26, 2017Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
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Patent number: 9748364Abstract: A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure.Type: GrantFiled: June 19, 2015Date of Patent: August 29, 2017Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Shiyu Sun, Naomi Yoshida, Benjamin Colombeau, Hans-Joachim L. Gossmann
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Patent number: 9613910Abstract: A package structure includes an integrated circuit die, a redistribution structure, an anti-fuse, and external connectors. The integrated circuit die is embedded in an encapsulant. The redistribution structure is on the encapsulant and is electrically coupled to the integrated circuit die. The anti-fuse is external to the integrated circuit die and the redistribution structure. The anti-fuse is mechanically and electrically coupled to the redistribution structure. The external connectors are on the redistribution structure, and the redistribution structure is disposed between the external connectors and the encapsulant.Type: GrantFiled: July 17, 2014Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: An-Jhih Su, Hsien-Wei Chen
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Patent number: 9601546Abstract: A cross bar array device includes first electrodes arranged adjacent to each other and extending in a first direction, the first electrodes including a main electrode layer and a scalable electrode layer. Second electrodes are arranged transversely to the first electrodes, the second electrodes including a main electrode layer and a scalable electrode layer. An electrolyte layer is disposed between the scalable electrode layers of the first electrodes and the second electrodes. A scalable electrode is formed from a scalable electrode layer and includes an undercut having a side laterally recessed from a width of a corresponding main electrode.Type: GrantFiled: September 12, 2016Date of Patent: March 21, 2017Assignee: International Business Machines CorporationInventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
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Patent number: 9378811Abstract: A method of operating a resistive non-volatile memory can be provided by applying a forming voltage across first and second electrodes of a selected memory cell in the variable resistance non-volatile memory device during an operation to the selected memory cell. The forming voltage can be a voltage level that is limited to less than a breakdown voltage of an insulation film included in selected memory cell between a variable resistance film and one of first electrode. Related devices and materials are also disclosed.Type: GrantFiled: September 9, 2013Date of Patent: June 28, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyunsu Ju, Min Kyu Yang, Eunmi Kim, Seonggeon Park, Ingyu Baek
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Patent number: 9324605Abstract: The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a horizontal surface. The method includes forming an interconnect structure over the horizontal surface of the substrate. The forming the interconnect structure includes forming an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The forming the interconnect structure includes forming a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.Type: GrantFiled: September 15, 2014Date of Patent: April 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hsiu-Ying Cho
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Patent number: 9257550Abstract: An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.Type: GrantFiled: June 30, 2015Date of Patent: February 9, 2016Assignee: STMICROELECTRONICS S.R.L.Inventors: Donato Corona, Nicolo′ Frazzetto, Antonio Giuseppe Grimaldi, Corrado Iacono, Monica Micciche′
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Patent number: 9035352Abstract: A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.Type: GrantFiled: April 30, 2012Date of Patent: May 19, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gianluca Boselli, Rajkumar Sankaralingam
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Publication number: 20150084094Abstract: An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode.Type: ApplicationFiled: September 24, 2014Publication date: March 26, 2015Applicant: STMICROELECTRONICS (TOURS) SASInventor: Samuel Menard
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Patent number: 8963277Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.Type: GrantFiled: May 30, 2013Date of Patent: February 24, 2015Assignee: MACRONIX International Co., Ltd.Inventors: Chen-Yuan Lin, Ching-Lin Chan, Cheng-Chi Lin, Shih-Chin Lien
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Publication number: 20150048415Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping.Type: ApplicationFiled: August 19, 2013Publication date: February 19, 2015Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Ling Hung, Hsin-Liang Chen, Wing-Chor Chan
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Publication number: 20140375377Abstract: A thyristor is disclosed comprising: a first region of a first conductivity type; a second region of a second conductivity type and adjoining the first region; a third region of the first conductivity type and adjoining the second region; a fourth region of the second conductivity type and comprising a first segment and a second segment separate from the first segment, the first segment and second segment each adjoining the third region; a first contact adjoining the first region; a second contact adjoining the first segment; and a trigger contact adjoining the second segment and separate from the second contact. Methods of triggering such a thyristor are also disclosed, as are circuits utilising one or more such thyristors.Type: ApplicationFiled: May 16, 2014Publication date: December 25, 2014Applicant: NXP B.V.Inventors: Rob Van Dalen, Maarten Jacobus Swanenberg, Inesz Emmerik-Weijland
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Patent number: 8835896Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.Type: GrantFiled: August 19, 2013Date of Patent: September 16, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hidenori Miyagawa, Shosuke Fujii, Akira Takashima, Daisuke Matsushita
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Patent number: 8791501Abstract: An integrated passive device (IPD) structure includes an electronic component having an active surface and an opposite inactive surface. The IPD structure further includes a passive device structure extending through the electronic component between the active surface and the inactive surface and having a portion(s) formed on the active surface, the inactive surface, or both the active and inactive surfaces. Accordingly, the IPD structure includes the functionality of the electronic component, e.g., an integrated circuit chip, and of the passive device structure, e.g., one or more capacitors, resistors, inductors, or surface mounted components. By integrating the passive device structure with the electronic component to form the IPD structure, separate mounting of passive component(s) to the substrate is avoided this minimizing the substrate size.Type: GrantFiled: December 3, 2010Date of Patent: July 29, 2014Inventors: Ruben Fuentes, Brett Dunlap
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Patent number: 8710455Abstract: A charged-particle beam lens includes a plate-like anode, a plate-like cathode, and an insulator disposed between the anode and the cathode. The insulator, the anode, and the cathode have a passage portion through which a charged beam is passed. A high-resistance film is formed on an inner side of the insulator, the inner side forming the passage portion, or an outermost side of insulator, and the anode and the cathode are electrically connected together via the high-resistance film. The anode and the high-resistance film, and the cathode and the high-resistance film each contain the same metal or semiconductor element and have different resistant values. This suppresses electric field concentration due to an increase in resistance and poor connection at the interface between the anode and the cathode and the high-resistance film or at the interface between the electroconductive film and the high-resistance film, thus suppressing generation of discharge.Type: GrantFiled: March 15, 2013Date of Patent: April 29, 2014Assignee: Canon Kabushiki KaishaInventor: Takashi Shiozawa
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Patent number: 8686470Abstract: An integrated circuit device provides electrostatic discharge (ESD) protection. In connection with various example embodiments, an ESD protection circuit includes a diode-type circuit having a p-n junction that exhibits a low breakdown voltage. Connected in series with the diode between an internal node susceptible to an ESD pulse and ground, are regions of opposite polarity having junctions therebetween for mitigating the passage of leakage current via voltage sharing with the diode's junction. Upon reaching the breakdown voltage, the diode shunts current to ground via another substrate region, bypassing one or more junctions of the regions of opposite polarity and facilitating a low clamping voltage.Type: GrantFiled: January 7, 2011Date of Patent: April 1, 2014Assignee: NXP, B.V.Inventor: Hans-Martin Ritter
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Patent number: 8680573Abstract: Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region.Type: GrantFiled: April 25, 2012Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
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Patent number: 8642987Abstract: The invention provides a novel memory for which process technology is relatively simple and which can store multivalued information by a small number of elements. A part of a shape of the first electrode in the first storage element is made different from a shape of the first electrode in the second storage element, and thereby voltage values which change electric resistance between the first electrode and the second electrode are varied, so that one memory cell stores multivalued information over one bit. By partially processing the first electrode, storage capacity per unit area can be increased.Type: GrantFiled: October 14, 2009Date of Patent: February 4, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tamae Takano, Kiyoshi Kato, Hideaki Kuwabara
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Patent number: 8399908Abstract: Methods for making a programmable metallization memory cell are disclosed.Type: GrantFiled: January 11, 2012Date of Patent: March 19, 2013Assignee: Seagate Technology LLCInventors: Haiwen Xi, Ming Sun, Dexin Wang, Shuiyuan Huang, Michael Tang, Song S. Xue
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Patent number: 8334165Abstract: Methods for making a programmable metallization memory cell are disclosed.Type: GrantFiled: April 16, 2010Date of Patent: December 18, 2012Assignee: Seagate Technology LLCInventors: Haiwen Xi, Ming Sun, Dexin Wang, Shuiyuan Huang, Michael Tang, Song S. Xue
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Patent number: 8299558Abstract: A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.Type: GrantFiled: August 3, 2011Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Alan B. Botula, Alvin J. Joseph, Alan F. Norris, Robert M. Rassel, Yun Shi
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Patent number: 8164110Abstract: The present invention relates to integration of lateral high-voltage devices, such as a lateral high-voltage diode (LHVD) or a lateral high-voltage thyristor, with other circuitry on a semiconductor wafer, which may be fabricated using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, or the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The reverse breakdown voltage capability of the LHVD may be increased by using an intrinsic material between the anode and the cathode. Similarly, in a lateral high-voltage thyristor, such as a lateral high-voltage Silicon-controlled rectifier (LHV-SCR), the withstand voltage capability of the LHV-SCR may be increased by using an intrinsic material between the anode and the cathode.Type: GrantFiled: November 18, 2010Date of Patent: April 24, 2012Assignee: RF Micro Devices, Inc.Inventors: Daniel Charles Kerr, David C. Dening, Julio Costa
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Patent number: 8125003Abstract: One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes.Type: GrantFiled: July 2, 2003Date of Patent: February 28, 2012Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 8097902Abstract: A programmable metallization memory cell that has an apertured insulating layer comprising at least one aperture therethrough positioned between the active electrode and the inert electrode. Superionic clusters are present within the at least one aperture, and may extend past the at least one aperture. Also, methods for making a programmable metallization memory cell are disclosed.Type: GrantFiled: July 10, 2008Date of Patent: January 17, 2012Assignee: Seagate Technology LLCInventors: Haiwen Xi, Ming Sun, Dexin Wang, Shuiyuan Huang, Michael Tang, Song S. Xue
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Publication number: 20110204415Abstract: A high holding voltage (HV) electrostatic discharge (ESD) protection circuit comprises a silicon controlled rectifier (SCR) device and compensation regions located within the length between the anode and cathode (LAC) of the SCR device which increase the holding voltage of the SCR device. The compensation regions may introduce negative feedback mechanisms into the SCR device which may influence the loop gain of the SCR and cause it to reach regenerative feedback at a higher holding voltage.Type: ApplicationFiled: February 17, 2011Publication date: August 25, 2011Applicant: SOFICS BVBAInventors: Sven Van Wijmeersch, Olivier Marichal
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Patent number: 7994536Abstract: An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.Type: GrantFiled: February 19, 2008Date of Patent: August 9, 2011Assignee: Qimonda AGInventors: Rolf Weis, Thomas Happ
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Patent number: 7968902Abstract: A light emitting device and method for producing the same is disclosed. The light emitting device includes a semiconductor material, an electrode positioned on the semiconductor material, a wire bonding area, and a resistor connected between the wire bonding area and the electrode.Type: GrantFiled: March 31, 2008Date of Patent: June 28, 2011Assignee: Bridgelux, Inc.Inventor: Chris Lowery
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Patent number: 7876596Abstract: A novel nonvolatile memory element, which can be manufactured by a simple and high yield process by using an organic material and has a high on/off ratio, and a method for manufacturing such nonvolatile memory element. A switching layer (14) made of an electrical insulating radical polymer is provided between an anode layer (12) and a cathode layer (16). Further, a hole injection transport layer (13) is provided between the switching layer (14) and the anode layer (12), and an electron injection transport layer (15), between the switching layer (14) and the cathode layer (16). An intermediate layer is provided between the switching layer and the adjacent layer. The radical polymer is preferably nitroxide radical polymer. The switching layer (14), the hole injection transport layer (13) and the electron injection transport layer (15) are formed by being stacked by a wet process.Type: GrantFiled: November 4, 2005Date of Patent: January 25, 2011Assignee: Waseda UniversityInventors: Hiroyuki Nishide, Kenji Honda, Yasunori Yonekuta, Takashi Kurata, Shigemoto Abe
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Patent number: 7863708Abstract: A field effect transistor (FET) includes a source electrode for receiving an externally-provided source voltage. The FET further includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region. During operation, one end of the resistive element is biased to the source voltage.Type: GrantFiled: April 16, 2009Date of Patent: January 4, 2011Assignee: Fairchild Semiconductor CorporationInventors: Hamza Yilmaz, Daniel Calafut
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Patent number: 7851888Abstract: Non-volatile memories formed on a substrate and fabrication methods are disclosed. A bottom electrode comprising a metal layer is disposed on the substrate. A buffer layer comprising a LaNiO3 film is disposed over the metal layer. A resistor layer comprising a SrZrO3 film is disposed on the buffer layer. A top electrode is disposed on the resistor layer.Type: GrantFiled: March 20, 2007Date of Patent: December 14, 2010Assignee: Winbond Electronics Corp.Inventors: Tseung-Yuen Tseng, Chun-Chieh Lin, Chao-Cheng Lin
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Patent number: 7821069Abstract: A semiconductor device includes: n transistor elements; n resistive elements; and n capacitive elements, each kind of elements coupled in series between the first and second terminals. The gate of each transistor element has a gate pad, and each transistor element includes transistor pads disposed on both sides. Each resistive element includes resistive pads disposed on both sides. Each capacitive element includes capacitive pads disposed on both sides. The gate pad other than the first stage transistor element, a corresponding resistive pad, and a corresponding capacitive pad are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the first stage are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the n-th stage are electrically coupled.Type: GrantFiled: January 22, 2008Date of Patent: October 26, 2010Assignee: DENSO CORPORATIONInventors: Satoshi Shiraki, Hiroyuki Ban, Akira Yamada
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Patent number: 7812333Abstract: An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode coupled to the second resistivity changing material. A cross-sectional width of the first resistivity changing material is less than a cross-sectional width of the second resistivity changing material.Type: GrantFiled: June 28, 2007Date of Patent: October 12, 2010Assignee: Qimonda North America Corp.Inventors: Jan Boris Philipp, Thomas Happ
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Patent number: 7772614Abstract: A solid electrolyte memory element comprising an inert cathode electrode, a reactive anode electrode and a solid electrolyte layer disposed between the inert cathode electrode and the reactive anode electrode, wherein the solid electrolyte layer comprises a solid electrolyte matrix having defect sites.Type: GrantFiled: March 16, 2006Date of Patent: August 10, 2010Assignee: Qimonda AGInventor: Cay-Uwe Pinnow
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Patent number: 7728350Abstract: One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes.Type: GrantFiled: June 28, 2006Date of Patent: June 1, 2010Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 7635909Abstract: A semiconductor diode has an anode, a cathode and a semiconductor volume provided between anode and cathode. A plurality of semiconductor zones are formed in the semiconductor volume, which semiconductor zones are inversely doped with respect to their immediate surroundings, spaced apart from one another and provided in the vicinity of the cathode. The semiconductor zones are spaced apart from the cathode.Type: GrantFiled: December 23, 2004Date of Patent: December 22, 2009Assignee: Infineon Technologies AGInventors: Anton Mauder, Hans-Joachim Schulze, Frank Pfirsch, Elmar Falck, Josef Lutz
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Patent number: 7633095Abstract: Integrating high-voltage devices with other circuitry, which may be fabricated on a semiconductor wafer using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, and the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The high-voltage devices may be used to create useful high-voltage circuits, such as level-shifting circuits, input protection circuits, charge pump circuits, switching circuits, latch circuits, latching switch circuits, interface circuits, any combination thereof, or the like. The high-voltage circuits may be controlled by the other circuitry.Type: GrantFiled: June 17, 2008Date of Patent: December 15, 2009Assignee: RF Micro Devices, Inc.Inventors: Daniel Charles Kerr, David C. Dening, Julio Costa
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Patent number: 7611957Abstract: The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer.Type: GrantFiled: January 30, 2007Date of Patent: November 3, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Eiji Nishibe, Toshihiro Hachiyanagi
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Patent number: 7613028Abstract: A switching element for reversible switching between an electrically insulating OFF state and an electrically conductive ON state, having two electrodes, namely a reactive electrode and an inert electrode, and also a solid electrolyte arranged between the two electrodes, which is characterized by the fact that the electrical conductivity of the solid electrolyte increases as the temperature thereof rises, but essentially no longer increases below a critical decomposition temperature of the solid electrolyte.Type: GrantFiled: May 18, 2005Date of Patent: November 3, 2009Assignee: Infineon Technologies AGInventors: Cay-Uwe Pinnow, Klaus-Dieter Ufert
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Patent number: 7521773Abstract: A field effect transistor includes an active region and a termination region surrounding the active region. A resistive element is coupled to the termination region, wherein upon occurrence of avalanche breakdown in the termination region an avalanche current starts to flow in the termination region, and the resistive element is configured to induce a portion of the avalanche current to flow through the termination region and a remaining portion of the avalanche current to flow through the active region.Type: GrantFiled: March 31, 2006Date of Patent: April 21, 2009Assignee: Fairchild Semiconductor CorporationInventors: Hamza Yilmaz, Daniel Calafut
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Patent number: 7515454Abstract: According to one embodiment of the present invention, a CBRAM cell includes a solid electrolyte block having at least three solid electrolyte contacting areas, electrodes electrically connected to the solid electrolyte contacting areas, wherein conductive paths are formable, erasable or detectable within the solid electrolyte block by applying voltages between the solid electrolyte contacting areas using the electrodes as voltage suppliers, and wherein the contacting areas are spatially separated from each other such that conductive paths starting from different solid electrolyte contacting areas or ending at different solid electrolyte contacting areas do not overlap each other.Type: GrantFiled: August 2, 2006Date of Patent: April 7, 2009Assignees: Infineon Technologies AG, Altis Semiconductor, SNCInventor: Ralf Symanczyk
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Patent number: 7465966Abstract: A new film formation method that makes it possible to form a film with a little concentration of contaminants from a material and to form a film on a low heat-resistant member is proposed. Further, a method for forming a film that can keep semiconductor properties is proposed. In the film formation method of the present invention, a first film that is to be a target is formed by employing plasma CVD, and the first film is sputtered, thereby forming the second film on a surface of the substrate to be processed in one chamber. By employing the film formation method of the present invention for a protective film of a semiconductor element, deterioration of a semiconductor device can be controlled.Type: GrantFiled: March 19, 2004Date of Patent: December 16, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsuhiro Ichijo, Taketomi Asami, Kunihiko Fukuchi, Satoshi Toriumi
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Patent number: 7442605Abstract: The present invention relates to a reproducible conditioning during the manufacturing of a resistively switching CBRAM memory cell comprising a first electrode and a second electrode with an active material positioned therebetween. The active material is adapted to be placed in a more or less electroconductive state by means of electrochemical switching processes. A CBRAM memory cell manufactured pursuant to the method according to the invention has, due to the improved conditioning, more reliable and more distinctly evaluable electrical switching properties. Moreover, no more forming step is necessary with the method according to the present invention.Type: GrantFiled: April 25, 2005Date of Patent: October 28, 2008Assignee: Infineon Technologies AGInventors: Klaus Dieter Ufert, Cay-Uwe Pinnow
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Patent number: 7414258Abstract: A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.Type: GrantFiled: June 14, 2006Date of Patent: August 19, 2008Assignee: Macronix International Co., Ltd.Inventors: Hsiang Lan Lung, Shih-Hung Chen
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Patent number: 7394110Abstract: Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.Type: GrantFiled: February 6, 2006Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Timothy J. Dalton, Daniel C. Edelstein, Ebenezer E. Eshun, Jeffrey P. Gambino, Kevin S. Petrarca, Anthony K. Stamper, Richard P. Volant