With Switching Speed Enhancement Means (e.g., Schottky Contact) Patents (Class 257/155)
  • Patent number: 10818788
    Abstract: A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs, and a Schottky diode area including a plurality of Schottky diodes formed in the drift region having the superjunction structure. Each of the integrated Schottky diodes includes a Schottky contact between a lightly doped semiconductor layer and a metallic layer.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 27, 2020
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Yi Su, Madhur Bobde
  • Patent number: 10812064
    Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Alexander Baiocchi, Masahiko Higashi, Namiko Hagane
  • Patent number: 10644147
    Abstract: A vertical semiconductor device is provided, including a transistor region and a Schottky diode region, and having, in a gallium nitride layer in the Schottky diode region, a first well region, a diode trench portion that is provided in direct contact with the first well region in an array direction in which the transistor region and the Schottky diode region are arrayed, a first upper drift region that is connected to the bottom of the diode trench portion, a lower drift region that is connected to the bottom of the first well region and a bottom of the first upper drift region, and a conductive portion that is connected to an upper portion of the first upper drift region.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 5, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Katsunori Ueno
  • Patent number: 10490646
    Abstract: Protons are injected from a back surface side of a semiconductor substrate to repair both defects within the semiconductor substrate and also defects in a channel forming region on a front surface side of the semiconductor substrate. As a result, variation in gate threshold voltage is reduced and leak current when a reverse voltage is applied is reduced. Provided is a semiconductor device including a semiconductor substrate that includes an n-type impurity region containing protons, on a back surface side thereof; and a barrier metal that has an effect of shielding from protons, on a front surface side of the semiconductor substrate.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: November 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichi Onozawa
  • Patent number: 10418476
    Abstract: The present invention is related to a silicon carbide semiconductor device which employs a silicon carbide substrate to form an integrated device. The integrated device of the present invention comprises a metal oxide semiconductor field-effect transistor (MOSFET) and an integrated junction barrier Schottky (JBS) diode in an anti-parallel connection with the MOSFET.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: September 17, 2019
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee
  • Patent number: 10366935
    Abstract: A drive unit for a motor includes a printed circuit board (PCB); a first gallium nitride switch having a gate, the first gallium nitride switch mounted to the PCB; a second gallium nitride switch having a gate, the second gallium nitride switch mounted to the PCB; a gate driver generating a turn-off drive signal to turn off the first gallium nitride switch and turn off the second gallium nitride switch; a first turn-off trace on the PCB, the first turn-off trace directing the turn-off drive signal to the gate of the first gallium nitride switch; and a second turn-off trace on the PCB, the second turn-off trace directing the turn-off drive signal to the gate of the second gallium nitride switch; wherein an impedance of the first turn-off trace is substantially equal to an impedance of the second turn-off trace.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: July 30, 2019
    Assignee: OTIS ELEVATOR COMPANY
    Inventors: Shashank Krishnamurthy, Xin Wu, William A. Veronesi, Kyle W. Rogers, Daryl J. Marvin
  • Patent number: 10128106
    Abstract: When a defect region is present near the pn junction in a GaN layer, lattice defects are present in the depletion layer. Therefore, when a reverse bias is applied to the pn junction, the defects in the depletion layer cause the generated current to flow as a leakage current. The leakage current flowing through the depletion layer can cause a decrease in the withstand voltage at the pn junction. Provided is a semiconductor device using gallium nitride, including a gallium nitride layer including an n-type region. The gallium nitride layer includes a first p-type well region and a second p-type well region that is provided on at least a portion of the first p-type well region and has a peak region with a higher p-type impurity concentration than the first p-type well region.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo
  • Patent number: 10115834
    Abstract: A method for manufacturing an edge termination structure for a silicon carbide power semiconductor device having a central region and an edge region is provided.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 30, 2018
    Assignee: ABB Schweiz AG
    Inventor: Jan Vobecky
  • Patent number: 10090417
    Abstract: A p-type region, a p? type region, and a p+ type region are selectively disposed in a surface layer of a silicon carbide substrate base. The p-type region and the p? type region are disposed in a breakdown voltage structure portion that surrounds an active region. The p+ type region is disposed in the active region to make up a JBS structure. The p? type region surrounds the p-type region to make up a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the p-type region and this overhanging portion acts as a field plate. The p+ type region has an acceptor concentration greater than or equal to a predetermined concentration and can make a forward surge current larger.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 2, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Tsuji, Akimasa Kinoshita, Noriyuki Iwamuro, Kenji Fukuda
  • Patent number: 9941381
    Abstract: A semiconductor device having a trench MOS barrier Schottky diode includes a semiconductor volume of a first conductivity type, the semiconductor volume (i) having a first side which is covered with a metal layer, and (ii) including at least one trench which extends in the first side and is at least partially filled with metal and/or with a semiconductor material of a second conductivity type. The trench has at least one wall section which includes an oxide layer, at least in areas. At least one area, situated next to the trench, of the first side covered with the metal layer has a layer, situated between the metal layer and the semiconductor volume, made of a first semiconductor material of the second conductivity type.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: April 10, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ning Qu, Alfred Goerlach
  • Patent number: 9929244
    Abstract: A method for producing a semiconductor device includes: depositing a barrier layer on a first surface of a semiconductor body having active regions of a semiconductor device; forming a contact layer that at least partially covers the barrier layer, the barrier layer being configured to prevent a material of the contact layer from diffusing into the semiconductor body; forming a first passivation layer on the contact layer and on exposed surfaces of the barrier layer; in a first etching process, removing the first passivation layer from above the barrier layer so as to uncover sections of the barrier layer; and in a second etching process, removing at least some sections of the barrier layer uncovered by the first etching process
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: March 27, 2018
    Assignee: Infineon Technologies AG
    Inventor: Jochen Hilsenbeck
  • Patent number: 9922969
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a source in electrical communication with the substrate. A drain is also in electrical communication with the substrate. A gate overlies the substrate between the source and the drain, wherein a channel is defined within the substrate directly underlying the gate, and where a Schottky portion of the substrate is positioned between the channel and the source.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 20, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Tsung-Che Tsai, Vaddagere Nagaraju Vasantha Kumar, Wei Gao
  • Patent number: 9866214
    Abstract: This invention provides a composite device and a switching power supply. The composite device integrates therein a first enhancement-mode MOS device and a depletion-mode MOS device, and comprises: an epitaxial region of a first doping type; a first well region and a second well region formed in parallel on the front side of the epitaxial region; a first doped region of the first doping type formed within the first well region; a gate of the first enhancement-mode MOS device; a second doped region of the first doping type formed within the second well region; a channel region of the first doping type, wherein the channel region extends from a boundary of the second well region to a boundary of the second doped region; and a gate of the depletion-mode MOS device. The switching power supply includes the composite device above. This invention can decrease the process complexity, reduce the chip area and cost, and may be applicable to high power scenarios.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: January 9, 2018
    Assignee: HANGZHOU SILAN MICROELECTRONICS CO., LTD.
    Inventor: Shaohua Zhang
  • Patent number: 9865717
    Abstract: A semiconductor device includes transistor cells formed inside a semiconductor body. First and second semiconductor well regions have second conductivity type dopants and are arranged external of the transistor cells. The first semiconductor well region is arranged between two transistor cells and the second semiconductor well region is electrically connected with a load contact. A separation region has first conductivity type dopants and extends from a surface of the semiconductor body along the vertical direction and is arranged between and in contact with each of the first and second semiconductor well regions. The first semiconductor well region extends at least as deep as each of body regions of two transistor cells. A transition in a first lateral direction between the separation and first semiconductor well regions extends continuously from the surface to a point in the semiconductor body at least as deep as each body region of two transistor cells.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 9, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Stephan Voss, Frank Dieter Pfirsch
  • Patent number: 9859370
    Abstract: A Schottky barrier diode includes a semiconductor layer having a plurality of trenches formed by digging in from a top surface and having mesa portions formed between adjacent trenches, and a Schottky metal formed to contact the top surface of the semiconductor layer including inner surfaces of the trenches.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: January 2, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Yoshiteru Nagai, Kohei Makita
  • Patent number: 9741873
    Abstract: In at least one general aspect, a SiC device can include a drift region of a first conductivity type, a shielding body, and a Schottky region. The SiC device can include a rim having a second conductivity type at least partially surrounding the shielding body and the Schottky region. The SiC device can include a termination region at least partially surrounding the rim and having a doping of the second conductivity type. The termination region can have a transition zone disposed between a first zone and a second zone where the first zone has a top surface lower in depth than a depth of a top surface of the second zone and the transition zone has a recess.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 22, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • Patent number: 9716151
    Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalk and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: July 25, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Mingjiao Liu, Michael Thomason
  • Patent number: 9595584
    Abstract: [Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 14, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Katsuhisa Nagao
  • Patent number: 9548383
    Abstract: A compound semiconductor device includes a channel layer of first arsenide semiconductor, an electron supply layer of second arsenide semiconductor over the channel layer, a gate electrode, a source electrode and a drain electrode over the channel layer, and a metal film between the gate electrode and the drain electrode, the metal film being insulated from the gate electrode and the drain electrode.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: January 17, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 9443849
    Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: September 13, 2016
    Assignee: Transphorm Inc.
    Inventors: Yifeng Wu, Umesh Mishra, Srabanti Chowdhury
  • Patent number: 9425307
    Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type between the first electrode and the second electrode, a plurality of second semiconductor regions of a second conductivity type selectively provided between the first semiconductor region and the second electrode, a third semiconductor region of the first conductivity type provided between each of the second semiconductor regions and the second electrode, an insulating film provided on the first semiconductor region in a location between adjacent second semiconductor regions, the second semiconductor regions, and the third semiconductor region; and a third electrode located over the insulating film, wherein a portion of the insulating film and the third electrode extend inwardly of the second semiconductor regions.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: August 23, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Kono
  • Patent number: 9419127
    Abstract: A semiconductor device includes switching devices in an epitaxial layer on a silicon substrate. Diffusion regions of different conductivity types are provided. In some instances, an electrode layer makes ohmic contact with the epitaxial layer and extends to, and makes ohmic contact with, a diffusion region electrically connected to the epitaxial layer. In some instances, diffusion regions of different conductivity types are arranged alternately one by one outward away from the epitaxial layer side.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: August 16, 2016
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 9391190
    Abstract: A FET incorporating a Schottky diode has a structure allowing the ratio of an area in which the Schottky diode is formed and an area in which the FET is formed to be freely adjusted. A trench extending for a long distance is utilized. Schottky electrodes are interposed at positions appearing intermittently in the longitudinal direction of the trench. By taking advantage of the growth rate of a thermal oxide film formed on SiC being slower, and the growth rate of a thermal oxide film formed on polysilicon being faster, a structure can be obtained in which insulating film is formed between gate electrodes and Schottky electrodes, between the gate electrodes and a source region, between the gate electrodes and a body region, and between the gate electrodes and a drain region, and in which insulating film is not formed between the Schottky electrodes and the drain region.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: July 12, 2016
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Yukihiko Watanabe, Sachiko Aoi, Hidefumi Takaya, Atsuya Akiba
  • Patent number: 9331150
    Abstract: A semiconductor device of an embodiment includes a p-type first diamond semiconductor layer, a p-type second diamond semiconductor layer disposed on the first diamond semiconductor layer, a plurality of n-type third diamond semiconductor layers disposed on the second diamond semiconductor layer, and a first electrode disposed on the second diamond semiconductor and the third diamond semiconductor layers. The p-type second diamond semiconductor layer has a p-type impurity concentration lower than a p-type impurity concentration of the first diamond semiconductor layer and has oxygen-terminated surfaces. Each of the third diamond semiconductor layers has an oxygen-terminated surface. The first electrode forms first junctions between the first electrode and the second diamond semiconductor. The first electrode forms second junctions between the first electrode and the third diamond semiconductor layers. The first junctions and the second junctions are Schottky junctions.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 3, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai
  • Patent number: 9318566
    Abstract: In a method of fabricating a semiconductor device, a channel layer is formed on a substrate, and trench patterns are formed in the channel layer. Impurity bodies are formed in the channel layer between the trench patterns, and grooves are formed between the trench patterns in the impurity bodies formed in the channel layer. Source isolation regions are formed in the impurity bodies at bottom portions of the grooves, and source regions are formed in the impurity bodies at sidewall portions of the grooves.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., Ltd.
    Inventors: Suk-Kyun Lee, Eung-Kyu Lee
  • Patent number: 9246016
    Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 26, 2016
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Patent number: 9209293
    Abstract: Provided is an integrated device having a MOSFET cell array embedded with a junction barrier Schottky (JBS) diode. The integrated device comprises a plurality of areas, each of which includes a plurality of MOS transistor cells and at least one JBS diode. Any two adjacent MOS transistor cells are separated by a separating line. A first MOS transistor cell and a second MOS transistor cell are adjacent in a first direction and separated by a first separating line, and the first transistor cell and a third MOS transistor cell are adjacent in a second direction and separated by a second separating line. The JBS diode is disposed at an intersection region between the first separating line and the second separating line. The JBS diode is connected in anti-parallel to the first, second and third MOS transistor cells.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: December 8, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Chung Hung, Young-Shying Chen, Cheng-Tyng Yen, Chwan-Ying Lee
  • Patent number: 9184307
    Abstract: A silicon carbide semiconductor device includes: a drift layer of the a first conduction type; a guard ring region of a second conduction type formed in annular form in a portion of one surface of the drift layer; a field insulating film formed on the one surface of the drift layer and surrounding the guard ring region; a Schottky electrode covering the guard ring region and the drift layer exposed inside the guard ring region and having an outer peripheral end existing on the field insulating film; and a surface electrode pad on the Schottky electrode, wherein an outer peripheral end of the surface electrode pad comes into contact with the field insulating film over the outer peripheral end of the Schottky electrode.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: November 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichiro Tarui, Masayuki Imaizumi, Naoki Yutani
  • Patent number: 8963276
    Abstract: A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n?-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p+-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n?-type semiconductor layer. The anode electrode forms a Schottky junction with the n?-type semiconductor layer and forms an ohmic junction with the p+-type contact layer.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 24, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Watanabe, Naoki Yutani, Yoshiyuki Nakaki, Kenichi Ohtsuka
  • Patent number: 8957461
    Abstract: A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomonori Mizushima, Michio Nemoto
  • Publication number: 20140209973
    Abstract: A reverse blocking semiconductor device includes a base region of a first conductivity type and a body region of a second, complementary conductivity type, wherein the base and body regions form a pn junction. Between the base region and a collector electrode an emitter layer is arranged that includes emitter zones of the second conductivity type and at least one channel of the first conductivity type. The channels extend through the emitter layer between the base region and the collector electrode and reduce the leakage current in a forward blocking state.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Inventors: Johannes Georg Laven, Roman Baburske, Christian Jaeger, Hans-Joachim Schulze
  • Patent number: 8785970
    Abstract: A bidirectional switch controllable by a voltage between its gate and rear electrode and including an N-type semiconductor substrate surrounded with a P-type well; on the front surface side, a P-type well in which is formed a first N-type region; on the rear surface side, a P-type layer in which is formed a second N-type region. The well is doped to less than 1016 at./cm3, the exposed surfaces of this well being heavily P-type doped. At least a third P-type region, of same doping level as the well, is formed on the front surface side in the substrate, and contains at least a fourth N-type region of a doping level lower than 1017 at./cm3, on which is formed a Schottky contact.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (TOURS) SAS
    Inventor: Samuel Menard
  • Patent number: 8772836
    Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Osamu Machida
  • Patent number: 8766232
    Abstract: According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sukhun Choi, Boun Yoon, Kevin Ahn, Doo-Sung Yun
  • Patent number: 8723234
    Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiharu Takada, Kentaro Ikeda
  • Patent number: 8716748
    Abstract: A semiconductor device includes: a substrate; a semiconductor stacked structure, provided over the substrate, including an electron transit layer and an electron supply layer; a gate electrode, a source electrode, and a drain electrode provided over the semiconductor stacked structure; a gate pad, a source pad, and a drain pad provided over the gate electrode, the source electrode, and the drain electrode, and connected to the gate electrode, the source electrode, and the drain electrode, respectively; and a conductive layer provided under the gate pad, the source pad, and the drain pad, wherein a distance between the gate pad and the source pad is smaller than a distance between the gate pad and the drain pad.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: May 6, 2014
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Kazukiyo Joshin
  • Patent number: 8686505
    Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: April 1, 2014
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
  • Patent number: 8680587
    Abstract: The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.
    Type: Grant
    Filed: September 11, 2011
    Date of Patent: March 25, 2014
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
  • Patent number: 8618582
    Abstract: Elements of an edge termination structure, such as multiple concentric guard rings, are effectively doped regions in a drift layer. To increase the depth of these doped regions, individual recesses may be formed in a surface of the drift layer where the elements of the edge termination structure are to be formed. Once the recesses are formed in the drift layer, these areas about and at the bottom of the recesses are doped to form the respective edge termination elements.
    Type: Grant
    Filed: September 11, 2011
    Date of Patent: December 31, 2013
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Agarwal, John Williams Palmour, Scott Allen
  • Publication number: 20130161691
    Abstract: A semiconductor device contains a semiconductor substrate, a cathode, an anode, and a gate electrode. The semiconductor device has a cathode segment disposed in a portion corresponding to at least the cathode, an anode segment disposed in a portion corresponding to the anode, a plurality of embedded segments disposed in a portion closer to the cathode segment than to the anode segment, a takeoff segment disposed between the gate electrode and the embedded segments to electrically connect the gate electrode to the embedded segments, and a channel segment disposed between the adjacent embedded segments.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 27, 2013
    Applicant: NGK INSULATORS, LTD.
    Inventor: NGK Insulators, Ltd.
  • Publication number: 20130082302
    Abstract: A semiconductor device comprises: a substrate having a first and second surface; trenches provided on the second surface; a gate electrode provided in each trench; a first-conductive-type emitter layer provided on the second surface and contacting with the trenches; and an emitter electrode provided on the second surface to extend in a longitudinal direction of the trenches, the emitter electrode having a non-contact portion partially provided in the first-conductive-type emitter layer.
    Type: Application
    Filed: September 12, 2012
    Publication date: April 4, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazutoshi NAKAMURA, Tsuneo Ogura
  • Patent number: 8399888
    Abstract: A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 0.01%?(Concentration of Ti)/(Concentration of Al)?20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 1×1017/cm3?(Concentration of Ti)?1×1018/cm3.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: March 19, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
  • Patent number: 8390124
    Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: March 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Inoue, Yoshihiro Hayashi, Kishou Kaneko
  • Patent number: 8372738
    Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: February 12, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventor: Tinggang Zhu
  • Patent number: 8324704
    Abstract: A silicon carbide semiconductor device with a Schottky barrier diode includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide drift layer on a first surface of the substrate, a Schottky electrode forming a Schottky contact with the drift layer, and an ohmic electrode on a second surface of the substrate. The Schottky electrode includes an oxide layer in direct contact with the drift layer. The oxide layer is made of an oxide of molybdenum, titanium, nickel, or an alloy of at least two of these elements.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: December 4, 2012
    Assignees: DENSO CORPORATION, Toyota Jidosha Kabushiki Kaisha
    Inventors: Takeo Yamamoto, Takeshi Endo, Eiichi Okuno, Hirokazu Fujiwara, Masaki Konishi, Takashi Katsuno, Yukihiko Watanabe
  • Patent number: 8288795
    Abstract: Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: October 16, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 8232609
    Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Hirotaka Amasuga, Yoshitsugu Yamamoto, Youichi Nogami
  • Patent number: 8174051
    Abstract: A III-nitride power device that includes a Schottky electrode surrounding one of the power electrodes of the device.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: May 8, 2012
    Assignee: International Rectifier Corporation
    Inventors: Jianjun Cao, Yanping Ma, Robert Beach, Michael A. Briere
  • Patent number: 8174089
    Abstract: The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: May 8, 2012
    Assignee: Cree, Inc.
    Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
  • Patent number: 8125008
    Abstract: A Schottky device and a semiconductor process of making the same are provided. The Schottky device comprises a substrate, a deep well, a Schottky contact, and an Ohmic contact. The substrate is doped with a first type of ions. The deep well is doped with a second type of ions, and formed in the substrate. The Schottky contact contacts a first electrode with the deep well. The Ohmic contact contacts a second electrode with a heavily doped region with the second type of ions in the deep well. Wherein the deep well has a geometry gap with a width formed under the Schottky contact, the first type of ions and the second type of ions are complementary, and the width of the gap adjusts the breakdown voltage.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 28, 2012
    Assignee: System General Corporation
    Inventors: Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu, Long Shih Lin