Abstract: An electronic apparatus that includes a semiconductor device mounted on an assembly base is disclosed. The semiconductor device includes a transmission line, whose impedance is matched to characteristic impedance, and a pad connected to the transmission line, through which a high frequency signal is supplied to or extracted from the semiconductor device. The pad accompanies a stub line that is concurrently formed with the transmission line and grounded within the semiconductor device. The stub line operates as a short stub that may compensate parasitic capacitance attributed to the pad.

Abstract: A semiconductor device having a JFET and diode, includes a substrate, a second well region, and a second doped region that are of a first conductivity type. The JFET also includes a first well region, a first doped region, and a shared region that are of the second conductivity type. The second well region is disposed in the substrate adjacent to the first well region. A source of the JFET includes the first doped region disposed in the first well region. An anode of the diode includes the second doped region disposed in the second well region. Both a drain of the JFET and a cathode of the diode include the shared region disposed in the first well region. A diode current flows along a first lateral axis of the device while a JFET current flows along a second lateral axis of the device.

Abstract: A device for optical communication including a substrate for mounting an IC chip, and a multilayered printed circuit board. An optical path for transmitting optical signal which penetrates the substrate for mounting an IC chip is formed in the substrate for mounting an IC chip.

Abstract: A semiconductor device having an improved contact structure. The device has a semiconductor substrate and a plurality of gate structures formed on the substrate. The device has a first interlayer dielectric overlying the gate structures. The device has a first copper interconnect layer overlying the first interlayer dielectric layer. The device also has a first low K dielectric layer overlying the first copper interconnect layer. A second copper interconnect layer is overlying the low K dielectric layer. In between the first and second copper layers is a copper ring structure enclosing an entirety of an inner region of the first low K dielectric layer. In a preferred embodiment, the copper ring structure is provided between the first copper interconnect layer and the second copper interconnect layer to maintain the inner region of the first low K dielectric layer. A bonding pad structure is overlying a region within the inner region.

Abstract: In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

Abstract: Resistive cross point memory devices are provided, along with methods of manufacture and use, including a method of changing an electrically programmable resistance cross point memory bit. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: The invention concerns a vertical component with a four-layered structure comprising a thick lightly-doped zone (1) of a first type of conductivity providing the component voltage strength, enclosed with a peripheral wall (2) of a second type of conductivity extending vertically from one surface to the other of the component, and highly doped layer (3) of the second type of conductivity extending over the entire rear surface of the component. A lightly-doped layer (21) of the second type of conductivity extends over the entire surface of the component at the interface between the lightly-doped thick zone of the first type of conductivity and the highly-doped layer of the second type of conductivity.

Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.

Abstract: An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.

Abstract: A structure that reduces signal cross-talk through the semiconductor substrate for System-On-Chip (SOC) (2) applications, thereby facilitating the integration of digital circuit blocks (6) and analog circuit blocks (8) onto a single IC. Cross-circuit interaction through a substrate (4) is reduced by strategically positioning the various digital circuit blocks (6) and analog circuit blocks (8) in an isolated wells (10), (12), (16) and (20) over a resistive substrate (4). These well structures (10), (12), (16), and (20) are then surrounded with a patterned low resistivity layer (22) and optional trench region (24). The patterned low resistivity region (22) is formed below wells (10) and (12) and functions as a low resistance AC ground plane. This low resistivity region (22) collects noise signals that propagate between digital circuit blocks (6) and analog circuit blocks (8).

Abstract: A semiconductor device has: a semiconductor substrate having a surface which has a predetermined pattern, in which an insulating layer is embedded; an interlayer insulator film formed on the substrate, the interlayer insulator film having a protective coat for protecting the substrate; and an electrode formed on the interlayer insulator film. In addition, a method for manufacturing a semiconductor device comprises the steps of: forming a semiconductor substrate having a surface which has a groove in which an insulating layer is embedded; forming a protective coat for protecting the surface of the semiconductor substrate, on the upper surface of the insulating layer embedded in the groove; and forming an electrode on the protective coat.

Abstract: A semiconductor chip provided, at a lateral face thereof, with an electrode for external electric connection. Where a semiconductor chip has a plurality of electrodes, all the electrodes are preferably formed at one or more lateral faces of the semiconductor chip. Each electrode is preferably embedded in a groove which is formed in a lateral face of the semiconductor chip and which is opened laterally of the semiconductor chip. The semiconductor chip may be a discrete bipolar transistor element. In this case, each of the base electrode, the emitter electrode and the collector electrode is preferably formed at a lateral face of the semiconductor chip.

Abstract: A peripheral structure for a monolithic power device, preferably planar, includes front and rear surfaces, connected respectively to a cathode and an anode, two junctions respectively reverse-biased and forward-biased when a direct and adjacent voltage is respectively applied to the two surfaces and at least an insulating box connecting the front and rear surfaces. The structure is such that when a direct voltage or a reverse voltage is applied, generating equipotential voltage lines, the insulating box enables to distribute the equipotential lines in the substrate.

Abstract: An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved.

Abstract: A semiconductor device sets an impurity density of a p base layer in a bevel end-face region to a density lower than that in an operating region and has a parasitic channel preventive region provided between the bevel end-face region and the operating region. Since the blocking-voltage and the current-carrying capacity can be adjusted independently from each other, the blocking voltage and the current-carrying capacity can be both improved.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: A thyristor includes a semiconductor body with a surface. The semiconductor body has an inner zone of a first conduction type; a cathode-side base zone of a second conduction type opposite the first type, the base zone having a recess formed therein; a layer of the second conduction type being disposed on the surface of the semiconductor body, being disposed in the cathode-side base zone, being thinner than the cathode-side base zone, and being joined to the cathode-side base zone; and an additional zone of the second conduction type being disposed in the recess, being joined to the layer, being thicker than the layer, and being spaced apart from the cathode-side base zone.

Abstract: The sensitivity of breakdown voltage to temperature and dV/dT induced currents is reduced in semiconductor power devices having a wide base transistor. The sensitivity is reduced by diverting current from the emitter of the wide base transistor to the base of the wide base transistor (an emitter short that does not reduce breakdown voltage) or by injecting a current into the base of the wide base transistor to its collector (an injected current that may lower the breakdown voltage, but no more than that related to temperature and capacitive current). The invention finds application in both epitaxial grown and substrate based devices.

Abstract: The present invention is directed to power semiconductor devices and, more particularly, to a semiconductor device with a static induction buffer structure which reduces the resistance of a buffer layer, enhances the injection efficiency of holes from the anode and permits the application of a high-intensity electric field across the cathode and anode, and a semiconductor device with a drift buffer structure in which an impurity density (concentration) gradient is set in a buffer layer to generate an internal electric field for holes to enhance the injection efficiency of holes from the anode and increase the electron storage efficiency or and impurity density (concentration) gradient is set in an anode region to generate an internal electric field for electrons and a high-intensity electric field can be applied across the cathode and anode.

Abstract: A channel in which electron current is supplied from n.sup.+ type source layer to an n.sup.- type base layer is formed in a thyristor portion by using a first gate electrode to have an electrical connection in a thyristor state. Injection of hole current to a p type base layer, which is necessary to maintain the thyristor state is extracted to a source terminal by a control MOSFET portion including a second gate electrode a turn-off time and the state of this device is changed to the transistor state similar to that in the IGBT so that a short switching time turn-off is realized.

Abstract: Optoelectronic devices (16) are formed on a first surface (12) of a gallium arsenide substrate (10) using selective ion implantation. Signal processing devices may be formed on a second, opposite surface (14) of the substrate (10) using selective ion implantation (38) and/or selective epitaxy (22,24),(40). Vertical interconnects (34,46) are formed between the first and second surfaces (12,14). Alternatively, a gallium arsenide buffer layer (54) may be grown on the first surface (12) of the substrate (10), and the signal processing devices formed on the buffer layer (54) using selective ion implantation (58,60,62) and/or selective epitaxy (76,78,80,82). Dielectric (50) and/or conductive metal (52) layers may be formed on selected areas of the first surface (12), and the buffer layer (54) grown from exposed areas (56) of the first surface (12) over the dielectric (50) and/or metal (52) layers using lateral epitaxial overgrowth organometallic chemical vapor deposition.

Abstract: The semiconductor protection device has a p.sup.+ -n.sup.- -p-n.sup.+ layer construction, and an n type impurity diffusion region is selectively formed in a surface portion of the pn junction. This n type impurity diffusion region is formed in a linear planar portion where substantially no electric field concentration is generated when a reverse voltage is applied to the pn junction formed between the n.sup.- type semiconductor region and the p type semiconductor region. Further, an electrode is provided in ohmic contact with both of the p type semiconductor region and the n.sup.+ type semiconductor region. This electrode is selectively made in contact with the p type semiconductor region at a position remote from the n type impurity diffusion region and adjacent to a curved planar portion of the pn junction where the electric field concentration tends to occur when a reverse voltage is applied to the pn junction formed between the n.sup.- type semiconductor region and the p type semiconductor region.