Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

Abstract: A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.

Abstract: IGBT and diode are formed with optimal electrical characteristics on the same semiconductor substrate. IGBT region and FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals in the front surface of an n? type semiconductor substrate, and P-type channel regions at predetermined intervals in the longitudinal direction of the trench between neighboring trenches, thereby configuring a MOS gate. The p-type channel region and n? type drift region are alternately disposed in longitudinal direction of the trench in the IGBT region. The p-type channel region and a p? type spacer region are alternately disposed in the longitudinal direction of the trench in the FWD region. Pitch in longitudinal direction of the trench of p-type channel region in the IGBT region is shorter than pitch in longitudinal direction of the trench of p-type channel region in the FWD region.

Abstract: An integrated circuit including a first power rail, a second power rail, a power clamp connected between the first and second power rails; and a trigger circuit connected to the power clamp and the first second power rails. The trigger circuit includes an RC element formed on the basis of field effect transistors, first inverter stage connected to the RC element, a second inverter stage, and a third inverter stage. The first, second and third inverter stages are connected in series to a control input of the power clamp. The trigger circuit also included a feed back connection from an output of the second inverter stage to the first inverter stage.

Abstract: A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 0<x<1, a GaN-based carrier transit layer formed on the AlxGa1-xN layer, a carrier supply layer formed on the carrier transit layer, a source electrode and a drain electrode formed on the carrier supply layer, and a gate electrode formed on the carrier supply layer between the source electrode and the drain electrode. Therefore, a GaN-HEMT that is superior in device characteristics can be realized in the case of using a relatively less expensive conductive SiC substrate compared with a semi-insulating SiC substrate.

Abstract: A light emission package includes at least one solid state emitter, a leadframe, and a body structure encasing a portion of the leadframe. At least one aperture is defined in an electrical lead to define multiple electrical lead segments, with at least a portion of the aperture disposed outside an exterior side wall of the package. A recess may be defined in the exterior side wall to receive a bent portion of an electrical lead. A body structure cavity may be bounded by a floor, and side wall portions and end wall portions that are separated by transition wall portions including a curved or segmented upper edge, with different wall portions being disposed at different angles of inclination.

Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.

Abstract: An exemplary bipolar non-punch-through power semiconductor device includes a semiconductor wafer and a first electrical contact on a first main side and a second electrical contact on a second main side. The wafer has an inner region with a wafer thickness and a termination region that surrounds the inner region, such that the wafer thickness is reduced at least on the first main side with a negative bevel. The semiconductor wafer has at least a two-layer structure with layers of different conductivity types, which can include a drift layer of a first conductivity type, a first layer of a second conductivity type at a first layer depth and directly connected to the drift layer on the first main side and contacting the first electrical contact, and a second layer of the second conductivity type arranged in the termination region on the first main side up to a second layer depth.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (AlxGa1?xN) (where 0.1<=x<=1) placed on the nitride based compound semiconductor layer; a nitride based compound semiconductor layer placed on the aluminum gallium nitride layer (AlxGa1?xN) (where 0.1<=x<=1) and doped with a second transition metal atom; an aluminum gallium nitride layer (AlyGa1?yN) (where 0.1<=y<=1) placed on the nitride based compound semiconductor layer doped with the second transition metal atom; and a gate electrode, a source electrode, and a drain electrode which are placed on the aluminum gallium nitride layer (AlyGa1?yN) (where 0.1<=y<=1).

Abstract: Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

Abstract: Disclosed herein is a pseudomorphic high electron mobility transistor (PHEMT) power device (1) including a semi-insulating substrate (2); an epitaxial substrate (3) formed on the semi-insulating substrate (2) a contact layer (19). The contact layer (19) includes a lightly doped contact layer (20) formed on the Schottky layer (18), and a highly doped contact layer (21) formed on the lightly doped contact layer (20) and having a doping concentration higher than the lightly doped contact layer (20). The PHEMT power device (1) further includes a—wide recess (23) formed to penetrate the highly doped contact layer (21) and a narrow recess (24) formed in the wide recess (23) to penetrate the lightly doped contact layer (20). The gate electrode (6) is formed in the narrow recess (24) and in Schottky contact with the Schottky layer (18).

Abstract: The present invention discloses an integrated PMOS transistor and Schottky diode, comprising a PMOS transistor which includes a gate, a source, a drain and a channel region between the source and drain, wherein the source, drain and channel region are formed in a substrate, and a parasitic diode is formed between the drain and the channel region; and a Schottky diode formed in the substrate and connected in reverse series with the parasitic diode, the Schottky diode having one end connected with the parasitic diode and the other end connected with the source.

Abstract: A light-emitting device which comprises as one unit a semiconductor light-emitting element; a first liquid for condensing the light from the semiconductor light-emitting element; a second liquid that is separate from but contacts the first liquid; an airtight space in which at least first liquid and second liquid are disposed; and first and second electrodes to which voltage is applied so as to change the shape of the interface between first liquid and second liquid and adjust the condensed state of the light from semiconductor light-emitting element.

Abstract: A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film; forming a sidewall on an inner side surface of the opening; forming a trench in the silicon substrate by etching the silicon substrate using the first silicon oxide film, the thermal oxidation-resistant film, and the sidewall as a mask; removing the sidewall; forming a second silicon oxide film thicker than the first silicon oxide film on an inner surface of the trench by applying thermal oxidation to the silicon substrate; burying a trench gate electrode in the trench; removing the thermal oxidation-resistant film; and introducing impurities into at least part of a region of the silicon substrate between the trenches.

Abstract: A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.

Abstract: The present invention discloses a laser dicing apparatus for a gallium arsenide wafer and a method thereof, wherein firstly, a gallium arsenide wafer is stuck onto a holding film; next, the gallium arsenide wafer together with the holding film is disposed on a working table; the gallium arsenide wafer has multiple chips or dice with a scribed line drawn between every two chips; a control device and an object lens are used to position the working table and a laser, and two video devices are used to observe whether the laser has been precisely aimed at one of the scribed lines; after parameters have been input into the control device, the laser is used to cut the gallium arsenide wafer, and the gallium arsenide wafer is then separated into multiple discrete chips or dice. The present invention can precisely cut gallium arsenide wafers, reduce the cost and accelerate the fabrication process.

Abstract: A thin film EL device is disclosed which includes a hole-injecting electrode, an electron-injecting electrode paired with the hole-injecting electrode, and a functional layer provided between the hole-injecting electrode and the electron-injecting electrode and emitting light by application of an electric field produced by the electrodes. The electron-injecting electrode contains at least two or more different metals having different work functions and a capturing substance for capturing a low work function metal, which is a metal other than a highest work function metal among the above-described metals, in its ionic state. This configuration prevents deterioration of the low work function metal, increasing the luminance and lifetime of the device.

Abstract: Valve sealing assemblies and methods of sealing a valve engaging member to a valve body. A first seat member is fixedly disposed within a valve body pocket. Two seal rings are disposed between a valve pocket and a pocket insert and a seal ring is disposed between the pocket insert and a seat member to provide a downstream seal. A built-in lip on one of the seat members and an accommodating groove on the other seat member prevent debris from entering the space between the two seat members. A retainer ring on the exterior annular surface of pocket insert seat member retains the pocket insert within valve body. A retainer ring on the exterior annular surface of the seat member retains the seat member within the pocket insert.

Abstract: A method for manufacturing a hetero-junction field effect transistor (HFET) device, which includes sequentially forming a non-doped GaN semiconductor layer and an AlGaN semiconductor layer on a substrate, separating devices from each other by etching the substrate, forming a photoresist layer pattern on the AlGaN semiconductor layer and forming gate electrodes by depositing a material on the substrate using the photoresist layer pattern, treating the surface of the AlGaN semiconductor layer, and forming a photoresist layer pattern on the substrate and forming ohmic electrodes by depositing a metal on the substrate using the photoresist layer pattern, is provided. Accordingly, it is possible to overcome a difficulty in aligning the gate electrode with the ohmic electrodes and prevent a substrate from having a step difference introduced by the ohmic electrodes because the gate electrode is formed before the ohmic electrodes are formed.

Abstract: An on-chip voltage sensor that selectively eliminates noise from a voltage measurement is provided. The on-chip voltage sensor has resistive and capacitive components in the voltage divider, thus allowing a voltage on a section of a computer chip to be measured exclusive of high-frequency noise. Further, a method for measuring a voltage on a section of a computer chip using a voltage divider having a resistor and a capacitor is provided. Further, a computer chip having an on-chip voltage sensor is provided. Further, a method and apparatus for observing voltages at multiple locations on an integrated circuit.

Abstract: In a hetero junction structure having an AlxGa1−x As layer 10 (0<x≦1), on which an AlyGa1−yAs layer (0≦y≦1 and y<x) is provided as having a band gap smaller than that of the AlxGa1−xAs layer 10 and a valence band energy larger than that of the AlxGa1−xAs layer 10, when the AlyGa1−yAs layer is selectively etched, an Au electrode film 16 is formed on a surface of the AlyGa1−yAs layer outside an etching region 14, a resist pattern 18 is formed so as to cover the Au electrode film 16 and expose the etching region 14, and the AlyGa1−yAs layer is selectively removed through the mask of the resist pattern 18 under irradiation of light by use of an etching solution having a Fermi level higher than that of the AlyGa1−yAs layer.

Abstract: A semiconductor device includes a substrate and a semiconductor layer of a first conductivity type, formed over the substrate via an insulating layer, the semiconductor layer having a protective diode. The protective diode has a first diffusion layer of a second conductivity type, formed in the semiconductor layer, a second diffusion layer of the second conductivity type, formed in the semiconductor layer, the second diffusion layer being isolated from the first diffusion layer, a third diffusion layer of the first conductivity type, formed in a region of the semiconductor layer, the region being sandwiched between the first and the second diffusion layers, the third diffusion layer being contact with the second diffusion layer, a first electrode formed as being contact with the first diffusion layer and a second electrode formed as being contact with the second and the third diffusion layers.

Abstract: An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

Abstract: A Zener diode (11) is provided in a chip periphery portion (CPP) which entirely surrounds the periphery of a unit cell portion (UCP) and the periphery of a gate pad portion (GPP) along first to fourth directions (D1) to (D4). The Zener diode (11) has an N+-P-N+-P-N+ structure consisting of an N+ type layer (1B), a P type layer (33), an N+ type layer (32), a P type layer (31) and an N+ type layer (1A), in which these layers extend along the first to fourth directions (D1) to (D4). With this structure, (1) achieving reduction in on-state resistance through enlargement of an effective cell region by downsizing the gate pad and (2) ensuring an improvement in current-voltage characteristic of the Zener diode through an increase in PN junction width, a power semiconductor device having higher electrostatic strength is obtained.

Abstract: The semiconductor device includes a semiconductor base body (11) formed of a damaged layer (102) serving as a gettering layer, a P+ collector layer (103), an N+ buffer layer (104), and an N− layer (105) laid one on top of another, a gate electrode (27) selectively formed on the upper main surface of the semiconductor base body (11) specifically on the external main surface of the N− layer (105), with a gate insulating film (26) interposed therebetween, an emitter electrode (28) selectively formed on the upper main surface of the semiconductor base body (11), and a collector electrode (106) formed on the lower main surface of the semiconductor base body (11), specifically on the external main surface of the damaged layer (102).

Abstract: A semiconductor device has first and second electrical terminals. The device comprises at least one n/p or p/n first junction adjacent the first terminal, and at least one of the other of a p/n or n/p second junction adjacent the second terminal. It also has at least one n/p or p/n junction disposed between the first and second junctions and arranged to be transverse thereto, and at least one gate terminal in contact with the p or n doped region of the first junction or the n or p doped region of the second junction.

Abstract: A power MOSFET includes a pair of electrically isolated gates having different gate widths. The MOSFET is connected in a switching mode DC-DC converter, with the gates being driven by a pulse width modulation (PWM) control to vary the duty cycle of the gate drive signal and thereby regulate the output voltage of the DC-DC converter. In light load conditions, the larger gate is disconnected from the PWM control to reduce the gate capacitance which must be driven by the PWM control. In normal load conditions, the larger gate is connected to the PWM control to reduce the on-resistance of the MOSFET. Both of these operations increase the efficiency of the DC-DC converter.

Abstract: A field-effect-controllable semiconductor component includes a semiconductor body with first and second surfaces. An inner zone of a first conduction type adjoins the first surface. An anode zone of the opposite, second conduction type adjoins the inner zone in the direction of the first surface and adjoins the second surface in the opposite direction. At least one first base zone of the second conduction type is embedded in the first surface. At least one source zone of the first conduction type is embedded in the first surface. At least one source electrode makes contact with the base zones and the source zones. At least one gate electrode is insulated from the semiconductor body and the source electrode by a gate oxide and at least partly covers parts of the first base zones appearing at the first surface. Intermediate cell zones contain the source zones. Trenches enclose the intermediate cell zones and are insulated from the intermediate cell zones by a gate oxide.

Abstract: An insulated gate thyristor is provided which includes a first-conductivity-type base layer of high resistivity, first and second second-conductivity-type base regions formed in a surface layer of a first major surface of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region, a gate electrode formed on surfaces of the first second-conductivity-type base region, the first-conductivity-type base layer, and the second second-conductivity-type base region, which surfaces are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region, an insulating film interposed between the gate electrode and these surface of the base regions and layer, a first main electrode in contact with both the first second-conductivity-type base region and the first-conduct

Abstract: In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

Abstract: In a semiconductor device and a method of manufacturing the same, the semiconductor device is provided with an n.sup.+ -type layer located between an n-type buffer layer and a p-type collector layer and having a higher impurity concentration than n-type buffer layer. A diffusion depth of p-type collector layer toward a first main surface is smaller in a first region and is larger in a second region. As a result, the semiconductor device has a sufficiently reduced turn-off loss.

Abstract: It is an object to obtain an insulated gate semiconductor device with an unreduced current value capable of being turned off while adopting structure for reducing the ON voltage, and a manufacturing method thereof. An N layer (43) is provided in close contact on a surface of an N.sup.- layer (42), a P base layer (44) is provided in close contact on the surface of the N layer (43), and a trench (47) which passes at least through the P base layer (44) is provided, and a gate electrode (49) is provided in the trench (47) through a gate insulating film (48). The carrier distribution of the N.sup.- layer (42) becomes closer to the carrier distribution of a diode, and an ON voltage is decreased and a current value capable of being turned off is not decreased when turning off. Accordingly, there are provided an insulated gate semiconductor device with low power consumption, small size, large capacity and high reliability.

Abstract: A GTO is specified which, starting from the anode-side main surface (2), comprises an anode emitter (6), a barrier layer (11), an n-base (7), a p-base (8) and a cathode emitter (9). The anode emitter (6) is designed as a transparent emitter and has anode short-circuits (10). By virtue of the combination of the barrier layer, the transparent anode emitter and the anode short-circuits, a GTO is obtained which can be operated at high switching frequencies, the substrate thickness of which can be reduced and which nevertheless exhibits no increase in the switching losses.

Abstract: In a complex semiconductor device, an IGBT and a thyristor are formed in an identical semiconductor substrate to be connected in parallel with each other between main electrodes such that an end of the thyristor on the cathode side is connected to the main electrode via an insulated gate electrode of the IGBT. Thanks to the complex of the IGBT and the thyristor, there is attained a semiconductor device having a satisfactory ignition characteristic, a low on-state voltage, and a high breakdown voltage.

Abstract: A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: A GTO having a cathode emitter (7) is specified, which cathode emitter has a low emission efficiency. This cathode emitter (7) provides a clearly increased resistance to the formation of current filaments. As a result, relatively high turn-off current densities can be reliably mastered. In addition, the fraction of the hole current in the total current is more than 10%. This is achieved, for example, by selecting the penetration depth as <1 .mu.m and the edge concentration as <10.sup.19 cm.sup.-3.

Abstract: A semiconductor device thyristor structure includes a first conductive type collector region, second conductive type and first conductive type base regions, and a second conductive type emitter region. First conductive type regions and second conductive type regions have respective first and second type majority carriers. A first MOSFET injects the second type majority carriers into the second conductive type base region. A second MOSFET is opened and closed independent of the first MOSFET and extracts the first type majority carriers from the first conductive type base region. A third MOSFET has a first gate electrode which is also a gate electrode of the first MOSFET, for extracting the first type majority carriers from the first conductive type base region. First conductive type and second conductive type emitter regions are formed within the first conductive type base region and an emitter voltage can be simultaneously applied to these emitter regions.

Abstract: The semiconductor device is formed of an EST part and an IGBT part, wherein the EST part has a first MOSFET and a second MOSFET synchronously switching, and the IGBT part has a third MOSFET controllable independently from them. At a turn-off of the semiconductor device, when turning off the first and second MOSFETs while keeping the third MOSFET at an on-state, IGBT operation remains. Thus, the current path which tends to flow to an emitter region changes toward an emitter electrode side even if the recovery of the potential barrier is late due to the junction in the emitter region, and the charge accumulation to the emitter region is restrained. After the potential barrier is recovered, the third MOSFET is turned off. Controllable turn-off current can be enlarged and turn-off time can be shortened.

Abstract: Between electrodes (9) and (10) are formed a p.sup.+ substrate (2), an n.sup.- epitaxial layer (1) having a protruding portion (3), an n.sup.+ diffusion region (4) and p.sup.+ diffusion regions (13). Control electrodes (6) are formed on insulating films (5) on opposite sides of the protruding portion (3) and n.sup.+ diffusion region (4). The potential at the control electrodes (6) is increased or decreased with the potential at an electrode (10) increased relative to an electrode (9) to generate potential barrier or conductivity modulation in the n.sup.- epitaxial layer (1), whereby a semiconductor device turns off or on. Introduced holes are drawn through the p.sup.+ diffusion regions (13) when the semiconductor device turns off, to provide a small resistance and a short distance when the holes are drawn without changes in the area of the n.sup.+ diffusion region (4). This permits the semiconductor device to have small switching loss and high switching speed with a low ON-voltage.