Abstract: A memory cell is disclosed. The memory cell includes a storage component that includes a chalcogenide stack that includes a plurality of layers of material and a selector component that includes a Schottky diode.

Abstract: A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

Abstract: The present invention provides various aspects for processing multiple types of substrates within cleanspace fabricators or for processing multiple or single types of substrates in multiple types of cleanspace environments. In some embodiments, a collocated composite cleanspace fabricator may be capable of processing semiconductor devices into integrated circuits and then performing assembly operations to result in product in packaged form. Customized smart devices, smart phones and touchscreen devices may be fabricated in examples of a cleanspace fabricator. In some examples, the smart devices, smart phones and touchscreen devices may have two touchscreens on opposite sides of the device along with hardware based encryption.

Abstract: A semiconductor device or a crystal that suppresses phase transition of a corundum structured oxide crystal at high temperatures is provided. According to the present invention, a semiconductor device or a crystal structure is provided, including a corundum structured oxide crystal containing one or both of indium atoms and gallium atoms, wherein the oxide crystal contains aluminum atoms at least in interstices between lattice points of a crystal lattice.

Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.

Abstract: A nonvolatile memory device includes a plurality of first electrode lines including upper portions that have convex top surfaces. A plurality of second electrode lines are disposed over the plurality of first electrode lines to cross the plurality of first electrode lines, and a plurality of memory patterns are disposed between the plurality of first electrode lines and the plurality of second electrode lines.

Abstract: Control elements that can be suitable for nonvolatile memory device applications are disclosed. The control element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The control element can be based on multilayer dielectric stacks. The control element can include a titanium oxide-carbon-doped silicon-titanium oxide multilayer stack. Electrode materials may include one of ruthenium, titanium nitride, or carbon. The titanium oxide layers may be replaced by one of zirconium oxide, hafnium oxide, aluminum oxide, magnesium oxide, or a lanthanide oxide.

Abstract: Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.

Abstract: A semiconductor light-emitting element manufacturing method including: a first step in which a first n-type semiconductor layer is laminated onto a substrate in a first organometallic chemical vapor deposition apparatus; and a second step in which a regrowth layer, a second n-type semiconductor layer, an active layer, and a p-type semiconductor layer are sequentially laminated onto the aforementioned first n-type semiconductor layer in a second organometallic chemical vapor deposition apparatus.

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract: A semiconductor device according to the present invention includes: an unit element which includes a first switch and a second switch, wherein each of the first switch and the second switch includes an electrical resistance changing layer whose state of electrical resistance is changed according to a polarity of an applied voltage, and each of the first switch and the second switch has two electrodes, and wherein one electrode of the first switch and one electrode of the second switch are connected each other to form a common node, and the other electrode of the first switch forms a first node, and the other electrode of the second switch forms a second node; a first wiring which is connected with the first node and forms a signal transmission line; and a second wiring which is connected with the second node and is connected with the first wiring through the unit element.

Abstract: A nonvolatile memory element (20) of the present invention comprises a resistance variable element (14) and a diode (18) which are formed on a substrate (10) such that the resistance variable element (14) has a resistance variable layer (11) sandwiched between a lower electrode (12) and an upper electrode (13), and the diode (18) which is connected in series with the resistance variable element (14) in the laminating direction and has an insulating layer or semiconductor layer (15) sandwiched between a first electrode (16) at the lower side and a second electrode (17) at the upper side. The resistance variable layer (11) is embedded in a first contact hole (21) formed on the lower electrode (12).

Abstract: The present application provides a thin film transistor and a method of manufacturing same capable of suppressing diffusion of aluminum to oxide semiconductor and selectively etching oxide semiconductor and aluminum oxide. The thin film transistor includes: a gate electrode; a channel layer whose main component is oxide semiconductor; a gate insulating film provided between the gate electrode and the channel layer; a sealing layer provided on the side opposite to the gate electrode, of the channel layer; and a pair of electrodes which are in contact with the channel layer and serve as a source and a drain. The sealing layer includes at least a first insulating film made of a first insulating material, and a second insulating film made of a second insulting material having etching selectivity to each of the oxide semiconductor and the first insulating material and provided between the first insulating film and the channel layer.

Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.

Abstract: A germanium semiconductor radiation detector contact made of yttrium metal. A thin (˜1000 ?) deposited layer of yttrium metal forms a thin hole-barrier and/or electron-barrier contact on both p- and n-type germanium semiconductor radiation detectors. Yttrium contacts provide a sufficiently high hole barrier to prevent measurable contact leakage current below ˜120 K. The yttrium contacts can be conveniently segmented into multiple electrically independent electrodes having inter-electrode resistances greater than 10 G?. Germanium semiconductor radiation detector diodes fabricated with yttrium contacts provide good gamma-ray spectroscopy data.

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract: Provided is a thin film transistor and thin film transistor panel array. The thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate and partially overlapping with the gate electrode; a source electrode and a drain electrode spaced apart from each other with respect to a channel region of the semiconductor layer; an insulating layer disposed between the gate electrode and the semiconductor layer; and a barrier layer disposed between the semiconductor layer and the source electrode and between the semiconductor layer and the drain electrode, in which the barrier layer comprises graphene. An ohmic contact is provided based on the type of material used for the semiconductor layer.

Abstract: Memory cells are described along with arrays and methods for manufacturing. An embodiment of a memory cell as described herein includes a second doped semiconductor region on a first doped semiconductor region and defining a pn junction therebetween. A first electrode on the second doped semiconductor region. An insulating member between the first electrode and a second electrode, the insulating member having a thickness between the first and second electrodes. A bridge of memory material across the insulating member, the bridge having a bottom surface and contacting the first and second electrodes on the bottom surface, and defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the thickness of the insulating member, wherein the memory material has at least two solid phases.

Abstract: The present invention relates to an apparatus combining bypass diode and wire. According to the present invention, the bypass diode can connect with the wire directly. It is not necessary to reserve an extra region on the substrate of the solar cell as the wire soldering area. Thereby, the required area of the ceramic substrate is reduced, and hence lowering the manufacturing cost of the solar cell substantially.

Abstract: Provided is a bottle opener. The bottle opener includes a handle, a body, a cap retaining portion, a force accumulation deforming portion, and a travel limiter. The handle is for a user to grasp. The body is installed on the handle. The cap retaining portion is formed on the body and contacts a side of a bottle cap. The force accumulation deforming portion is provided on the body and is elastically deformed by external pressure. The travel limiter is provided between the force accumulation deforming portion and the handle, and receives part of the force accumulation deforming portion to control a range of elastic deformation.

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: An electrical generator includes a substrate, a semiconductor piezoelectric structure having a first end and an opposite second end disposed adjacent to the substrate, a first conductive contact and a second conductive contact. The structure bends when a force is applied adjacent to the first end, thereby causing an electrical potential difference to exist between a first side and a second side of the structure. The first conductive contact is in electrical communication with the first end and includes a material that creates a Schottky barrier between a portion of the first end of the structure and the first conductive contact. The first conductive contact is also disposed relative to the structure in a position so that the Schottky barrier is forward biased when the structure is deformed, thereby allowing current to flow from the first conductive contact into the first end.

Abstract: A thin film transistor (TFT), a method of fabricating the TFT, and a flat panel display having the TFT, wherein the TFT includes a substrate; a gate electrode provided on the substrate; a gate insulating layer provided on the gate electrode; a source electrode and a drain electrode provided on the gate insulating layer and insulated from the gate electrode; and an organic semiconductor layer contacting the source and drain electrodes and insulated from the gate electrode.

Abstract: A resistive memory device is provided. The resistive memory device includes a bottom electrode, a resistance-variable layer, and a top electrode. The resistance-variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance-variable layer. The resistance-variable layer includes a conductive polymer layer that reacts with the top electrode to form an oxide layer.

Abstract: A nonvolatile memory device includes a plurality of component memory layers stacked on one another. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring, and a stacked structure unit provided between the first wiring and the second wiring. The stacked structure unit has a memory layer and a rectifying element. The rectifying element has a Schottky junction formed on an interface between an electrode and an oxide semiconductor. The electrode includes a metal and the oxide semiconductor includes a metal.

Abstract: A method of fabricating a chalcogenide memory cell is described. The cross-sectional area of a chalcogenide memory element within the cell is controlled by the thickness of a bottom electrode and the width of a word line. The method allows the formation of ultra small chalcogenide memory cells.

Abstract: A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal.

Abstract: An integrated circuit package system is provided including providing an integrated circuit die having a contact pad, forming a protection cover over the contact pad, forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover, developing a conductive layer over the passivation layer, and forming a pad opening in the protection cover for exposing the contact pad.

Abstract: An organic light-emitting transistor having a source electrode layer; a drain electrode layer facing the source electrode layer; an organic light-emitting layer formed between the source electrode layer and the drain electrode layer; a semiconductor layer formed between the organic light-emitting layer and the source electrode layer; and a gate electrode layer deposited to face through a gate insulation film to one face of the source electrode layer opposite to the other face facing the drain electrode layer. The organic light-emitting transistor further comprises: a charge-carrier suppression layer formed between the organic light-emitting layer and the source electrode layer to have an aperture; and a relay region formed between the charge-carrier suppression layer and the source electrode layer to relay charge-carriers from the source electrode layer to the aperture.

Abstract: A semiconductor probe having a wedge shape resistive tip and a method of fabricating the semiconductor probe is provided. The semiconductor probe includes a resistive tip that is doped with a first impurity, has a resistance region doped with a low concentration of a second impurity having an opposite polarity to the first impurity, and has first and second semiconductor electrode regions doped with a high concentration of the second impurity on both side slopes of the resistive tip. The probe also includes a cantilever having the resistive tip on an edge portion thereof, and an end portion of the resistive tip has a wedge shape.

Abstract: To provide a semiconductor layer in which a GaN system epitaxial layer having high crystal quality can be obtained. The semiconductor layer includes a ?-Ga2O3 substrate 1 made of a ?-Ga2O3 single crystal, a GaN layer 2 formed by subjecting a surface of the ?-Ga2O3 substrate 1 to nitriding processing, and a GaN growth layer 3 formed on the GaN layer 2 through epitaxial growth by utilizing an MOCVD method. Since lattice constants of the GaN layer 2 and the GaN growth layer 3 match each other, and the GaN growth layer 3 grows so as to succeed to high crystalline of the GaN layer 2, the GaN growth layer 3 having high crystalline is obtained.

Abstract: A device includes a first semiconductor chip and a second semiconductor chip which are connected to each other in an electrically conductive manner via a bonding wire, the bonding wire having a contact to the first semiconductor chip at a first contact point and having a contact to the second semiconductor chip at a second contact point, and the device including a further bonding wire which has a further first contact point and a further second contact point, a maximum distance between the bonding wire and a direct connecting line between the first and second contact points perpendicular to the connecting line being greater than a further maximum distance between the further bonding wire and a further connecting line between the further first contact point and the further second contact point perpendicular to the further connecting line.

Abstract: Disclosed is a composition for preparing an organic insulator, including an organic silane material, having a vinyl group, an acetylene group or an acryl group as a functional group for participating in a crosslinking reaction, a crosslinking agent, and a solvent for dissolving the above components. The organic insulator of example embodiments may be provided in the form of a solid insulating film, which may increase charge mobility while decreasing the threshold voltage and operating voltage of OTFTs, and which also may generate relatively slight hysteresis.

Abstract: The present invention relates to a transistor for selecting a storage cell and a switch using a solid electrolyte. In a storage cell, a metal is stacked on a drain diffusion layer of a field-effect transistor formed on a semiconductor substrate surface. The solid electrolyte using the metal as a carrier is stacked on the metal. The solid electrolyte contacts with the metal via a gap, and the metal is connected to a common grounding conductor. A source of the field-effect transistor is connected to a column address line, and a gate of the field-effect transistor is connected to a row address line.

Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming a cup-shaped electrode on sidewalls of an opening in an insulation layer and through the opening on an ohmic layer that is stacked on a conductive structure. An insulation filling member is formed that at least partially fills an interior of the electrode. The insulation filling member is formed within a range of temperatures that is sufficiently low to not substantially change resistance of the ohmic layer. A variable resistivity material is formed on the insulation filling member and is electrically connected to the electrode.

Abstract: The present invention describes a method of and an apparatus for providing a wafer, the wafer including Silicon; etching trenches in the wafer to form Silicon fins; filling Silicon Oxide in the trenches; planarizing the Silicon Oxide; recessing the Silicon Oxide to a first thickness to form exposed Silicon pedestals from the Silicon fins; depositing SiGe over the exposed Silicon pedestal; recessing the Silicon Oxide to a second thickness; undercutting the exposed Silicon pedestals to form necked-in Silicon pedestals; oxidizing thermally and annealing the SiGe; and forming Germanium nanowires.

Abstract: A circuit board includes: a substrate; source and drain electrodes formed on the substrate; an organic semiconductor layer formed on the source and drain electrodes; a gate insulating layer formed on the organic semiconductor layer; and a gate electrode formed on the gate insulating layer, wherein: the substrate includes a first part, a second part, and a third part interposed between the first and second parts and a thickness of the first part or a thickness of the second part is greater than that of the third part; the source electrode is formed on the first part; the drain electrode is formed on the second part; a part of the organic semiconductor layer is formed on the third part; and a thickness of the gate insulating layer disposed on the first and second parts is smaller than that of the gate insulating layer disposed on the third part.

Abstract: A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal.

Abstract: A nanometric device is disclosed for the measurement of the electrical conductivity of individual molecules and their quantum effects having: a substrate surmounted by, in order, a barrier to diffusion layer, an electrically conductive layer, a “bounder” layer and an electrically insulating layer; and a suitable miniaturized probe; wherein the “bounder” layer and the electrically insulating layer have at least one nanometric pore formed within, the base of which consists of the electrically conductive layer. A method for the production of a nanometric device for the measurement of the electrical conductivity of individual molecules and their quantum effects, and a method for the measurement of the electrical conductivity and quantum effects of a molecule of interest, are also disclosed.

Abstract: An electrical generator includes a substrate, a semiconductor piezoelectric structure having a first end and an opposite second end disposed adjacent to the substrate, a first conductive contact and a second conductive contact. The structure bends when a force is applied adjacent to the first end, thereby causing an electrical potential difference to exist between a first side and a second side of the structure. The first conductive contact is in electrical communication with the first end and includes a material that creates a Schottky barrier between a portion of the first end of the structure and the first conductive contact. The first conductive contact is also disposed relative to the structure in a position so that the Schottky barrier is forward biased when the structure is deformed, thereby allowing current to flow from the first conductive contact into the first end.

Abstract: Provided is an electronic device, a field effect transistor having the electronic device, and a method of manufacturing the electronic device and the field effect transistor. The electronic device includes: a substrate; a first electrode and a second electrode which are formed in parallel to each other on the substrate, each of the first electrode and the second electrode comprising two electrode pads separated from each other and a heating element that connect the two electrode pads; a catalyst metal layer formed on the heating element of the first electrode; and a carbon nanotube connected to the second electrode by horizontally growing from the catalyst metal layer; wherein the heating elements are separated from the substrate by etching the substrate under the heating elements of the first and the second electrodes.

Abstract: A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract: A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer underlying the first device region and joining the sinker region, a deep guard ring substantially encircling the sinker region, and a deep trench oxide region substantially encircling the sinker region. The isolation structure further includes a wide guard ring between the first and the second device regions. The sinker region and the buried region preferably have a high impurity concentration. Integrated circuits to be noise decoupled are preferably formed in the respective first and second device regions.

Abstract: The invention provides for a write-once nonvolatile memory array, the memory cells comprising a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. The initial, unprogrammed state of each memory cell is a crystalline, low-resistance state, while the programmed state is an amorphous, high-resistance state. Optimizing the circuitry for a write-only memory array, the wordlines or bitlines can be long, with at least 256 cells on a wordline or bitline, and in some embodiments, having thousands of cells on a wordline or bitline. In a preferred embodiment, such an array can be a monolithic three dimensional memory array comprising stacked memory levels.

Abstract: A nano-elastic memory device and a method of manufacturing the same. The nano-elastic memory device may include a substrate, a plurality of lower electrodes arranged in parallel on the substrate, a support unit formed of an insulating material to a desired or predetermined thickness on the substrate having cavities that expose the lower electrodes, a nano-elastic body extending perpendicular from a surface of the lower electrodes in the cavities, and a plurality of upper electrodes formed on the support unit and perpendicularly crossing the lower electrodes over the nano-elastic bodies.

Abstract: A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.

Abstract: The difficulty of miniaturization of large-scale integrated circuits in electric devices based on the conventional techniques involving three-dimensional device structures or the introduction of novel materials is solved. Wires 2 and 3 are disposed to intersect one another in midair in a matrix. The ends of the wires 2 and 3 in midair are designed to be in direct contact with the insides of a package which contains a semiconductor device so that electrical connection and/or physical support can be acquired. Cross point 1 where wires 2 and 3 are in contact with each other is a region which has current switching function similar to the function of a channel of a common MOSFET. Cross point 1 is a region where base wire 2 functioning as a substrate and gate electrode wire 3 functioning as a control electrode (gate electrode) intersect in contact with one another, or a region where base wire 2 and a lead wire 4 overlap.

Abstract: An organic transistor is capable of emitting light at high luminescence efficiency, operating at high speed, handling large electric power, and can be manufactured at low cost. The organic transistor includes an organic semiconductor layer between a source electrode and a drain electrode, and gate electrodes shaped like a comb or a mesh, which are provided at intervals approximately in the central part of the organic semiconductor layer approximately parallel to the source electrode and the drain electrode. The organic semiconductor layer consists of an electric field luminescent organic semiconductor material such as compounds of naphthalene, anthracene, tetracene, pentacene, hexacene, a phthalocyanine system compound, an azo system compound, a perylene system compound, a triphenylmethane compound, a stilbene compound, poly N-vinyl carbazole, and poly vinyl pyrene.