Abstract: A photodetector includes a two-terminal bipolar phototransistor arranged on a substrate. The phototransistor includes a base, a collector, and an emitter. An electrical connection is made between the base and the local substrate near a region of the phototransistor. The electrical connection can be by way of metal interconnects.

Abstract: It will be understood that in some embodiments, nitrogen-containing ligands bonded to the silicon may not necessarily be identical to another nitrogen-containing ligand bonded to the same silicon atom. For example, in some embodiments, R1 and R2 may be different alkyl ligands. In some embodiments, a first NR1R2 ligand attached to a silicon atom may not be the same as or have the same alkyl ligands as another NR1R2 ligand attached to the same silicon atom. As noted above, R1 and R2 may be any alkyl ligand.

Abstract: A thin film, a method of forming the thin film, a semiconductor device including the thin film, and a method of manufacturing the semiconductor device include forming a thin film including a metal oxynitride, and treating the thin film with inert gas ions so as to stabilize properties of the thin film. The metal oxynitride may include zinc oxynitride (ZnOxNy). The inert gas ions may include at least one of Ar ions and Ne ions. The treating of the thin film with the inert gas ions may be performed by a sputtering process, a plasma treatment process, or the like.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract: A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.

Abstract: A method for manufacturing a structure having a textured surface, including a substrate made of mineral glass having a given texture, for an organic-light-emitting-diode device, the method including supplying a rough substrate, having a roughness defined by a roughness parameter Ra ranging from 1 to 5 ?m over an analysis length of 15 mm and with a Gaussian filter having a cut-off frequency of 0.8 mm; and depositing a liquid-phase silica smoothing film on the substrate, the film being configured to smooth the roughness sufficiently and to form the textured surface of the structure.

Abstract: A vertical semiconductor component having a semiconductor body, which has an inner region and an edge region that is arranged between the inner region and an edge of the semiconductor body. At least one semiconductor junction between a first semiconductor zone of a first conduction type, said first semiconductor zone being arranged in the region of a first side of the semiconductor body in the inner region, and a second semiconductor zone of the second conduction type, said second semiconductor zone adjoining the first semiconductor zone in the vertical direction.

Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.

Abstract: A power supply device is disclosed that is able to satisfy the power requirements of a device in service and has high efficiency. The power supply device includes a first power supply; a voltage step-up unit that steps up an output voltage of the first power supply; a voltage step-down unit that steps down an output voltage of the voltage step-up unit; and a load that is driven to operate by an output voltage of the voltage step-down unit. The voltage step-up unit steps up the output voltage of the first power supply to a lower limit of an operating voltage of the voltage step-down unit.

Abstract: A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line.

Abstract: A rectenna capable of power conversion from electromagnetic (EM) waves of high frequencies is provided. In one embodiment, a rectenna element generates currents from two sources—based upon the power of the incident EM wave and from an n-type semiconductor, or another electron source attached to a maximum voltage point of an antenna element. The combined current from both sources increases the power output of the antenna, thereby increasing the detection sensitivity of the antenna of a low power signal. Full wave rectification is achieved using a novel diode connected to a gap in the antenna element of a rectenna element. The diode is conductive at forward bias voltage or reverse bias voltage, and rectifies the antenna signal generated by the desired EM wave received by antenna raise from The rectenna element of the present invention may be used as a building block to create large rectenna arrays.

Abstract: Provided is a semiconductor device including: a silicon substrate; at least two trenches spaced apart from each other, being in parallel with each other, and being formed by vertically etching the silicon substrate from a surface thereof; an electrically insulating film for burying therein at least bottom surfaces of the trenches; a base region formed in a region of the silicon substrate located between the two trenches; and an emitter region and a collector region formed on portions of side surfaces of the trenches, respectively, the portions of the sides located above the insulating film and formed in the base region.

Abstract: A power supply device is disclosed that is able to satisfy the power requirements of a device in service and has high efficiency. The power supply device includes a first power supply; a voltage step-up unit that steps up an output voltage of the first power supply; a voltage step-down unit that steps down an output voltage of the voltage step-up unit; and a load that is driven to operate by an output voltage of the voltage step-down unit. The voltage step-up unit steps up the output voltage of the first power supply to a lower limit of an operating voltage of the voltage step-down unit.

Abstract: A power semiconductor device includes a semiconductor substrate having a plurality of trenches formed in an upper surface thereof; a buried insulating film; a buried field plate electrode; a control electrode; a first main electrode provided on a lower side of the semiconductor substrate; and a second main electrode provided on an upper side of the semiconductor substrate. The semiconductor substrate includes: a first semiconductor; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type; a fourth semiconductor layer; and a fifth semiconductor layer. The buried insulating film is thicker than a gate insulating film. At least one of the second semiconductor layer and the third semiconductor layer has a portion with its sheet dopant concentration varying along a depth direction of the semiconductor substrate.

Abstract: A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer.

Abstract: With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the source. The MOFROM is completely compatible with the mainstream standard CMOS process. The standard MOSFET presents an “OFF” state before the burning and an “ON” state with a stable low-resistance path after the burning.

Abstract: An ultraviolet type white color light emitting device (Q) including a 340 nm-400 nm ultraviolet InGaN-LED, a first fluorescence plate of ZnS doped with more than 1×1017 cm?3 Al, In, Ga, Cl, Br or I for absorbing ultraviolet rays and producing blue light (fluorescence), a second fluorescence plate of ZnSSe or ZnSe doped with more than 1×1017 cm?3 Al, In, Ga, Cl, Br or I for absorbing the blue light, producing yellow light (fluorescence) and synthesizing white color light by mixing the yellow light with the blue light. A blue light type white color light emitting device (R) including a 410 nm-470 nm blue light InGaN-LED, a fluorescence plate of ZnSxSe1-x (untreated 0.2?x?0.6; heat-treated 0.3?x?0.67) doped with more than 1×1017 cm?3 Al, In, Ga, Cl, Br or I for absorbing the blue light, producing 568 nm-580 nm yellow light (fluorescence) and synthesizing white color light by mixing the yellow light with the blue LED light.

Abstract: A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a punch-through stopper area is formed on a main surface side of a semiconductor substrate, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.

Abstract: A semiconductor component includes a first semiconductor region (110, 210) having a first conductivity type and a second semiconductor region (120, 220) above the first semiconductor region and having a second conductivity type. The semiconductor component further comprises a third semiconductor region (130, 230) above the second semiconductor region and having the first conductivity type, a fourth semiconductor region (140, 240) above the third semiconductor region and having the second conductivity type, a fifth semiconductor region (150, 250) above the third semiconductor region and having the first conductivity type, a sixth semiconductor region (160, 260) substantially enclosed within the fifth semiconductor region and having the second conductivity type, and a seventh semiconductor region (170, 270) above the first semiconductor region and having the second conductivity type.

Abstract: The invention relates to a so-called punch-through diode comprising a stack of, for example, an n++, p−, p+, n++ region (1, 2, 3, 4). In the known diode, these regions (1, 2, 3, 4) are arranged on a substrate (11) in said order. The diode is provided with connection conductors (5, 6). Such a diode does not have a steep I-V characteristic and hence is less suitable as a TVSD (=Transient Voltage Suppression Device). Particularly at voltages below 5 volts, a punch-through diode could form an attractive alternative for use as a TVSD. A punch-through diode according to the invention has an inverted structure, which means that the regions (1, 2, 3, 4) are positioned in reverse order on the substrate (11) and thus, the first region (1) adjoins the surface, and the fourth region (4) adjoins the substrate (11). Such a diode has a very steep I-V characteristic, is very suitable as a TVSD and functions very well at an operating voltage below 5 volts.

Abstract: A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding portion. A wire bonding region and a bump attach region are respectively defined on opposite surfaces of the protruding portion, and staggered in position. This allows a force applied from a wire bonder to the wire bonding regions not to adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions spaced apart from the bump attach regions can be prevented from being contaminated by an etching solution used in solder bump implantation, so that wire bonding quality can be well maintained.

Abstract: The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors (5, 6). During operation of said diode, a voltage is applied such that the second semiconductor region (2) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part (2A, 2B) of the second semiconductor region (2), which, viewed in projection, borders on the edge of the mesa (12), is provided with a larger flux of doping atoms of the second conductivity type than the remainder (2A) of the second semiconductor region (2).

Abstract: A NAND-type flash memory device for preventing punchthrough and a method for forming the same are provided. The NAND-type flash memory device includes a string selection transistor, a plurality of cell memory transistors, and a ground selection transistor being sequentially connected in series. The device further includes a bitline contact connected to a drain region of the string selection transistor, and a common source line connected to a source region of the ground selection transistor. Impurities are heavily doped to a drain-to-channel interface in the string selection transistor and a channel-to-source interface in the ground selection transistor, forming pockets for preventing punchthrough. The pockets are preferably formed using a tilted ion implantation using the vertical gate structures as masks.

Abstract: The invention relates to a ground-compatible inhibit circuit structure and method, for circuits integrated in a semiconductor substrate which is unrelated to ground potential. The circuit structure is integrated in the same substrate as an associated circuit to be inhibited, and the substrate is covered with an epitaxial layer accommodating the components of the inhibit circuit structure. It includes a stable internal voltage reference and a circuit portion for comparing this reference with an inhibit signal in order to block the associated circuit upon a predetermined threshold value being exceeded, even in a condition of the signal potential being higher than the supply potential to the circuit. Advantageously, the epitaxial layer of each well is always at a potential higher than or equal to that of the substrate.

Abstract: A lateral semiconductor structure having a punch-through diode for forming a temperature-compensated voltage limitation in which the space charge resistance is reduced through a lateral arrangement of preferably annular regions around a base trough. This is achieved in that the preferably annular regions are arranged with a specific doping as well as a specific separation from the base trough. By using the punch-through and avalanche effects, a higher breakdown voltage is achieved since the space charge resistance is reduced by the chosen arrangement.

Abstract: A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to define portions of the dielectric layers that will be removed in an etch step to create voids to the surface of the semiconductor substrate. Subsequently, epitaxially growth is employed to form active regions within the voids that were previously formed. Transistors are then formed in and on the active regions and are subsequently interconnected to form an integrated circuit.

Abstract: The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region.

Abstract: A semiconductor device having an oxygen-rich punchthrough region under the channel region, and a process for fabricating such a device are disclosed. In accordance with one embodiment, a semiconductor device is formed by forming an oxygen-rich punchthrough region in a substrate, and forming a channel region over the oxygen-rich punchthrough region. The use of an oxygen-rich punchthrough region may, for example, inhibit the diffusion of dopants used in forming the channel region.

Abstract: A semiconductor device of the RESURF type with a "low-side" lateral DMOST (LDMOST), comprising a semiconductor body (1) of predominantly a first conductivity type and a surface region (3) adjoining a surface (2) and of a second conductivity type. The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3) with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is present at a distance from the back gate region (5). A separation region (15) of the first conductivity type is provided around the LDMOST in the surface region (3), which separation region adjoins the surface (2) and extends towards the semiconductor body (1).

Abstract: A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus.

Abstract: The present invention is to provide a static induction semiconductor device with a distributed main electrode structure and a static induction semiconductor device with a static induction main electrode shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other and formed partly in contact with the lower impurity density region as well, and alternatively a static induction short-circuit region opposite in conductivity type to the main electrode region is formed in the lower impurity density region surrounded by the higher impurity density region.

Abstract: An input/output protection device for an integrated circuit is formed using a trench (22). A first electrode region (46) is formed adjacent a first portion of the trench sidewall (24), and a second electrode region (48) is formed adjacent a second portion of the trench sidewall (24). One of the electrode regions is then electrically coupled to an input/output pad, while the other electrode region is electrically coupled to ground. Excessive voltages on the input/output pad are then discharged when the electrode, which is electrically coupled to the input/output pad, punches through to the electrode that is electrically coupled to ground.

Abstract: A static induction semiconductor device has a low-resistance drain region, a high-resistance layer disposed on the drain region, a low-resistance source region spaced from the high-resistance layer, a low-resistance gate region disposed in the high-resistance layer, and a hetero layer disposed in an interface between the high-resistance layer and the source region and an interface between the gate region and a surface protective layer on the gate and source regions. The hetero layer, which may be made of AlGaAs, has a band gap larger than a semiconductor crystal such as GaAs of the drain, source, and gate regions. The static induction semiconductor device has a low resistance turned on and can operate in a bipolar mode.

Abstract: In a bipolar static induction transistor (BSIT) with increased input impedance, gate-voltage control is used for switching operations. The BSIT includes a collector region, a base region, an emitter region, and a source region in the base region. For enhanced turn-off, an auxiliary base region is included; alternatively, a drain region is provided in the base region.

Abstract: The disclosed improved GaAs majority carrier rectifying barrier diodes comprise a p.sup.+ region between semiconductor regions that comprise n-doped material. Exemplary structures are n.sup.+ -i-p.sup.+ -i-n.sup.+ and n.sup.+ -n-p.sup.+ -n-n.sup.+. The improvement comprises use of carbon as the p-dopant and results in readily manufacturable reliable devices.

Abstract: In a MOS controlled power device, or MOS composite a static induction thyristor, an static induction thyristor (SI thyristor) unit, a MOS transistor connected in cascode relation to the SI thyristor unit and a voltage regulation element are merged onto the single monolithic chip. The SI thyristor unit has a cathode region of first conductivity type having high impurity concentration, an anode and a gate regions of second conductivity type having high impurity concentration, and a channel region of first conductivity type having low impurity concentration. The MOS transistor has a drain region which is the same region as the cathode region, a well or a base of second conductivity type formed adjacent to the channel region of the SI thyristor unit, and a source region of first conductivity type having high impurity concentration. The source region is formed within the well or above the base.

Abstract: A transferred electron effect device (1) has adjacent its cathode contact region (3) an injection zone (60) defining a potential barrier (P) for causing electrons to be emitted, under the influence of an electric field applied between the cathode and anode contact regions (3 and 4), into the active region (5) of the device with an energy comparable to that of a relatively high mass, low mobility satellite minimum (L) of the active region (5). The anode contact region (4), active region (5), injection zone (60) and cathode contact region (3) are grown sequentially, for example using molecular beam epitaxy, on a substrate which is then selectively removed to expose the anode contact region. A heat sink (70) is provided in thermal contact with the anode contact region (4). Providing the heat sink (70) in thermal contact with the anode contact region (4) rather than the cathode contact region (3) enables a significant increase in rf output power.

Abstract: The invention relates to a controllable, temperature-compensated voltage limiter with a p.sup.+ np.sup.+ (or n.sup.+ pn.sup.+) semiconductor structure in which the width and doping of the central zone is selected such that no avalanche or Zener effect appears when voltage is applied to the two outer layers (punch-through diode). In accordance with the invention, the voltage U.sub.B to be limited is applied between the blocking pn-juncture (B-C). In addition, an adjustable auxiliary voltage (U.sub.H) is applied between the other pn-junction (H-C). The punch-through can be set to a higher defined value via the auxiliary voltage U.sub.H, this value being independent of the temperature to a large extent.