Abstract: A method of obtaining a doped semiconductor layer, including the successive steps of: a) performing, in a first single-crystal layer made of a semiconductor alloy of at least a first element A1 and a second element A2, an ion implantation of a first element B which is a dopant for the alloy and of a second element C which is not a dopant for the alloy, to make an upper portion of the first layer amorphous and to preserve the crystal structure of a lower portion of the first layer; and b) performing a solid phase recrystallization anneal of the upper portion of the first layer, resulting in transforming the upper portion of the first layer into a doped single-crystal layer of the alloy.

Abstract: A silicon wafer having a layer of oxygen precipitates and method of manufacturing thereof wherein the wafer exhibiting robustness characterized as having a ratio of a first average density from a first treatment that to a second average density from a second treatment is between 0.74 to 1.02, wherein the first treatment includes heating the wafer or a portion of the wafer at about 1150° C. for about 2 minutes and then between about 950 to 1000° C. for about 16 hours, and the second treatment includes heating the wafer or a portion of the wafer at about 780° C. for about 3 hours and then between about 950 to 1000° C. for about 16 hours. The wafer exhibits heretofore unattainable uniformity wherein a ratio of an oxygen precipitate density determined from any one cubic centimeter in the BMD layer of the wafer to another oxygen precipitate density from any other one cubic centimeter in the BMD layer of the wafer is in a range of 0.77 to 1.30.

Abstract: A method for fabricating a MOS transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.

Abstract: A manufacturing method of a semiconductor device includes: preparing a semiconductor substrate including a first semiconductor layer made of gallium oxide containing Sn and a second semiconductor layer disposed on the first semiconductor layer and made of n type gallium oxide having a Sn concentration lower than a Sn concentration of the first semiconductor layer; implanting ions of a group 2 element into the second semiconductor layer; and forming a diffusion region, in which the group 2 element diffuses, in a range from a surface of the second semiconductor layer to an interface between the second semiconductor layer and the first semiconductor layer.

Abstract: Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

Abstract: A new and useful p-type oxide semiconductor with a wide band gap and an enhanced electrical conductivity and the method of manufacturing the p-type oxide semiconductor are provided. A method of manufacturing a p-type oxide semiconductor including: generating atomized droplets by atomizing a raw material solution containing at least a d-block metal in the periodic table and a metal of Group 13 of the periodic table; carrying the atomized droplets onto a surface of a base by using a carrier gas; causing a thermal reaction of the atomized droplets adjacent to the surface of the base under an atmosphere of oxygen to form the p-type oxide semiconductor on the base.

Abstract: Provided is a semiconductor device which includes a semiconductor substrate that has an upper surface and a lower surface. A hydrogen chemical concentration distribution of the semiconductor substrate in a depth direction has a first hydrogen concentration peak and a second hydrogen concentration peak disposed closer to the lower surface side of the semiconductor substrate than the first hydrogen concentration peak. An intermediate donor concentration between the first hydrogen concentration peak and the second hydrogen concentration peak is different from any of an upper surface side donor concentration between the first hydrogen concentration peak and the upper surface of the semiconductor substrate and a lower surface side donor concentration between the second hydrogen concentration peak and the lower surface of the semiconductor substrate. The intermediate donor concentration may be higher than either the upper surface side donor concentration or the lower surface side donor concentration.

Abstract: The present invention includes: transferring a C-plane sapphire thin film 1t having an off-angle of 0.5-5° onto a handle substrate composed of a ceramic material having a coefficient of thermal expansion at 800 K that is greater than that of silicon and less than that of C-plane sapphire; performing high-temperature nitriding treatment on the GaN epitaxial growth substrate 11 and covering the surface of the C-plane sapphire thin film 1t with a surface treatment layer 11a made of AlN; having GaN grow epitaxially on the surface treatment layer 11a; ion-implanting a GaN film 13; pasting and bonding together the GaN film-side surface of the ion-implanted GaN film carrier and a support substrate 12; performing peeling at an ion implantation region 13ion in the GaN film 13 and transferring a GaN thin film 13a onto the support substrate 12; and obtaining a GaN laminate substrate 10.

Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.

Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.

Abstract: A silicon carbide epitaxial wafer (10) of the present invention is a silicon carbide epitaxial wafer including: a silicon carbide substrate (1) and a silicon carbide layer (2) provided on a first principal plane (1A) of the silicon carbide substrate (1) and having a film thickness of 100 ?m or more, wherein a warpage amount of the silicon carbide epitaxial wafer is ?20 ?m or more and 20 ?m or less.

Abstract: A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.

Abstract: A device forming method including: forming a diffusion layer by ion-implanting a dopant into a silicon single crystal substrate; and activating the diffusion layer by laser annealing. When the silicon single crystal substrate to be used has an oxygen concentration of less than 5 ppma in a region for forming the diffusion layer, the device forming method includes a step of controlling the region for forming the diffusion layer to have an oxygen concentration of 5 ppma or more before the diffusion layer is activated by the laser annealing. A device forming method capable of easily enhancing dopant activation level by laser annealing even when a region for forming a diffusion layer has a low oxygen concentration.

Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.

Abstract: A method of forming a semiconductor device includes irradiating a semiconductor body with particles. Dopant ions are implanted into the semiconductor body such that the dopant ions are configured to be activated as donors or acceptors. Thereafter, the semiconductor body is processed thermally.

Abstract: A wafer defect analysis method according to one embodiment comprises the steps of: thermally treating a wafer at different temperatures; measuring an oxygen precipitate index of the thermally treated wafer; determining a characteristic temperature at which the oxygen precipitate index is maximized; and discriminating a type of defect region of the wafer depending on the determined characteristic temperature.

Abstract: A balance spring for an oscillator of a timepiece, wherein it comprises a component part, in particular at least a coil or a portion of a coil, provided with heavily doped silicon having an ion density greater than or equal to 1018 at/cm3, in order to permit the thermo-compensation of the oscillator.

Abstract: A method controls a resistivity of a grown silicon single crystal by using a dopant when the silicon single crystal is grown by CZ method, including the steps of initially doping with a primary dopant such that the silicon single crystal has a predetermined conductive type and additionally doping with a secondary dopant having a conductive type opposite to that of the primary dopant continuously or intermittently, according to a solidification rate expressed by (crystalized weight)/(initial weight of silicon raw material) while growing the silicon single crystal, wherein in the additional doping step, the additional doping with the secondary dopant is carried out when the solidification rate is a predetermined value ? or more, while the crystal is not doped with the secondary dopant until the solidification rate reaches the predetermined value ?.

Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.

Abstract: A method of polishing a silicon wafer, including performing a mirror polishing process on the silicon wafer, the mirror polishing process including: performing rough polishing on the silicon wafer; subsequently removing metallic impurities attached on a surface of the silicon wafer by performing both an oxidation process with ozone gas or ozone water and an oxide-film removing process with hydrofluoric acid vapor or hydrofluoric acid solution on the surface of the silicon wafer; and then performing final polishing. The invention provides a method of polishing a silicon wafer and a method of producing an epitaxial wafer that can prevent the occurrence of PID in the silicon wafer due to a mirror-polishing process and the degradation of surface quality of the silicon wafer after the mirror-polishing process and the epitaxial wafer having an epitaxial layer stacked thereon in a subsequent process.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion.

Abstract: A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer.

Abstract: Monocrystalline silicon semiconductor wafers have a front side and a rear side, and a denuded zone which extends from the front side to the rear side as far as a depth which between a center and an edge of the semiconductor wafer on average is not less than 8 ?m and not more than 18 ?m, and having a region adjoining the denuded zone having BMDs whose density at a distance of 30 ?m from the front side is not less than 2×109 cm?3. The semiconductor wafers are produced by a method comprising providing a substrate wafer of monocrystalline silicon and an RTA treating the substrate wafer, the treatment subdivided into a first thermal treatment of the substrate wafer in an atmosphere consisting of argon and into a second thermal treatment of the substrate wafer in an atmosphere consisting of argon and ammonia.

Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Abstract: One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.

Abstract: The application relates to a high-resistivity silicon substrate (100) with a reduced radio frequency loss for a radio frequency integrated passive device. The substrate comprising a bulk zone (110) comprising high-resistivity bulk silicon and a preserved sub-surface lattice damage zone (120b) comprising fractured silicon above the bulk zone. The lattice damage zone is processed into the substrate and the preserved lattice damage zone is configured to achieve the RF loss reduction of the substrate by suppressing a parasitic surface conduction.

Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.

Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.

Abstract: A semiconductor component and a method for producing a semiconductor component are described. The semiconductor component includes a semiconductor body including an inner zone and an edge zone, and a passivation layer, which is arranged at least on a surface of the semiconductor body adjoining the edge zone. The passivation layer includes a semiconductor oxide and that includes a defect region having crystal defects that serve as getter centers for contaminations.

Abstract: A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.

Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.

Abstract: A method of manufacture of an optoelectronic device includes the steps of: providing or forming a body of crystalline silicon containing substitutional carbon atoms, and irradiating said body of crystalline silicon with protons (H+) to create radiative defect centers in a photoactive region of the device, wherein at least some of said defect centers are G-center complexes having the form Cs—SiI—Cs, where Cs is a substitutional carbon atom and S¾ is an interstitial silicon atom. An optoelectronic device (FIG. 3) manufactured using the method is described.

Abstract: A gallium and nitrogen containing substrate structure includes a handle substrate member having a first surface and a second surface and a transferred thickness of gallium and nitrogen material. The structure has a gallium and nitrogen containing active region grown overlying the transferred thickness and a recessed region formed within a portion of the handle substrate member. The substrate structure has a conductive material formed within the recessed region configured to transfer thermal energy from at least the transferred thickness of gallium and nitrogen material.

Abstract: According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region.

Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.

Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.

Abstract: Process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.

Abstract: A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.

Abstract: The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).

Abstract: Embodiments of the present invention provide metal structures for transporting or gettering materials disposed on or within a semiconductor substrate. A structure for transporting a material disposed on or within a semiconductor substrate may include a metal structure disposed within the semiconductor substrate and at a spaced distance from the material. The metal structure is configured to transport the material through the semiconductor substrate and to concentrate the material at the metal structure. The material may include a contaminant disposed within the semiconductor substrate, e.g., that originates from electronic circuitry on the substrate.

Abstract: A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm?3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm?3.

Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.

Abstract: A gallium and nitrogen containing substrate structure includes a handle substrate member having a first surface and a second surface and a transferred thickness of gallium and nitrogen material. The structure has a gallium and nitrogen containing active region grown overlying the transferred thickness and a recessed region formed within a portion of the handle substrate member. The substrate structure has a conductive material formed within the recessed region configured to transfer thermal energy from at least the transferred thickness of gallium and nitrogen material.

Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 ?m from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.

Abstract: A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.

Abstract: A method of manufacture of an optoelectronic device includes the steps of: providing or forming a body of crystalline silicon containing substitutional carbon atoms, and irradiating said body of crystalline silicon with protons (H+) to create radiative defect centres in a photoactive region of the device, wherein at least some of said defect centres are G-centre complexes having the form Cs—SiI—Cs, where Cs is a substitutional carbon atom and S¾ is an interstitial silicon atom. An optoelectronic device (FIG. 3) manufactured using the method is described.

Abstract: In order to obtain a SOI wafer having an excellent ability of gettering metal impurities, an efficient method of manufacturing a SOI wafer, and a highly reliable MEMS device using such a SOI wafer, provided is a SOI wafer including: a support wafer (1) and an active layer wafer (6) which are bonded together with an oxide film (3) therebetween, each of the support wafer (1) and the active layer wafer (6) being a silicon wafer; a cavity (1b) formed in a bonding surface of at least one of the silicon wafers; and a gettering material (2) formed on a surface on a side opposite to the bonding surface.

Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.