Including Region Containing Crystal Damage Patents (Class 257/617)
  • Patent number: 11916103
    Abstract: A new and useful p-type oxide semiconductor with a wide band gap and an enhanced electrical conductivity and the method of manufacturing the p-type oxide semiconductor are provided. A method of manufacturing a p-type oxide semiconductor including: generating atomized droplets by atomizing a raw material solution containing at least a d-block metal in the periodic table and a metal of Group 13 of the periodic table; carrying the atomized droplets onto a surface of a base by using a carrier gas; causing a thermal reaction of the atomized droplets adjacent to the surface of the base under an atmosphere of oxygen to form the p-type oxide semiconductor on the base.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: February 27, 2024
    Assignees: FLOSFIA INC., KYOTO UNIVERSITY
    Inventors: Shizuo Fujita, Kentaro Kaneko, Toshimi Hitora, Tomochika Tanikawa
  • Patent number: 11901419
    Abstract: Provided is a semiconductor device which includes a semiconductor substrate that has an upper surface and a lower surface. A hydrogen chemical concentration distribution of the semiconductor substrate in a depth direction has a first hydrogen concentration peak and a second hydrogen concentration peak disposed closer to the lower surface side of the semiconductor substrate than the first hydrogen concentration peak. An intermediate donor concentration between the first hydrogen concentration peak and the second hydrogen concentration peak is different from any of an upper surface side donor concentration between the first hydrogen concentration peak and the upper surface of the semiconductor substrate and a lower surface side donor concentration between the second hydrogen concentration peak and the lower surface of the semiconductor substrate. The intermediate donor concentration may be higher than either the upper surface side donor concentration or the lower surface side donor concentration.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: February 13, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasunori Agata
  • Patent number: 11479876
    Abstract: The present invention includes: transferring a C-plane sapphire thin film 1t having an off-angle of 0.5-5° onto a handle substrate composed of a ceramic material having a coefficient of thermal expansion at 800 K that is greater than that of silicon and less than that of C-plane sapphire; performing high-temperature nitriding treatment on the GaN epitaxial growth substrate 11 and covering the surface of the C-plane sapphire thin film 1t with a surface treatment layer 11a made of AlN; having GaN grow epitaxially on the surface treatment layer 11a; ion-implanting a GaN film 13; pasting and bonding together the GaN film-side surface of the ion-implanted GaN film carrier and a support substrate 12; performing peeling at an ion implantation region 13ion in the GaN film 13 and transferring a GaN thin film 13a onto the support substrate 12; and obtaining a GaN laminate substrate 10.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 25, 2022
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yoshihiro Kubota, Kazutoshi Nagata
  • Patent number: 10950461
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10916444
    Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 9, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 10879359
    Abstract: A silicon carbide epitaxial wafer (10) of the present invention is a silicon carbide epitaxial wafer including: a silicon carbide substrate (1) and a silicon carbide layer (2) provided on a first principal plane (1A) of the silicon carbide substrate (1) and having a film thickness of 100 ?m or more, wherein a warpage amount of the silicon carbide epitaxial wafer is ?20 ?m or more and 20 ?m or less.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: December 29, 2020
    Inventors: Keiko Masumoto, Satoshi Segawa, Kazutoshi Kojima, Tomohisa Kato, Toshiyuki Ohno
  • Patent number: 10796905
    Abstract: A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 6, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Michael R. Seacrist
  • Patent number: 10748772
    Abstract: A device forming method including: forming a diffusion layer by ion-implanting a dopant into a silicon single crystal substrate; and activating the diffusion layer by laser annealing. When the silicon single crystal substrate to be used has an oxygen concentration of less than 5 ppma in a region for forming the diffusion layer, the device forming method includes a step of controlling the region for forming the diffusion layer to have an oxygen concentration of 5 ppma or more before the diffusion layer is activated by the laser annealing. A device forming method capable of easily enhancing dopant activation level by laser annealing even when a region for forming a diffusion layer has a low oxygen concentration.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: August 18, 2020
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Katsuyoshi Suzuki
  • Patent number: 10734230
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first region formed on a front surface side of a semiconductor substrate; a drift region formed closer to a rear surface of the semiconductor substrate than the first region is; a buffer region that: is formed closer to the rear surface of the semiconductor substrate than the drift region is; and has one or more peaks of an impurity concentration that are higher than an impurity concentration of the drift region; and a lifetime killer that: is arranged on a rear surface side of the semiconductor substrate; and shortens a carrier lifetime, wherein a peak of a concentration of the lifetime killer is arranged between: a peak that is closest to a front surface of the semiconductor substrate among the peaks of the impurity concentration in the buffer region; and the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: August 4, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Misaki Takahashi
  • Patent number: 10580653
    Abstract: A method of forming a semiconductor device includes irradiating a semiconductor body with particles. Dopant ions are implanted into the semiconductor body such that the dopant ions are configured to be activated as donors or acceptors. Thereafter, the semiconductor body is processed thermally.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies AG
    Inventors: Franz-Josef Niedernostheide, Johannes Georg Laven, Hans-Joachim Schulze
  • Patent number: 10541181
    Abstract: A wafer defect analysis method according to one embodiment comprises the steps of: thermally treating a wafer at different temperatures; measuring an oxygen precipitate index of the thermally treated wafer; determining a characteristic temperature at which the oxygen precipitate index is maximized; and discriminating a type of defect region of the wafer depending on the determined characteristic temperature.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 21, 2020
    Assignee: SK SILTRON CO., LTD.
    Inventor: Jae Hyeong Lee
  • Patent number: 10539926
    Abstract: A balance spring for an oscillator of a timepiece, wherein it comprises a component part, in particular at least a coil or a portion of a coil, provided with heavily doped silicon having an ion density greater than or equal to 1018 at/cm3, in order to permit the thermo-compensation of the oscillator.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: January 21, 2020
    Assignee: ROLEX SA
    Inventors: Richard Bossart, Olivier Hunziker
  • Patent number: 10400353
    Abstract: A method controls a resistivity of a grown silicon single crystal by using a dopant when the silicon single crystal is grown by CZ method, including the steps of initially doping with a primary dopant such that the silicon single crystal has a predetermined conductive type and additionally doping with a secondary dopant having a conductive type opposite to that of the primary dopant continuously or intermittently, according to a solidification rate expressed by (crystalized weight)/(initial weight of silicon raw material) while growing the silicon single crystal, wherein in the additional doping step, the additional doping with the secondary dopant is carried out when the solidification rate is a predetermined value ? or more, while the crystal is not doped with the secondary dopant until the solidification rate reaches the predetermined value ?.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: September 3, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Ryoji Hoshi, Hiroyuki Kamada, Kiyotaka Takano
  • Patent number: 10079282
    Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: September 18, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai, Chiharu Ota, Kazuto Takao, Takashi Shinohe
  • Patent number: 9824880
    Abstract: A method of polishing a silicon wafer, including performing a mirror polishing process on the silicon wafer, the mirror polishing process including: performing rough polishing on the silicon wafer; subsequently removing metallic impurities attached on a surface of the silicon wafer by performing both an oxidation process with ozone gas or ozone water and an oxide-film removing process with hydrofluoric acid vapor or hydrofluoric acid solution on the surface of the silicon wafer; and then performing final polishing. The invention provides a method of polishing a silicon wafer and a method of producing an epitaxial wafer that can prevent the occurrence of PID in the silicon wafer due to a mirror-polishing process and the degradation of surface quality of the silicon wafer after the mirror-polishing process and the epitaxial wafer having an epitaxial layer stacked thereon in a subsequent process.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: November 21, 2017
    Assignee: SHIN-ETSU HANDOTAI CO., LTD
    Inventor: Hideki Sato
  • Patent number: 9646835
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 9, 2017
    Assignee: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Patent number: 9536740
    Abstract: A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: January 3, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Laven, Franz Josef Niedernostheide, Frank Dieter Pfirsch
  • Patent number: 9530859
    Abstract: A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: December 27, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shuhei Oki, Tsuyoshi Nishiwaki
  • Patent number: 9230798
    Abstract: Monocrystalline silicon semiconductor wafers have a front side and a rear side, and a denuded zone which extends from the front side to the rear side as far as a depth which between a center and an edge of the semiconductor wafer on average is not less than 8 ?m and not more than 18 ?m, and having a region adjoining the denuded zone having BMDs whose density at a distance of 30 ?m from the front side is not less than 2×109 cm?3. The semiconductor wafers are produced by a method comprising providing a substrate wafer of monocrystalline silicon and an RTA treating the substrate wafer, the treatment subdivided into a first thermal treatment of the substrate wafer in an atmosphere consisting of argon and into a second thermal treatment of the substrate wafer in an atmosphere consisting of argon and ammonia.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: January 5, 2016
    Assignee: SILTRONIC AG
    Inventors: Timo Mueller, Michael Gehmlich, Frank Faller, Dirk Waehlisch
  • Patent number: 9219112
    Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony J. Lochtefeld, Matthew T. Currie, Zhiyuan Cheng, James Fiorenza, Glyn Braithwaite, Thomas A. Langdo
  • Patent number: 9099421
    Abstract: One or more techniques or systems for controlling a profile of a surface of a semiconductor region are provided herein. In some embodiments, an etching to deposition (E/D) ratio is set to be less than one to form the region within the semiconductor. For example, when the E/D ratio is less than one, an etching rate is less than a deposition rate of the E/D ratio, thus ‘growing’ the region. In some embodiments, the E/D ratio is subsequently set to be greater than one. For example, when the E/D ratio is greater than one, the etching rate is greater than the deposition rate of the E/D ratio, thus ‘etching’ the region. In this manner, a smooth surface profile is provided for the region, at least because setting the E/D ratio to be greater than one enables etch back of at least a portion of the grown region.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
  • Publication number: 20150145105
    Abstract: The application relates to a high-resistivity silicon substrate (100) with a reduced radio frequency loss for a radio frequency integrated passive device. The substrate comprising a bulk zone (110) comprising high-resistivity bulk silicon and a preserved sub-surface lattice damage zone (120b) comprising fractured silicon above the bulk zone. The lattice damage zone is processed into the substrate and the preserved lattice damage zone is configured to achieve the RF loss reduction of the substrate by suppressing a parasitic surface conduction.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventor: Atte HAAPALINNA
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9018735
    Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 28, 2015
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Jung-Goo Park
  • Patent number: 8987866
    Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: March 24, 2015
    Assignee: Sony Corporation
    Inventors: Yoshikazu Motoyama, Hiroki Tsunemi, Hideo Yamagata
  • Publication number: 20150076597
    Abstract: A semiconductor component and a method for producing a semiconductor component are described. The semiconductor component includes a semiconductor body including an inner zone and an edge zone, and a passivation layer, which is arranged at least on a surface of the semiconductor body adjoining the edge zone. The passivation layer includes a semiconductor oxide and that includes a defect region having crystal defects that serve as getter centers for contaminations.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 19, 2015
    Inventors: Hans-Joachim Schulze, Manfred Pfaffenlehner, Markus Schmitt
  • Patent number: 8981530
    Abstract: A semiconductor device includes a first NMOS device with a first threshold voltage and a second NMOS device with a second threshold voltage. The first NMOS device includes a first gate structure over a semiconductor substrate, first source/drain (S/D) regions in the semiconductor substrate and adjacent to opposite edges of the first gate structure. The first S/D regions are free of dislocation. The second NMOS device includes a second gate structure over the semiconductor substrate, second S/D regions in the semiconductor substrate and adjacent to opposite edges of the second gate structure, and a dislocation in the second S/D regions.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming Zhu
  • Patent number: 8975728
    Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuyuki Ikarashi, Masayasu Tanaka
  • Patent number: 8975169
    Abstract: A method of manufacture of an optoelectronic device includes the steps of: providing or forming a body of crystalline silicon containing substitutional carbon atoms, and irradiating said body of crystalline silicon with protons (H+) to create radiative defect centers in a photoactive region of the device, wherein at least some of said defect centers are G-center complexes having the form Cs—SiI—Cs, where Cs is a substitutional carbon atom and S¾ is an interstitial silicon atom. An optoelectronic device (FIG. 3) manufactured using the method is described.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: March 10, 2015
    Assignee: The University of Surrey
    Inventors: Kevin Peter Homewood, Russell Mark Gwilliam
  • Patent number: 8946865
    Abstract: A gallium and nitrogen containing substrate structure includes a handle substrate member having a first surface and a second surface and a transferred thickness of gallium and nitrogen material. The structure has a gallium and nitrogen containing active region grown overlying the transferred thickness and a recessed region formed within a portion of the handle substrate member. The substrate structure has a conductive material formed within the recessed region configured to transfer thermal energy from at least the transferred thickness of gallium and nitrogen material.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: February 3, 2015
    Assignee: Soraa, Inc.
    Inventors: Mark P. D'Evelyn, Arpan Chakraborty, William D. Houck
  • Publication number: 20150001680
    Abstract: According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer, wherein a first heat treatment for holding a silicon single crystal wafer in an oxygen containing atmosphere at a first heat treatment temperature for 1 to 60 seconds and cooling it to 800° C. or less at a temperature falling rate of 1 to 100° C./second by using a rapid heating/rapid cooling apparatus is performed to inwardly diffuse oxygen and form an oxygen concentration peak region near a surface of the silicon single crystal wafer, and then a second heat treatment is performed to agglomerate oxygen in the silicon single crystal wafer into the oxygen concentration peak region. As a result, it is possible to provide the method for manufacturing a silicon single crystal wafer that enables forming an excellent gettering layer close to a device forming region.
    Type: Application
    Filed: December 14, 2012
    Publication date: January 1, 2015
    Inventors: Tetsuya Oka, Koji Ebara
  • Patent number: 8916953
    Abstract: The present invention provides a method for manufacturing a silicon single crystal wafer, in which a heat treatment is performed with respect to a silicon single crystal wafer having oxygen concentration of less than 7 ppma and nitrogen concentration of 1×1013 to 1×1014 atoms/cm3, which is obtained from a V-region silicon single crystal ingot grown by the Czochralski method, in a non-nitriding atmosphere at 1150 to 1300° C. for 1 to 120 minutes. As a result, a method for manufacturing a low-cost silicon single crystal wafer which is applicable to an IGBT by using a V-region wafer that is manufactured by the CZ method which can cope with an increase in diameter, by making a bulk have no defects and by providing a radial resistivity distribution, which is substantially equal to that when the neutron irradiation is effected, without performing the neutron irradiation is provided.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: December 23, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Wei Feng Qu, Fumio Tahara, Yuuki Ooi, Shu Sugisawa
  • Publication number: 20140346639
    Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.
    Type: Application
    Filed: January 14, 2013
    Publication date: November 27, 2014
    Inventors: Francois Boedt, Roland Brun, Olivier Ledoux, Eric Butaud
  • Publication number: 20140327112
    Abstract: Process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.
    Type: Application
    Filed: October 14, 2011
    Publication date: November 6, 2014
    Applicant: SunEdison, Inc.
    Inventors: Jeffrey L. Libbert, Lu Fei
  • Patent number: 8847328
    Abstract: A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 30, 2014
    Assignee: IXYS Corporation
    Inventor: Andreas Laschek-Enders
  • Publication number: 20140264756
    Abstract: The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Christopher N. Collins, Mukta G. Farooq, Troy L. Graves-Abe, Joyce C. Liu, Gerd Pfeiffer, Thuy L. Tran-Quinn
  • Publication number: 20140264757
    Abstract: Embodiments of the present invention provide metal structures for transporting or gettering materials disposed on or within a semiconductor substrate. A structure for transporting a material disposed on or within a semiconductor substrate may include a metal structure disposed within the semiconductor substrate and at a spaced distance from the material. The metal structure is configured to transport the material through the semiconductor substrate and to concentrate the material at the metal structure. The material may include a contaminant disposed within the semiconductor substrate, e.g., that originates from electronic circuitry on the substrate.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: The Aerospace Corporation
    Inventors: Nathan Presser, David P. Taylor
  • Patent number: 8835930
    Abstract: A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm?3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm?3.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Publication number: 20140246755
    Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.
    Type: Application
    Filed: May 13, 2014
    Publication date: September 4, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi YOSHIMURA, Masayuki MIYAZAKI, Hiroshi TAKISHITA, Hidenao KURIBAYASHI
  • Patent number: 8786053
    Abstract: A gallium and nitrogen containing substrate structure includes a handle substrate member having a first surface and a second surface and a transferred thickness of gallium and nitrogen material. The structure has a gallium and nitrogen containing active region grown overlying the transferred thickness and a recessed region formed within a portion of the handle substrate member. The substrate structure has a conductive material formed within the recessed region configured to transfer thermal energy from at least the transferred thickness of gallium and nitrogen material.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: July 22, 2014
    Assignee: Soraa, Inc.
    Inventors: Mark P. D'Evelyn, Arpan Chakraborty, William Houck
  • Patent number: 8779552
    Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 ?m from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20140191370
    Abstract: A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected.
    Type: Application
    Filed: September 16, 2013
    Publication date: July 10, 2014
    Inventor: Woo Young SIM
  • Publication number: 20140187026
    Abstract: A method of manufacture of an optoelectronic device includes the steps of: providing or forming a body of crystalline silicon containing substitutional carbon atoms, and irradiating said body of crystalline silicon with protons (H+) to create radiative defect centres in a photoactive region of the device, wherein at least some of said defect centres are G-centre complexes having the form Cs—SiI—Cs, where Cs is a substitutional carbon atom and S¾ is an interstitial silicon atom. An optoelectronic device (FIG. 3) manufactured using the method is described.
    Type: Application
    Filed: August 9, 2012
    Publication date: July 3, 2014
    Applicant: THE UNIVERSITY OF SURREY
    Inventors: Kevin Peter Homewood, Russell Mark Gwilliam
  • Publication number: 20140175573
    Abstract: In order to obtain a SOI wafer having an excellent ability of gettering metal impurities, an efficient method of manufacturing a SOI wafer, and a highly reliable MEMS device using such a SOI wafer, provided is a SOI wafer including: a support wafer (1) and an active layer wafer (6) which are bonded together with an oxide film (3) therebetween, each of the support wafer (1) and the active layer wafer (6) being a silicon wafer; a cavity (1b) formed in a bonding surface of at least one of the silicon wafers; and a gettering material (2) formed on a surface on a side opposite to the bonding surface.
    Type: Application
    Filed: February 28, 2014
    Publication date: June 26, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Eiji YOSHIKAWA, Jyunichi ICHIKAWA, Yukihisa YOSHIDA
  • Publication number: 20140124897
    Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.
    Type: Application
    Filed: October 3, 2013
    Publication date: May 8, 2014
    Applicant: SONY CORPORATION
    Inventors: Yoshikazu Motoyama, Hiroki Tsunemi, Hideo Yamagata
  • Publication number: 20140103493
    Abstract: An arrangement for manufacturing a crystal of the melt of a raw material comprises: a furnace having a heating device with one or more heating elements, which are configured to generate a gradient temperature field directed along a first direction, a plurality of crucibles for receiving the melt, which are arranged within the gradient temperature field side by side, and a device for homogenizing the temperature field within a plane perpendicular to the first direction in the at least two crucibles. The arrangement further has a filling material inserted within a space between the crucibles wherein the filling shows an anisotropic heat conductivity. Additionally or alternatively, the arrangement may comprise a device for generating magnetic migration fields, both the filling material having the anisotropic heat conductivity and the device for generating magnetic migration fields being suited to compensate or prevent the formation of asymmetric phase interfaces upon freezing of the raw melt.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 17, 2014
    Applicant: FREIBERGER COMPOUND MATERIALS GMBH
    Inventors: Stefan EICHLER, Thomas BÜNGER, Michael BUTTER, Rico RÜHMANN, Max SCHEFFER-CZYGAN
  • Publication number: 20140103492
    Abstract: The present invention provides a method for producing a silicon wafer from a defect-free silicon single crystal grown by a CZ method, the method comprising: preparing a silicon wafer obtained by slicing the defect-free silicon single crystal and subjected to mirror-polishing; then performing a heat treatment step of subjecting the mirror-polished silicon wafer to heat treatment at a temperature of 500° C. or higher but 600° C. or lower for 4 hours or more but 6 hours or less; and performing a repolishing step of repolishing the silicon wafer after the heat treatment step such that a polishing amount becomes 1.5 ?m or more. Therefore, it is an object to provide a method by which a silicon wafer can be produced at a high yield, the silicon wafer in which LPDs are reduced to a minimum, the silicon wafer with a low failure-incidence rate in an inspection step and a shipment stage.
    Type: Application
    Filed: May 14, 2012
    Publication date: April 17, 2014
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Izumi Fusegawa, Ryoji Hoshi, Susumu Sonokawa, Hisayuki Saito
  • Patent number: 8674481
    Abstract: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: March 18, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Steven R. Droes, Yutaka Takafuji
  • Patent number: 8664746
    Abstract: A silicon on insulater (SOI) wafer is provided. A dielectric layer is formed on an active silicon substrate of the wafer. The dielectric layer is patterned and etched to expose selected portions of the silicon substrate. Impurities are then introduced into the exposed portions of the silicon substrate to act as gettering regions. The dielectric layer is then removed and an epitaxial layer of silicon is grown on the silicon substrate. Trenches are etched in the epitaxial layer of silicon through the gettering regions, partially removing the gettering regions and any contaminants contained therein. Remaining portions of the gettering regions still act as gettering regions during subsequent process steps.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: March 4, 2014
    Assignee: STMicroelectronics Pte. Ltd.
    Inventors: Janusz Karol Korycinski, Wanliang Wen
  • Patent number: 8575652
    Abstract: An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: November 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiki Kamata