Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.

Abstract: A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius.

Abstract: A semiconductor package device comprises a substrate, a die, an encapsulant and an antenna layer. The substrate has a top surface and a bottom surface opposite to the top surface. The die is disposed on the top surface of the substrate. The encapsulant is disposed on the top surface of the substrate and surrounds the die. The encapsulant has a top surface and defines a recess on the top surface of the encapsulant. The antenna layer is disposed on the top surface of the encapsulant and extends within the recess on the top surface of the encapsulant.

Abstract: One example includes a flux qubit readout circuit. The circuit includes a gradiometric SQUID that is configured to inductively couple with a gradiometric flux qubit to modify flux associated with the gradiometric superconducting quantum interference device (SQUID) based on a flux state of the flux qubit. The circuit also includes a current source configured to provide a readout current through the gradiometric SQUID during a state readout operation to determine the flux state of the gradiometric flux qubit at a readout node.

Abstract: A superconducting thermal detector (bolometer) of THz (sub-millimeter) wave radiation based on sensing the change in the amplitude or phase of a resonator circuit, consisting of a capacitor (Csh) and a superconducting temperature dependent inductor where the said inductor is thermally isolated from the heat bath (chip substrate) by micro-suspensions. The bolometer design includes a thin film inductor located on the membrane, a single or/and multi-layered thin film capacitor, and a thin film absorber of incoming radiation. The bolometer design can also include a lithographic antenna with antenna termination and/or a back reflector beneath the membrane for optimal wavelength detection by the resonance circuit. The superconducting thermal detector (bolometer) and arrays of these detectors operate in a temperature range from 1 Kelvin to 10 Kelvin.

Abstract: Systems and methods for operating a quantum Otto cycle, including a superconducting LC resonator circuit electrically coupled to an input control unit with a reservoir source and a waveform generator configured to generate a bias current. A superconducting flux qubit is coupled to the LC resonator via a superconducting quantum interference device (“SQUID”). The SQUID generates a flux in the presence of the bias current, and the flux generated by the SQUID mediates a coupling rate between the flux qubit and the LC resonator. The waveform generator alternates the bias current to adiabatically change the coupling rate between the flux qubit and the LC resonator during adiabatic stages of the quantum Otto cycle. The reservoir source sends pulses to thermalize the flux qubit and the LC resonator system during isochoric stages of the quantum Otto cycle.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

Abstract: Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract: Vapor-liquid-solid growth of nanowires is tailored to achieve complex one-dimensional material geometries using phase diagrams determined for nanoscale materials. Segmented one-dimensional nanowires having constant composition display locally variable electronic band structures that are determined by the diameter of the nanowires. The unique electrical and optical properties of the segmented nanowires are exploited to form electronic and optoelectronic devices. Using gold-germanium as a model system, in situ transmission electron microscopy establishes, for nanometer-sized Au—Ge alloy drops at the tips of Ge nanowires (NWs), the parts of the phase diagram that determine their temperature-dependent equilibrium composition. The nanoscale phase diagram is then used to determine the exchange of material between the NW and the drop. The phase diagram for the nanoscale drop deviates significantly from that of the bulk alloy.

Abstract: An integrated circuit connection comprises a substrate, first and second transmission lines, a die, and a conductive ribbon. The first transmission line has a first end and is arranged on the substrate. The die is spaced from the first end. The die has a first surface, which is arranged on the substrate, and a second surface, which is opposite to the first surface and which has the second transmission line arranged thereon. The second transmission line has a second end. The conductive ribbon electrically couples the first and the second ends.

Abstract: A photoelectric conversion device including a substrate, a photoelectric conversion element including a first electrode, a second electrode and an organic compound layer and a sealing member that are disposed in this order. When a cross section of the photoelectric conversion device in a thickness direction is observed with the sealing member being placed at an upper side, a bonding member seals the organic compound layer at an outside thereof. An output electrode on the sealing member has a protrusion. A side conductive portion is electrically connected with the protrusion in an up-and-down direction. A substrate conductive member electrically connected with the first electrode and the second electrode extends to an outside of the bonding member. An electrical connecting member electrically connects the side conductive portion to the substrate conductive member at a further outside of the bonding member.

Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Abstract: Superconducting connections are provided to internal layers of a multi-layer circuit board structure, for example by superconducting vias.

Abstract: A method of expanding the contact pitch for un-diced chips in an array by pre-slicing the array in a first direction, attaching a lead frame to the chips' contacts, and then slicing the array and attached lead frame in the second direction. The lead frame has leads mechanically connected one another such that slicing the frame in the second direction along the mechanical connections separates the leads. Each lead has a first terminal which is conductively attached to a chip contact and a second terminal extending beyond the boundaries of the chip to which the first terminal is attached. In this manner, the contact pitch is effectively expanded to the terminal pitch of the leads.

Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Abstract: Disclosed are packages for optocouplers and methods of making the same. An exemplary optocoupler comprises a substrate having a first surface and a second surface, a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's first surface, and a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's second surface. The substrate may comprise a pre-molded leadframe, and electrical connections between optoelectronic dice on opposite surfaces of the substrate may be made via one or more leads of the leadframe.

Abstract: The invention describes a method of achieving superconductivity in Group IV semiconductors via the addition of doubly charged impurity atoms to the crystal lattice. The doubly charged impurities function as composite bosons in the semiconductor. Increasing the density of the composite bosons to a level where their wavefunctions overlap, results in the formation of a Bose condensate. The concentration of the doubly charged impurity atoms in the host lattice and the binding energy of the impurities are important factors in determining whether a Bose condensate will form. Doubly charged impurities must be present in the semiconductor at a concentration at which they exhibit overlapping wavefunctions, but still exist within the crystal lattice as bosons.

Abstract: A process for growth of boron-based nanostructures, such as nanotubes and nanowires, with a controlled diameter and with controlled chemical (such as composition, doping) as well as physical (such as electrical and superconducting) properties is described. The boron nanostructures are grown on a metal-substituted MCM-41 template with pores having a uniform pore diameter of less than approximately 4 nm, and can be doped with a Group Ia or Group IIa electron donor element during or after growth of the nanostructure. Preliminary data based on magnetic susceptibility measurements suggest that Mg-doped boron nanotubes have a superconducting transition temperature on the order of 100 K.

Abstract: A compliant semiconductor chip package assembly includes a a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Abstract: A qubit implementation based on exciton condensation in capacitively coupled Josephson junction chains is disclosed. The qubit may be protected in the sense that unwanted terms in its effective Hamiltonian may be exponentially suppressed as the chain length increases. Also disclosed is an implementation of a universal set of quantum gates, most of which offer exponential error suppression.

Abstract: A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

Abstract: The invention relates to a coil for producing a magnetic field having at least one winding (12), which is manufactured from a superconductor, is cast into a plastic and whose winding end (19) which is arranged at the circumference (13) of the winding (12) is used for making contact with an electrical conductor (15). In order to provide coils with windings (12) consisting of superconductors which make robust contact-making possible given simple production, an electrically conductive connection piece (30) with a base region (31), which is connected to the winding end (19), and a top region (32) for connecting the conductor (15) is provided for contact-making purposes, the base region (31) of said connection piece (30) being covered partially in the radial direction by a reinforcing insert (14), which is cast into the plastic (20) and at least partially surrounds the winding (12).

Abstract: A method for producing a thin layer device such as a superconductive device excellent in mechanical strength and useful as a submillimeter band receiver is provided. The thin layer device is produced by forming a multilayer structure substance comprising an NbN/MgO/NbN-SIS junction on an MgO temporary substrate, then forming SiO2, as a substrate, on said multilayer structure substance, and subsequently removing the MgO temporary substrate by etching. A superconductive device (a thin layer device) produced by a method of the present invention has excellent performance and high mechanical strength, and therefore introduction to a waveguide for a submillimeter band is also easy.

Abstract: A process for growth of boron-based nanostructures, such as nanotubes and nanowires, with a controlled diameter and with controlled chemical (such as composition, doping) as well as physical (such as electrical and superconducting) properties is described. The boron nanostructures are grown on a metal-substituted MCM-41 template with pores having a uniform pore diameter of less than approximately 4 nm, and can be doped with a Group Ia or Group IIa electron donor element during or after growth of the nanostructure. Preliminary data based on magnetic susceptibility measurements suggest that Mg-doped boron nanotubes have a superconducting transition temperature on the order of 100 K.

Abstract: A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a second plurality of output ports (190) comprising: a first stack (140) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (142); a second stack (160) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer (113) containing at least one switching element circuit (162); and interconnecting circuitry (150) that connects the first stack (140) of IC layers to the second stack (160) of IC layers to form the compact multi-stage switching network. The stacks (140, 160) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection.

Abstract: A novel micro optical system as a platform technology for electrical and optical interconnections, thermal and mechanical assembly and integration of electronic, optoelectronic, passive and active components. This platform provides optical coupling and chip-to-chip interconnection by microwave electrical, optical guided and unguided waves, and power or bias electrical contacts or interfaces by a novel chip in flexible circuit, rigid or inflexible embodiments.

Abstract: In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical junction formed by a well and a highly doped region closer to a surface of the substrate. The counter doping implant may also increase the concentration of the dopant of the well. The counter doping implant and the source/drain implant may be performed using the same mask. Transistors fabricated using embodiments of the present invention may be employed in memory cells to reduce soft error rates.

Abstract: A semiconductor light emitting device including a p-type electrode structure and having a low contact resistance and high reflectance is provided. The semiconductor light emitting device includes a transparent substrate, an electron injection layer having first and second regions on the transparent substrate, an active region formed on the first region, a hole injection layer on the active layer, a first electrode structure on the second region, and a second electrode structure on the hole injection layer, and includes a first layer including nitrogen and a second layer including Pd. The low contact resistance and high reflectance can be obtained by forming a trivalent compound layer composed of Pd—Ga—N at an interface between the hole injection layer, which is composed of p-GaN, and the metal layer of the p-type electrode.

Abstract: It is an object to provide a tuning circuit which has large fractional frequency band width, for example frequency band of the return loss of less than ?10 dB. The tuning circuit is composed of a superconductor microstrip lines, a superconductor distributed tunnel junction elements, a signal input part and a signal output part. It comprises at least a superconductor microstrip line and at least two superconductor tunnel junction elements, wherein the microstrip line and the tunnel junction element are connected alternately. The microstrip line and the tunnel junction element are half-wavelength of an input signal at a center frequency. A quarter-wavelength impedance transformer is comprised between a signal input part and a half-wavelength tunnel junction which is nearest to the signal input part.

Abstract: An interconnect is described including a semiconductor substrate having opposing surfaces, including first and second insulated conductors for transmitting signals. A third conductor substantially surrounds and is electrically insulated from the first and second insulated conductors. Capacitance between the first insulated conductor and the third conductor is substantially equivalent to capacitance between the second insulated conductor and the third conductor. The first insulated conductor and the second insulated conductor are disposed between the opposing surfaces of the semiconductor substrate.

Abstract: A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.

Abstract: An interconnect is described including a semiconductor substrate having opposing surfaces, including first and second insulated conductors for transmitting signals. A third conductor substantially surrounds and is electrically insulated from the first and second insulated conductors. Capacitance between the first insulated conductor and the third conductor is substantially equivalent to capacitance between the second insulated conductor and the third conductor. The first insulated conductor and the second insulated conductor are disposed between the opposing surfaces of the semiconductor substrate.

Abstract: An integrated circuit arrangement includes at least one electrical conductor that, when a current flows through it, produces a magnetic field that acts on at least a further part of the circuit configuration, wherein seen in cross-section, the electrical conductor has at least one recess or depression, or a region of reduced conductivity on the side facing that part, in order to influence the magnetic field that can be produced.

Abstract: A method for increasing the critical temperature, Tc, of a high critical temperature superconducting (HTS) film (104) grown on a substrate (102) and a superconducting structure (100) made using the method. The HTS film has an a-b plane parallel to the surface of the substrate and a c-direction normal to the surface of the substrate. Generally, the method includes providing the substrate, growing the HTS film on the substrate and, after the HTS film has been grown, inducing into the HTS film a residual compressive strain the a-b plane and a residual tensile strain into the c-direction.

Abstract: A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a second plurality of output ports (190) comprising: a first stack (140) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (142); a second stack (160) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer (113) containing at least one switching element circuit (162); and interconnecting circuitry (150) that connects the first stack (140) of IC layers to the second stack (160) of IC layers to form the compact multi-stage switching network. The stacks (140, 160) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection.

Abstract: A method includes providing a superconducting material having pinning sites that can pin magnetic vortices within the superconducting material. The method also includes pinning one or more magnetic vortices at one or more of the pinning sites. An information storage apparatus includes a superconducting material, doped particles within the superconducting material that can pin dipole magnetic vortices, a magnetic tip that generates pinned magnetic vortices and a magnetic detector that detects pinned magnetic vortices.

Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.

Abstract: The present invention generally involves an extra-substrate control system comprising a first substrate, attached to which is at least one superconducting structure, and a second substrate, connected to which is at least one element of circuitry, wherein the superconducting structure and the circuitry interact, so that a change in a state of the superconducting structure can be detected by the circuitry. The present invention also provides a quantum computing apparatus comprising a first substrate, attached to which is one or more layers of material, at least one of which is a superconducting material, a second substrate, deposited on which is a flux shield and on the flux shield is at least one element of circuitry, wherein the superconducting material and the second substrate are separated by a mean distance that is small enough to permit coupling between the element of circuitry and the superconducting material.

Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

Abstract: A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble organic insulating material. The superconducting integrated circuit is produced by a method Eat includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.

Abstract: A switching device has an S (Superconductor)-N (Normal Metal)-S superlattice to control the stream of electrons without any dielectric materials. Each layer of said Superconductor has own terminal. The superlattice spacing is selected based on “Dimensional Crossover Effect”. This device can operate at a high frequency without such energy losses as devices breaking the superconducting state. The limit of the operation frequency in the case of the Nb/Cu superlattice is expected to be in the order of 1018 Hz concerning plasmon loss energy of the normal metals (Cu; in the order of 103 eV).

Abstract: A superconductor integrated circuit (10) includes a silicon substrate (12) a niobium ground layer (14), an anodized niobium first ground insulator layer (16), a second ground insulator layer (22), a molybdenum nitrogen (MoNx) resistor (18) provided between the first and second ground insulator layers (16, 22), a Josephson junction (23) provided above the first and second ground insulator layers (16, 22), first and second oxide insulators (27, 30), and a niobium interconnect (28) for providing electrical communication with the Josephson junction. The MoNx first resistor (18) provides a sheet resistance of between 3-5 ohms/sq at 4° K with a thickness of approximately 95 nm and enables the superconductor integrated circuit (10) to have a critical current density between 6-8 kA/cm2.

Abstract: A process for the formation of structures in microelectronic devices such as integrated circuit devices wherein a patterned layer of a metal, alloy, nitride or silicide is subjected to a low temperature, wide beam electron beam annealing. The process involves depositing a silicide, nitride, metal, or metal alloy layer onto a substrate; and then overall flood exposing said entire layer to electron beam radiation under conditions sufficient to anneal the layer.

Abstract: A method and structure for a d-wave qubit structure includes a qubit disk formed at a multi-crystal junction (or qubit ring) and a superconducting screening structure surrounding the qubit. The structure may also include a superconducting sensing loop, where the superconducting sensing loop comprises an s-wave superconducting ring. The structure may also include a superconducting field effect transistor.

Abstract: A detector for detecting electromagnetic radiation incident thereon over a desired range of frequencies exhibits a given responsivity and includes an output and first and second non-insulating layers, which layers are spaced apart such that a given voltage can be applied thereacross. The first non-insulating layer is formed of a metal, and the first and second non-insulating layers are configured to form an antenna structure for receiving electromagnetic radiation over the desired range of frequencies. The detector further includes an arrangement disposed between the first and second non-insulating layers and configured to serve as a transport of electrons between the first and second non-insulating layers as a result of the electromagnetic radiation being received at the antenna structure.

Abstract: An electrically stabilized thin-film high-temperature superconductor includes a superconductive layer (32) applied over a flat metallic substrate (31) and connected to the metallic substrate (31) so that electrical contact between the superconductive layer (32) and the metallic substrate (31) is distributed over the area of the metallic substrate (31).

Abstract: A ferroelectric is used to switch a superconductor computer element. Part of the superconductor element can be a high temperature superconductor layer, doped to the vicinity of a superconductor insulator transition. The ferroelectric overlies the superconductor layer, forming a heterostructure. A voltage can be applied to polarize the ferroelectric. This polarization in turn generates an electric field for the superconductor layer, effectively changing its doping. For sufficiently large voltages the superconductor transitions into an insulating state. When included into a sensor, this heterostructure can function as a switch, used in relation to reading the state of qubits. When coupling two qubits, this heterostructure can be used to control the entanglement of the two qubits.

Abstract: A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer disposed exterior to the ultra-thin film bonding layer. The Me is a metal other than copper and, preferably, is zinc. The concentration of the Me is less than about 5 atomic percent, preferably less than about 2 atomic percent, and even more preferably, less than about 1 atomic percent. In a preferred embodiment of the metallized structure, the dielectric layer, ultra-thin film bonding layer and the copper-Me alloy layer are all disposed immediately adjacent one another. If desired, a primary conductor, such as a film of copper, may be formed exterior to the foregoing layer sequence. The present invention also contemplates methods for forming the foregoing structure as well as electroplating baths that may be used to deposit the copper-Me alloy layer.

Abstract: A memory cell section includes a first wiring which is extended in a first direction, and a second wiring which is extended in a second direction different from the first direction, and a third wiring which is disposed between the first and second wirings, and a first magneto resistive effect element which is disposed at an intersection of the first and second wirings between the first and second wirings, and is connected to the second and third wirings. Further, a peripheral circuit section includes a fourth wiring, and a fifth wiring which is disposed above the fourth wiring, and a second magneto resistive effect element which is disposed between the fourth and fifth wirings and is connected to the fourth and fifth wirings to be used as a resistive element.