Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

Abstract: Apparatus is disclosed in which at least one resistive switching element is interposed between at least a first and a second conducting electrode element. The resistive switching element comprises a metal oxynitride. A method for making such a resistive switching element is also disclosed.

Abstract: A method of manufacturing a semiconductor storage device according to an embodiment includes: stacking a first wiring layer; stacking a memory cell layer on the first wiring layer; and stacking a stopper film on the memory cell layer. The method of manufacturing a semiconductor storage device also includes: etching the stopper film, the memory cell layer, and the first wiring layer; polishing an interlayer insulating film to the stopper film after burying the stopper film, the memory cell layer, and the first wiring layer with the interlayer insulating film; performing a nitridation process to the stopper film and the interlayer insulating film to form an adjustment film and a block film on surfaces of the stopper film and the interlayer insulating film, respectively; and forming a second wiring layer on the adjustment film, the second wiring layer being electrically connected to the adjustment film.

Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.

Abstract: Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.

Abstract: A metal-insulator transition switching device includes a first electrode and a second electrode. A channel region which includes a bulk metal-insulator transition material separates the first electrode and the second electrode. A method for forming a metal-insulator transition switching device includes depositing a layer of bulk metal-insulator transition material in between a first electrode and a second electrode to form a channel region and forming a gate electrode operatively connected to the channel region.

Abstract: Provided is a switching device including ion conducting part 4 having an ion conductor, first electrode 1 formed at a first gap away from ion conducting part 4, second electrode 2 formed to be in contact with ion conducting part 4 and third electrode 3 formed at a second gap away from ion conducting part 4. Second electrode 2 supplies metal ions to the ion conductor, or receives the metal ions from the ion conductor to precipitate metal corresponding to the metal ions.

Abstract: A complementary logic element including first and second transistor elements. The first and second gate electrodes of the two transistor elements are electrically parallel to form a common gate. Both the coupling layers of the first and the second transistor element include a resistance switching material, a conductivity of which may be altered by causing an ion concentration to alter if an electrical voltage signal of an appropriate polarity is applied. The first and second transistor elements also include an ion conductor layer that is capable of accepting ions from the coupling layer and of releasing ions into the coupling layer. The coupling layers and ion conductor layers are such that the application of an electrical signal of a given polarity to the gate enhances the electrical conductivity of the first coupling layer and diminishes the electrical conductivity of the second, or vice versa.

Abstract: An electronic device (100), the electronic device (100) comprises a substrate (101), a first electrode (102) formed at least partially on the substrate (101), a second electrode (103) formed at least partially on the substrate (101), a convertible structure (104) connected between the first electrode (102) and the second electrode (103), and a spacer element (105) connected between the first electrode (102) and the second electrode (103) and adapted for spacing the convertible structure (104) with regard to a surface of the substrate (101).

Abstract: Provided is a switching device including ion conducting part 4 having an ion conductor, first electrode 1 formed at a first gap away from ion conducting part 4, second electrode 2 formed to be in contact with ion conducting part 4 and third electrode 3 formed at a second gap away from ion conducting part 4. Second electrode 2 supplies metal ions to the ion conductor, or receives the metal ions from the ion conductor to precipitate metal corresponding to the metal ions.

Abstract: The switching element of the present invention is of a configuration that includes: a first electrode (14) and a second electrode (15) provided separated by a prescribed distance; a solid electrolyte layer (16) provided in contact with the first electrode (14) and the second electrode (15); a third electrode (18) that can supply metal ions and that is provided in contact with the solid electrolyte layer (16); and a metal diffusion prevention film (17) that covers points of the surface of the solid electrolyte layer (16) that are not in contact with the first electrode (14), the second electrode (15) or the third electrode (18). This configuration prevents the adverse effect of metal ions upon other elements.

Abstract: A multi-terminal electrically actuated switch comprises a source electrode, a drain electrode, and an active region physically connected to both electrodes. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). A gate electrode is physically connected to the source/sink region. Methods of operating the switch are also provided.

Abstract: A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

Abstract: A semiconductor structure that includes two programmable vias each of which contains a phase change material that is integrated with a heating material. In particular, the present invention provides a structure in which two programmable vias, each containing a phase change material, are located on opposing surfaces of a heating material. Each end portion of an upper surface of the heating material is connected to a metal terminal. These metal terminals, which are in contact with the end portions of the upper surface of the heating material, can be each connected to an outside component that controls and switches the resistance states of the two programmable vias. The two programmable vias of the inventive structure are each connected to another metal terminal. These metal terminals that are associated with the programmable vias can be also connected to a circuit block that may be present in the structure.

Abstract: Programmable resistive memory cells are accessed by semiconductor diode structures. Manufacturing methods and integrated circuits for programmable resistive elements with such diode structures are also disclosed.

Abstract: There is provided a semiconductor device able to increase the mobility of carriers and reduce the current in the OFF state. The semiconductor device includes a gate electrode, an insulating layer on the gate electrode, a first electrode on the insulating layer, a second electrode on the insulating layer at an interval with the first electrode, an organic semiconductor layer disposed in the interval between the first electrode and the second electrode and covering at least part of the first electrode and the second electrode, and a first resistance layer formed on the organic semiconductor layer and having an electrical resistance lower than that of the organic semiconductor layer. The first resistance layer is formed from conductive polymers.

Abstract: The invention relates to a layered construction for a Gunn diode. The layered construction comprises a series of stacked layers consisting of a first highly doped nd GaAs layer (3), a graded AlGaAs layer (5), which is placed upon the first highly doped layer (3), whereby the aluminum concentration of this layer, starting from the boundary surface to the first nd GaAs layer (3), decreases toward the opposite boundary surface of the AlGaAs layer (5), and of a second highly doped n+ layer (7). An undoped intermediate layer (4, 6) serving as a diffusion or segregation stop layer is placed on at least one boundary surface of the AlGaAs layer (5) to one of the highly doped layers (3, 7) and prevents an unwanted doping of the graded layer.

Abstract: A precision RF passive component including: a silicon substrate; a first dielectric layer deposited above the silicon substrate; a first metal layer formed above the first dielectric layer; a second dielectric layer formed above the first metal layer; and a second metal layer formed above the second dielectric layer. In one embodiment a passivation layer is added above the second metal layer. In an exemplary embodiment the first metal layer includes a first adhesion layer, a metal sub-layer, and a second adhesion layer; and the second dielectric layer includes a first diffusion barrier layer, a dielectric sub-layer second diffusion barrier. In an exemplary embodiment, the metal sub-layer includes copper. In another exemplary embodiment the dielectric sub-layer includes SiO2 or Si3N4 between diffusion barrier layers including SiN.

Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.

Abstract: A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A two-terminal NDR device can be formed by coupling the gate and drain of an NDR-capable FET, such that the coupled gate and drain form a first terminal and the source of the NDR-capable FET forms the second terminal. By applying an appropriate body bias between the body and source of an NDR-capable FET configured in this manner, the NDR-capable FET can be forced to operate with a negative threshold voltage, thereby allowing the resulting two-terminal device to exhibit the desired NDR characteristics. This two-terminal device can, for example, be used as a load element in a static random access memory (SRAM) cell and various other circuits where the NDR behavior of the device would be beneficial.

Abstract: To provide an active electronic device which is formed from a carbon nanotube and which excels in high frequency operation and an electronic apparatus using the active electronic device. Provided are the active electronic device including: a carbon nanotube (1); a first electrode (S) connected to one end of the carbon nanotube; a second electrode (D) connected to the other end of the carbon nanotube; and a third electrode (G) facing the carbon nanotube (1) to irradiate the carbon nanotube (1) with electromagnetic waves, in which the amount of current flowing into the carbon nanotube (1) is changed by electromagnetic waves, at least high frequency electromagnetic waves, radiated from the third electrode onto the carbon nanotube (1), and the electronic apparatus using the active electronic device.

Abstract: A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion of the surface of the monolithic semiconducting substrate. An insulator precursor species is implanted beneath the surface of the recessed first portion of the monolithic semiconducting substrate, and a trench is etched around the implanted and recessed first portion of the monolithic semiconducting substrate. The insulator precursor species is activated to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate. The semiconductor on insulator structure is formed in the first portion of the monolithic semiconducting substrate, and the bulk semiconductor structure is formed in the second portion of the monolithic semiconducting substrate.

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: Provided are a semiconductor device which shows excellent negative differential conductance or negative transconductance and is manufactured without a complicated manufacturing process and a method of manufacturing the same. The semiconductor device includes a channel layer serving as a conduction region and a floating region electrically separated from the channel layer. Provided between the channel layer and the floating region is a quantum well layer constituted with a pair of barrier layers and a quantum well layer sandwiched between the pair of barrier layers. A source electrode and a drain electrode are electrically connected to the channel layer. A gate electrode is provided in an opposite position from the well layer in the floating region. When changing a drain voltage relative to a predetermined gate voltage, drain current characteristics show negative differential conductance.

Abstract: A method for forming a heterojunction bipolar transistor includes forming two sets of spacers on the sides of an emitter pedestal. After the first set of spacers is formed, first extrinsic base regions are implanted on either side of an intrinsic base. The second set of spacers is formed on the first set of spacers. Second extrinsic base regions are then implanted on respective sides of the intrinsic base. By using two sets of spacers, the first and second extrinsic base regions have different widths. This advantageously brings the combined extrinsic base structure closer to the emitter of the transistor but not closer to the collector. As a result, the base parasitic resistance is reduced along with collector-to-extrinsic base parasitic capacitance. The performance of the transistor is further enhanced as a result of the extrinsic base regions being self-aligned to the emitter and collector.

Abstract: A system and method is described for providing a robust mechanical and electrical connection between two or more circuit boards which may be employed for diagnostic purposes and/or for permanent connections. A spacer block, connection block, or pedestal, preferably made of PCB type material is preferably disposed between two PCBs. The pedestal is preferably dimensioned to space the two PCBs far enough apart that the surface mount components on two boards connected employing the inventive pedestal do not interfere with one another. The pedestal preferably provides for ample signal density and signal quality because of the block thickness and availability of insulation within the pedestal.

Abstract: A method for testing a plurality of integrated circuits. In one embodiment, a plurality of integrated circuits are arranged on a wafer. The integrated circuits are separated on the wafer across the boundary region. Testing interconnects are disposed across the boundary region to test switchable couplings included in each of the integrated circuits on the wafer. After the integrated circuits are tested on the wafer using the testing interconnects across the boundary region, the boundary region is removed, which separates the wafer into individual integrated circuit dice and severs the testing interconnects.

Abstract: There is provided a single electron device. The device has weak links with bottle-neck figure in place of the tunnel junction of the prior device. The weak links are easily formed on the same substrate by simple processes and thus the integration of the single electron device can be easily achieved.

Abstract: A surface mount circuit device (110), such as a flip chip, of the type which is attached to a conductor pattern (126) with solder bump connections (120). The solder bump connections (120) are formed by reflowing solder on shaped input/output pads (112) on the device (110), with the shape of the pads (112) being tailored to favorably affect optimal distribution, shape and height of the solder bump connections (120) following reflow soldering of the device (110) to the conductor pattern (126). The solder bump connections (120) are preferably characterized by a shape that increases the stand-off height of the device (110). The shaped solder bump connections (120) also promote stress relief during thermal cycling, improve mechanical bonding, allow better penetration of cleaning solutions, and improve flow of encapsulation materials between the device (110) and its substrate (122).

Abstract: Disclosed in this invention is a new four-terminal type and multiple delta-doped transistors with multiple functions grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD). All the epilayers are grown on n.sup.+ -GaAs substrates. The real-space transfer transistors (RST), the collector is located under the substrate, reveal very strong negative differential resistance phenomena. The RST structure using an InGaAs channel manifests superior characteristics of a very high peak-to-valley current ratio up to 430,000 at room temperature, a peak current as high as 100 mA, very sharp charge injection, and a valley current as broad as 5.5V. Meanwhile, high performance heterostructure field effect transistors can be implemented on the same wafer by further evaporating a gate between source and drain electrodes. In order to significantly reduce leakage current, an ohmic recession is made at the source and drain.

Abstract: An active matrix LCD employs a two-terminal or three-terminal switch structure employing an electrically conductive wire. The wire has an insulating layer thereon forming a wire structure. The wire structure is placed in a groove in a transparent substrate and an electrode layer is deposited on the insulating layer at spaced intervals to form an array of diodes connected in parallel. By applying a suitable voltage to the wire, all of the diodes in parallel are turned on to charge the electrodes to desired electrical potentials on one side of the liquid crystal material. An array of electrodes matching the position of the diodes on the other side of the liquid crystal material are charged to the desired potentials in order to control the color and brightness of the display by controlling the light transmittance of the liquid crystal cells between the two sets of electrodes.