Fet With Metal Source Region Patents (Class 257/902)
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Patent number: 9006826Abstract: The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends along a length (i.e., the larger dimension of the butted contact) from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.Type: GrantFiled: May 14, 2012Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Tzyh-Cheang Lee
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Patent number: 8809861Abstract: A transistor is formed having a thin film metal channel region. The transistor may be formed at the surface of a semiconductor substrate, an insulating substrate, or between dielectric layers above a substrate. A plurality of transistors each having a thin film metal channel region may be formed. Multiple arrays of such transistors can be vertically stacked in a same device.Type: GrantFiled: December 29, 2010Date of Patent: August 19, 2014Assignee: STMicroelectronics Pte Ltd.Inventors: Olivier Le Neel, Ravi Shankar, Calvin Leung
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Patent number: 8723235Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.Type: GrantFiled: February 20, 2012Date of Patent: May 13, 2014Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8217386Abstract: A vertical field effect transistor (FET) comprises a gate electrode and a first electrode layer having a dielectric layer interposed between these electrodes and a semiconducting active layer electrically coupled to the first electrode. The active layer and the dielectric layer sandwich at least a portion of the first electrode where at least one portion of the active layer is unshielded by the first electrode such that the unshielded portion is in direct physical contact with the dielectric layer. A second electrode layer is electrically coupled to the active layer where the second electrode is disposed on at least a portion of the unshielded portion of the active layer such that the second electrode can form electrostatic fields with the gate electrode upon biasing in unscreened regions near the first electrode.Type: GrantFiled: June 29, 2007Date of Patent: July 10, 2012Assignee: University of Florida Research Foundation, Inc.Inventors: Andrew Gabriel Rinzler, Zhuangchun Wu, Bo Liu
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Patent number: 8183611Abstract: A spin transistor that includes: a semiconductor substrate including an upper cladding layer and a lower cladding layer, and a channel layer interposed between the upper and lower cladding layers; a ferromagnetic source and a ferromagnetic drain formed on the semiconductor substrate and spaced from each other in a length direction of the channel layer; and a gate electrode formed on the semiconductor substrate between the source and the drain and having applied a gate voltage thereto to control a spin precession of an electron passing through the channel layer, wherein the semiconductor substrate includes a first carrier supply layer of a first conductivity type disposed below the lower cladding layer and supplying carriers to the channel layer, and a second carrier supply layer of a second conductivity type opposite to the first conductivity type formed on the upper cladding layer and supplying the carriers to the channel layer.Type: GrantFiled: August 18, 2010Date of Patent: May 22, 2012Assignee: Korea Institute of Science and TechnologyInventors: Hyung Jun Kim, Jin Dong Song, Hyun Cheol Koo, Kyung Ho Kim, Suk Hee Han
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Patent number: 8120072Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.Type: GrantFiled: July 24, 2008Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8035141Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon.Type: GrantFiled: October 28, 2009Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Jinghong Li, Viorel Ontalus, Zhengmao Zhu
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Patent number: 7960734Abstract: A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates.Type: GrantFiled: July 15, 2010Date of Patent: June 14, 2011Assignees: STMicroelectronics (Crolles 2) SAS, Interuniversitair Micro-Electronica CentrumInventor: Damien Lenoble
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Patent number: 7608901Abstract: Disclosed herein is a spin transistor including: a semiconductor substrate having a channel layer formed therein; first and second electrodes which are formed to be spaced apart from each other on the substrate at a predetermined distance along a longitudinal direction of the channel layer; a source and drain which include magnetized ferromagnetic materials and are formed to be spaced apart form each other between the first electrode and the second electrode at a predetermined distance along the longitudinal direction of the channel layer; and a gate which is formed on the substrate between the source and the drain, and adjusts spin orientations of electrons passing through the channel layer, wherein the electrons passing through the channel layer are spin-aligned at a lower side of the source by a stray magnetic field of the source and spin-filtered at a lower side of the drain by a stray field of the drain.Type: GrantFiled: July 12, 2007Date of Patent: October 27, 2009Assignee: Korea Institute of Science and TechnologyInventors: Hyun Cheol Koo, Jong Hwa Eom, Suk Hee Han, Joon Yeon Chang, Hyung Jun Kim
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Patent number: 7560758Abstract: The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.Type: GrantFiled: June 29, 2006Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Huilong Zhu, Hong Lin
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Patent number: 7259432Abstract: A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film formed so as to be aligned in a direction parallel to the principal surface of the substrate and adjacent to the gate electrode with a part of the first interlayer insulating film interposed therebetween. The second interlayer insulating film has a lower relative permeability than the first interlayer insulating film.Type: GrantFiled: March 2, 2005Date of Patent: August 21, 2007Assignee: Matsushita Electric Industrisl Co., Ltd.Inventor: Masaki Tamaru
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Patent number: 7081646Abstract: There are disclosed TFTs that have excellent characteristics and can be fabricated with a high yield. The TFTs are fabricated, using an active layer crystallized by making use of nickel. Gate electrodes are comprising tantalum. Phosphorus is introduced into source/drain regions. Then, a heat treatment is performed to getter nickel element in the active layer and to drive it into the source/drain regions. At the same time, the source/drain regions can be annealed out. The gate electrodes of tantalum can withstand this heat treatment.Type: GrantFiled: August 28, 2001Date of Patent: July 25, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 6828610Abstract: A magnetic tunnel junction is fabricated by forming pinned and sense layers; and re-setting a magnetization vector of at least one of the layers.Type: GrantFiled: July 23, 2003Date of Patent: December 7, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Thomas Anthony, Lung Tran, Manish Sharma
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Patent number: 6809379Abstract: The invention relates to a field effect transistor with a drain region, a source region, a channel region and a gate region. The gate region is provided with a metal layer.Type: GrantFiled: February 24, 2003Date of Patent: October 26, 2004Assignee: Infineon Technologies AGInventor: Franz Kreupl
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Patent number: 6713820Abstract: A semiconductor device is provided in which each of contacts between a source and a drain of a MOS transistor and a metallic wiring is either a contact having an arbitrary one side longer than the other side, or source contacts and well contacts are made batting contacts each having an arbitrary one side of a diffusion region having the same polarity as that of a well shorter than the other side. Thus, the contact shape is longitudinal in a transistor width direction, which makes it possible that a large current is caused to flow with a small interval of gates thereof.Type: GrantFiled: April 8, 2002Date of Patent: March 30, 2004Assignee: Seiko Instruments Inc.Inventors: Toshihiko Omi, Kazutoshi Ishii
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Publication number: 20010056542Abstract: A system for protecting an electronic device from mechanical intrusion attempt. An intrusion barrier able to detect mechanical intrusion by means of circuit traces which detect any change in the resistance characteristics of the electric circuit. These circuit traces function as a resistors and they are connected together to form a Wheatstone bridge. According to the present invention the logical lay-out of these connections is selected so that the voltage difference between two adjacent traces is minimized. In this way the current leakage effect is limited to the minimum.Type: ApplicationFiled: May 7, 2001Publication date: December 27, 2001Applicant: International Business Machines CorporationInventors: Mario Leonardo Cesana, Roberto Antonio Zavatti
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Publication number: 20010019131Abstract: The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (e.g. InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (e.g. p+-GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (e.g. InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer. The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET.Type: ApplicationFiled: March 2, 2001Publication date: September 6, 2001Inventors: Takehiko Kato, Kazuki Ota, Hironobu Miyamoto, Naotaka Iwata, Masaaki Kuzuhara
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Patent number: 6180987Abstract: A method for fabricating an integrated circuit is presented. In the method, a substrate is provided having a dielectric base layer formed thereupon. Source/drain trenches may be formed in the dielectric base layer. Source/drain structures containing metal may then be formed within the source/drain trenches. The upper surface of the dielectric base layer is then recessed a recession depth below upper surfaces of the source/drain structures. A gate trench is thus defined between upper portions of the source/drain structures extending above the upper surface of the dielectric base layer. A conductive channel layer is subsequently formed at least partially within the gate trench. A gate conductive layer may then be formed above the conductive channel layer and at least partially within the gate trench.Type: GrantFiled: February 11, 1999Date of Patent: January 30, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, H. Jim Fulford, Jr.
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Patent number: 6130462Abstract: A novel vertical poly load device in 4T SRAM and a method for fabricating the same are disclosed. The poly load structure is a vertical device formed on a buried contact. The poly load vertical device is constructed by forming a hollow in a planarized dielectric layer with a high temperature oxide layer on the walls of the hollow and with lightly doped n-type polysilicon in the hollow. The poly load is connected to the respective drain of the driver transistor through the buried contact and to the gate of the respective gate of the other driver transistor through a connecting line. The resistance of the poly load will increase, as the voltage of the buried contact becomes low thereby reducing the standby current.Type: GrantFiled: July 26, 1999Date of Patent: October 10, 2000Assignee: Worldwide Semiconductor Manufacturing Corp.Inventors: Ching-Nan Yang, Chia-Chen Liu
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Patent number: 6057583Abstract: A transistor is provided and formed using self-aligned low-resistance source and drain regions within a metal-oxide semiconductor (MOS) process. The gate of the transistor may also be formed from a low-resistance material such as a metal. The source and drain regions of the transistor are configured upon a semiconductor substrate, and the transistor channel is within the substrate. A protective dielectric layer is deposited over the semiconductor substrate. Source/drain trenches are formed in the protective dielectric layer and subsequently filled with sacrificial dielectrics. The protective dielectric lying between these sacrificial dielectrics is removed, and replaced with sidewall spacers, a gate dielectric, and a gate conductor which may be formed from a low-resistance metal. The sacrificial dielectrics are subsequently removed and replaced with source/drain regions which are preferably formed from a low-resistance metal.Type: GrantFiled: January 6, 1999Date of Patent: May 2, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Mark I. Gardner, H. Jim Fulford, Jr.
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Patent number: 5994727Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.Type: GrantFiled: September 30, 1997Date of Patent: November 30, 1999Assignee: Samsung Electronics Co., Ltd.Inventor: Jong Boong Lee
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Patent number: 5962893Abstract: An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the source electrode on the n-semiconductor layer through a gate insulating film. When a voltage is applied to the gate electrode to lower the Schottky barrier height at the interface between the source electrode and the n-semiconductor layer, electrons are injected from the source electrode into the n-semiconductor layer, and a current flows in the semiconductor device. A diffusion layer which prevents a decrease in manufacturing time is not required to form in the n-semiconductor layer, and a channel which causes an increase in ON state voltage is not present.Type: GrantFiled: January 16, 1996Date of Patent: October 5, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Takashi Shinohe
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Patent number: 5942790Abstract: A new conceptional transistor and a method for manufacturing, which increases the integration of semiconductor devices using conventional MOS devices are provided. The present invention provides a transistor in which a structure of metal-insulator film-metal dot-metal (MIMIM), metal-insulator film-metal dot-semiconductor (MIMS), or semiconductor-metal dot-semiconductor (SMS) is formed, using junction of electrodes operating as a source and a drain having a metal dot of nm therebetween, and the current flow between source and drain is controlled by controlling tunneling and Schottky barrier formed between the source and the metal dot using the method of controlling electrical potential of metal dot through charging effect of gate electrode isolated by a thick insulator.Type: GrantFiled: August 20, 1998Date of Patent: August 24, 1999Assignee: Electronics and Telecommunications Research InstituteInventors: Kang Ho Park, Jeong Sook Ha
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Patent number: 5663584Abstract: (MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught.Type: GrantFiled: December 29, 1994Date of Patent: September 2, 1997Inventor: James D. Welch
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Patent number: 5428234Abstract: A semiconductor device which comprises a semiconductor substrate having thereon a channel region, said channel region comprising (A) a channel, and (B) a metallic layer or a compound layer of a metal with a constituent material of the semiconductor substrate, provided that at least a part of said metallic layer or said compound layer is included in said channel. The semiconductor device has stable characteristics with high operation speed, and yet, is capable of being fabricated by a simple process.Type: GrantFiled: September 16, 1994Date of Patent: June 27, 1995Assignee: Sony CorporationInventor: Hirofumi Sumi
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Patent number: 5319237Abstract: A self-encapsulated power conductor component with improved heat transfer has a chip bearing at least one power transistor having at least one interdigitated electrode, provided with an air bridge, and a sink provided with at least one metal islet in relief. The air bridge is reinforced and the chip is brazed in reverse to the islet of the sink by its air bridge. Other islets brazed to the metallizations on the rim of the chip reinforce the mechanical fixing. The access to the electrodes is obtained by via holes and the second face of the substrate may receive non-integrable components. The device can be applied to power transistors and integrated circuits, notably on GaAs.Type: GrantFiled: September 27, 1993Date of Patent: June 7, 1994Assignee: Thomson Composants MicroondesInventor: Patrick Legros
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Patent number: 5162890Abstract: In a multi-layered integrated memory circuit, a method for using sacrificial layers and insulating "sticks" is disclosed to provide a contact between two layers, where the contact does not short to an intervening layer. This invention provides this with minimal extra processing by using sacrificial layers with appropriate etch and etch stop properties. As these layers are etched, additional layers which alternate in the same conducting/insulating pattern are exposed. Each etch stops on either a conductive or insulative layer. A contact layer may then be deposited which connects the uppermost capacitor plate to the pass transistor of the memory cell.Type: GrantFiled: April 5, 1991Date of Patent: November 10, 1992Assignees: Ramtron Corporation, NMB Semiconductor CorporationInventor: Douglas B. Butler