Fet Configuration Adapted For Use As Static Memory Cell Patents (Class 257/903)
  • Patent number: 10411019
    Abstract: A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.
    Type: Grant
    Filed: June 18, 2016
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hidehiro Fujiwara, Wei-Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 10373676
    Abstract: Objects are to provide a semiconductor device with a novel structure, to provide a semiconductor device with high resistance to noise, to provide a semiconductor device with a small chip area, and to provide a semiconductor device with low power consumption. In a memory cell included in a frame memory, a transistor containing an oxide semiconductor and a transistor containing silicon are used in combination to retain charge, whereby data is retained. In this structure, turning off the transistor containing an oxide semiconductor can prevent data fluctuations even if power noise through a wiring is generated.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Takayuki Ikeda, Naoaki Tsutsui
  • Patent number: 10360337
    Abstract: A method of forming an integrated circuit includes: forming a conductive grid on a semiconductor substrate; selecting a plurality of first conductive lines from a plurality of non-continuous conductive lines according to a first mask layer assigned to the plurality of first conductive lines; selecting a plurality of second conductive lines from the plurality of non-continuous conductive lines according to a second mask layer assigned to the plurality of second conductive lines, wherein the second mask layer different from the first mask layer, and the plurality of second conductive lines is electrically connected to the plurality of first conductive lines via the plurality of continuous conductive lines; and replacing the plurality of second conductive lines by a plurality of third conductive lines respectively, wherein the plurality of third conductive lines is assigned to the first mask layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hiranmay Biswas, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 10068909
    Abstract: The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1), a second inverter comprises a second pull-up transistor (PL2) and a second pull-down transistor (PD2), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD1, the PD2, the SW, and the PG comprise a first diffusion region, the PL1 and the PL2 comprise a second diffusion region.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chien-Hung Chen
  • Patent number: 10020049
    Abstract: The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: July 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Chih-Wei Tsai
  • Patent number: 9997523
    Abstract: A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Toshiro Nakanishi, Donghwan Kim, Suhwan Kim, Yubin Kim, Jin Soak Kim, Gabjin Nam, Sungkweon Baek, Taehyun An, Eunae Chung
  • Patent number: 9984972
    Abstract: A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: May 29, 2018
    Assignee: SK hynix Inc.
    Inventors: Tae Kyung Kim, Chul Young Park, Hyoung Soon Yune
  • Patent number: 9978798
    Abstract: Recording photons incident on an image sensor; and storing the recorded photons on the image sensor in varying densities, wherein the photons are recorded in varying densities by storing electrons non-linearly. Key words include a sensor and storing non-linearly.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: May 22, 2018
    Assignees: SONY CORPORATION, SONY PICTURES ENTERTAINMENT INC.
    Inventor: Kazunori Tanaka
  • Patent number: 9966379
    Abstract: A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source electrode of the first access transistor may be electrically connected to both an output terminal of the first inverter and an input terminal the second inverter. The drain electrode of the first access transistor may be asymmetrical to the source electrode of the first access transistor with reference to a gate electrode of the first access transistor. A drain electrode of the second access transistor or a source electrode of the second access transistor may be electrically connected to both an output terminal of the second inverter and an input terminal the first inverter.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: May 8, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Gong Zhang
  • Patent number: 9829514
    Abstract: To provide a current detection circuit which suppresses a change in characteristics of a PMOS transistor on the non-inversion input terminal side of a differential amplifier due to NBTI and causes no change in threshold value at which an output voltage of the current detection circuit is inverted. A voltage limiting circuit which limits a voltage drop is provided between a non-inversion input terminal of a differential amplifier and a source of a PMOS transistor on the inversion input terminal side.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 28, 2017
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventor: Toshiyuki Tsuzaki
  • Patent number: 9754659
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 9704564
    Abstract: A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9465559
    Abstract: In embodiments of the present invention improved capabilities are described for emulating multiple-time programmable memory utilizing one-time programmable memory, the memory comprising a plurality of one time programmable (OTP) memory locations for storing information, the plurality of OTP memory locations configured to operate as a single emulated many time programmable (eMTP) memory location, wherein the plurality of OTP memory locations operating as an eMTP memory location are associated with one address, the one address readable and writable.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: October 11, 2016
    Assignee: TEGO, INC.
    Inventors: Timothy P. Butler, Javier Berrios, Steve Beckhardt, Robert W. Hamlin, Larry Moore, David Puleston, Leonid Mats
  • Patent number: 9431066
    Abstract: A circuit comprises a first voltage line, a second voltage line parallel to the first voltage line, and a bit line between the first voltage line and the second voltage line. The bit line is separated from the first voltage line by a minimum distance allowed by a design rule. The bit line is closer to the first voltage line than to the second voltage line. A first capacitance value between the bit line and the first voltage line is different than a second capacitance value between the bit line and the second voltage line.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: August 30, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Lin Chen, Feng-Ming Chang, Huai-Ying Huang, Kian-Long Lim, Ping-Wei Wang
  • Patent number: 9424447
    Abstract: In embodiments of the present invention improved capabilities are described for a stand-alone RFID sensor apparatus comprising a passive radio frequency identification (RFID) tag configured to read sensor information from a sensor, the passive RFID tag comprising an RF network node and a communication facility, the RF network node comprising (i) an RF and analog block for receiving and transmitting an RFID interrogation signal, (ii) a data processing and controller block for digital information processing, (iii) a memory store, and (iv) a power management block for managing power requirements of the RFID sensor apparatus, and the communications facility linking the sensor and the passive RFID tag, wherein the data processing and controller block manages communication of the sensor information through the communications facility.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: August 23, 2016
    Assignee: TEGO, INC.
    Inventors: David Puleston, Robert W. Hamlin, Steven Benoit, Leonid Mats
  • Patent number: 9336859
    Abstract: A memory array includes a first memory cell and a second memory cell aligned along a column direction. Each of the first memory cell and the second memory cell includes a pair of cross-coupled inverters, a first switch on a first side, along the column direction, of the pair of cross-coupled inverters, a second switch aligned with the first switch along the column direction, on a second side of the pair of cross-coupled inverters opposing to the first side, a third switch on the first side of the pair of cross-coupled inverters, and a fourth switch aligned with the third switch along the column direction, on the second side of the pair of cross-coupled inverters. The memory array also includes a first data line, a first complementary data line, a second data line and a second complementary data line.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 10, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Kuei Lin, Hung-Jen Liao, Jhon Jhy Liaw, Yen-Huei Chen
  • Patent number: 9190404
    Abstract: Provided are a semiconductor device and a method of fabricating the same. The device may include a transistor on a substrate comprising a gate insulating pattern, a gate electrode and an impurity region, a shared contact plug electrically connected to the gate electrode and the impurity region, and an etch-stop layer between side surfaces of the gate electrode and the shared contact. The shared contact plug may include a first conductive pattern electrically connected to the first impurity region and a second conductive pattern electrically connected to the gate electrode, and a top surface of the first conductive pattern may be higher than a top surface of the gate electrode.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: November 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hak-Sun Lee, Myeongcheol Kim, Cheol Kim, Sanghyun Lee
  • Patent number: 9029956
    Abstract: A static random access memory cell is provided that includes first and second inverters formed on a substrate each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters resides over first regions below the buried oxide layer and having a first doping level and applied bias providing a first voltage threshold for the pull-down transistors. A pair of passgate transistors is coupled the cell nodes of the first and second inverters, and each is formed over second regions below the buried oxide layer and having a second doping level and applied bias providing a second voltage threshold for the passgate transistors. The first voltage threshold differs from the second voltage threshold providing electrical voltage threshold control between the pull-down transistors and the passgate transistors.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: May 12, 2015
    Assignee: Global Foundries, Inc.
    Inventors: Randy W. Mann, Scott D. Luning
  • Patent number: 9006841
    Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Shishir Kumar, Dibya Dipti, Pierre Malinge
  • Patent number: 9006826
    Abstract: The present disclosure relates to an SRAM memory cell. The SRAM memory cell has a semiconductor substrate with an active area and a gate region positioned above the active area. A butted contact extends along a length (i.e., the larger dimension of the butted contact) from a position above the active area to a position above the gate region. The butted contact contains a plurality of distinct regions having different widths (i.e., the smaller dimensions of the butted contact), such that a region spanning the active area and gate region has width less than the regions in contact with the active area or gate region. By making the width of the region spanning the active area and gate region smaller than the regions in contact with the active area or gate, the etch rate is reduced at a junction of the gate region with the active area, thereby preventing etch back of the gate material and leakage current.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Tzyh-Cheang Lee
  • Patent number: 9000503
    Abstract: A semiconductor device in which wirings are formed adequately and electrical couplings are made properly in an SRAM memory cell. In the SRAM memory cell of the semiconductor device, a via to be electrically coupled to a third wiring as a word line is directly coupled to a contact plug electrically coupled to the gate wiring part of an access transistor. Also, another via to be electrically coupled to the third wiring as the word line is directly coupled to a contact plug electrically coupled to the gate wiring part of another access transistor.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Nobuo Tsuboi
  • Patent number: 8980707
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 8969932
    Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 3, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy C. Wei, Akshey Sehgal, Seung Y. Kim, Teck Jung Tang, Francis M. Tambwe
  • Patent number: 8947912
    Abstract: Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: February 3, 2015
    Assignee: University of Virginia Licensing & Ventures Group
    Inventors: Benton H. Calhoun, Randy W. Mann
  • Patent number: 8908419
    Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
  • Patent number: 8884373
    Abstract: A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Sato, Hideyuki Arai, Takayuki Yamada
  • Patent number: 8878307
    Abstract: In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is a doped SiGe shared contact between (a) a gate conductor region shared by an N-channel MOSFET and a P-channel MOSFET and (b) a drain diffusion region of an N-channel MOSFET or of a P-channel MOSFET.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: November 4, 2014
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Koji Miyata
  • Patent number: 8853700
    Abstract: Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Viraj Y. Sardesai, Robert C. Wong
  • Patent number: 8797787
    Abstract: A memory bit cell includes a latch, a write port coupled to the latch, and a read port coupled to the latch. The write port includes a first set of devices having a first threshold voltage and a second set of devices having a second threshold voltage that is greater than the first threshold voltage. The read port includes a third set of devices having a third threshold voltage that is less than the first threshold voltage.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 8779528
    Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up Fin Field-Effect Transistor (FinFET) and a second pull-up FinFET, and a first pull-down FinFET and a second pull-down FinFET forming cross-latched inverters with the first pull-up FinFET and the second pull-up FinFET. A first pass-gate FinFET is connected to drains of the first pull-up FinFET and the first pull-down FinFET. A second pass-gate FinFET is connected to drains of the second pull-up FinFET and the second pull-down FinFET, wherein the first and the second pass-gate FinFETs are p-type FinFETs. A p-well region is in a center region of the SRAM cell and underlying the first and the second pull-down FinFETs. A first and a second n-well region are on opposite sides of the p-well region.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 8748978
    Abstract: A sense-amp transistor for a semiconductor device and a method for manufacturing the same are disclosed. A sense-amp transistor for a semiconductor device includes a recess array formed in a gate region of a sense-amp, a plurality of buried gates formed in each recess of the recess array so as to form a vertical channel region, and an upper gate configured to form a horizontal channel region in an active region between the buried gates. As a result, the number of additional processes is minimized, and the sensing margin of the sense-amp is guaranteed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: June 10, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang Ho Lee
  • Patent number: 8723235
    Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8710592
    Abstract: An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunme Lim, Hanbyung Park, Ho-Kwon Cha
  • Patent number: 8674413
    Abstract: One illustrative device disclosed herein includes a substantially un-doped layer of a semiconductor material positioned above a semiconducting substrate, a device isolation structure, at least a portion of which is positioned in a trench that extends through the substantially un-doped semiconductor material and into the substrate, a plurality of outer fins and at least one inner fin defined in the substantially un-doped layer of semiconductor material, wherein the at least one inner fin is positioned laterally between the plurality of outer fins and wherein a width of a bottom of each of the plurality of outer fins is greater than a width of a bottom of the inner fin, and a gate electrode positioned around at least a portion of the plurality of outer fins and the inner fin.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 18, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Min-hwa Chi
  • Patent number: 8659088
    Abstract: An SRAM cell includes six four-terminal double gate FETs formed on four semiconductor thin film plates, in which first and third FETs, fourth and fifth FETs, third and fourth FETs, and second and sixth FETs neighbor each other and logic signal input gates thereof are formed on facing side surfaces of respective semiconductor thin film plates; the second and sixth FETs sandwich second and third plates; the threshold voltage control gates of the second, third, fourth, and sixth FETs are connected in common to a first bias wiring; threshold voltage control gates of the first and fifth FETs are connected in common to a second bias wiring; and the word line and the first and second bias wirings are arranged in a direction perpendicular to the alignment direction of the first to the fourth plates.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 25, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventor: Shinichi Ouchi
  • Patent number: 8643110
    Abstract: A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned conductor that provides a biasing signal to distinct regions of the silicon layer of the SOI. The conductor is recessed into the insulator layer to provide a substantially planar interface with the silicon layer. The conductor is connected to a bias voltage source. In an embodiment, a plurality of conductor is provided that respectively connected to a plurality of voltage sources. Thus, different regions of the silicon layer are biased by different bias signals.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, John K. Zahurak
  • Patent number: 8633548
    Abstract: A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: January 21, 2014
    Assignee: Microsemi SoC Corporation
    Inventors: Fethi Dhaoui, John McCollum, Frank Hawley, Leslie Richard Wilkinson
  • Patent number: 8610196
    Abstract: In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsufumi Tanamoto, Kosuke Tatsumura, Kiwamu Sakuma, Atsuhiro Kinoshita, Shinobu Fujita, Koichi Muraoka
  • Patent number: 8604522
    Abstract: In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masataka Takebuchi, Kazuhiro Utsunomiya, Noriyasu Ikeda
  • Patent number: 8569812
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 29, 2013
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David L. Kencke, Ibrahim Ban
  • Patent number: 8542514
    Abstract: A memory structure and method to fabricate the same is described. The memory structure includes a first memory cell having a first pair of non-volatile portions. The memory structure also includes a second memory cell having a second pair of non-volatile portions. The first and second pairs of non-volatile portions are disposed in an inter-locking arrangement.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 24, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sethuraman Lakshminarayanan, Myongseob Kim
  • Patent number: 8525270
    Abstract: The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: September 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lee-Wee Teo, Ming Zhu, Chi-Ju Lee, Sheng-Chen Chung, Kai-Shyang You, Harry-Hak-Lay Chuang
  • Patent number: 8520430
    Abstract: A memory device includes a first nanowire connected to a first bit line node and a ground node, a first field effect transistor (FET) having a gate disposed on the first nanowire, a second FET having a gate disposed on the first nanowire, a second nanowire connected to a voltage source node and a first input node, a third FET having a gate disposed on the second nanowire, a third nanowire connected to the voltage source node and a second input node, a fourth FET having a gate disposed on the third nanowire, a fourth nanowire connected to a second bit line node and the ground node, a fifth FET having a gate disposed on the fourth nanowire, and a sixth FET having a gate disposed on the fourth nanowire.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight
  • Patent number: 8507990
    Abstract: A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: August 13, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaki Okuno
  • Patent number: 8488371
    Abstract: In a random access memory, one of a first conductivity type well constituting a first bit in one column group and another first conductivity type well constituting a second bit selected simultaneously to the first bit in an adjacent column group, is isolated from a common well of the first conductivity type by providing a deep well of a second conductivity type, such that the area of the deep well of the second conductivity type does not exceed the area of one column group.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: July 16, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Taiki Uemura
  • Patent number: 8476717
    Abstract: A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert C. Wong, Haining S. Yang
  • Patent number: 8445343
    Abstract: Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also disclosed.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Kim, Kihyun Hwang, Sangryol Yang, Yong-Hoon Sang, Ju-Eun Kim
  • Patent number: 8431455
    Abstract: Disclosed herein is a method of forming a memory device. In one example, the method includes performing a first ion implantation process with dopant atoms of a first type to partially form extension implant regions for a pull-down transistor and to fully form extension implant regions for a pass gate transistor of the memory device and, after performing the first ion implantation process, forming a first masking layer that masks the pass gate transistor and exposes the pull-down transistor to further processing. The method concludes with the step of performing a second ion implantation process with dopant atoms of the first type to introduce additional dopant atoms into the extension implant regions for the pull-down transistor that were formed during the first ion implantation process while masking the pass gate transistor from the second ion implantation process with the first masking layer.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: April 30, 2013
    Assignee: Globalfoundries Inc.
    Inventors: Ralf van Bentum, Nihar-Ranjan Mohapatra
  • Patent number: 8405159
    Abstract: In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanna Adachi, Shigeru Kawanaka, Satoshi Inaba
  • Patent number: 8399935
    Abstract: Circuits and methods for providing a dual gate oxide (DGO) embedded SRAM with additional logic portions, where the logic and the embedded SRAM have NMOS transistors having a common gate dielectric thickness but have different lightly doped drain (LDD) implantations formed using different LDD masks to provide optimum transistor operation. In an embodiment, a first embedded SRAM is a single port device and a second embedded SRAM is a dual port device having a separate read port. In certain embodiments, the second SRAM includes NMOS transistors having LDD implants formed using the logic portion LDD mask. Transistors formed with the logic portion LDD mask are faster and have lower Vt than transistors formed using a SRAM LDD mask. Dual core devices having multiple embedded SRAM arrays are disclosed. Methods for making the embedded SRAM are also disclosed.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: March 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw