Abstract: A ferroelectric memory device and a method of formation are disclosed. In one particular embodiment, a ferroelectric memory device comprises a first electrode layer formed on a substrate, a ferroelectric polymer layer formed on substantial portion of a first electrode layer, a thin layer of conductive ferroelectric polymer formed on a substantial portion of the ferroelectric polymer layer, where the ferroelectric polymer may be made conductive by doping with conductive nano-particles, and a second electrode layer formed on at least a portion of the carbon doped ferroelectric polymer layer.

Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.

Abstract: A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the topmost interconnect plane for providing Al bonding pads. The fuses are configured as Al fuses and, in the semiconductor structure having Cu metallization planes, are provided above the diffusion barrier of the topmost Cu metallization plane but below a passivation layer.

Abstract: An integrated fuse has regions of different doping located within a fuse neck. The integrated fuse includes a polysilicon layer and a silicide layer. The polysilicon layer includes first and second regions having different types of dopants. In one example, the first region has an N-type dopant and the second region has a P-type dopant. The polysilicon layer can also include a third region in between the first and second regions, which also has a different dopant. During a fusing event, a distribution of temperature peaks around the regions of different dopants. By locating regions of different dopants within the fuse neck, agglomeration of the silicide layer starts reliably within the fuse neck (for example, at or near the center of the fuse neck) and proceeds toward the contact regions. An improved post fuse resistance distribution and an increased minimum resistance value in the post fuse resistance distribution is realized compared to conventional polysilicon fuses.

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op

Abstract: Semiconductor diodes are diode connected vertical cylindrical field effect devices having one diode terminal as the common connection between a gate and a source/drain of the vertical cylindrical field effect devices. Methods of forming the diode connected vertical cylindrical field effect devices are disclosed.

Abstract: A memory array and some addressing circuitry therefor are formed by creating circuit elements at the crossing-points of two layers of electrode conductors that are separated by a layer of a semiconductor material. The circuit elements formed at the crossing-points function as data storage devices in the memory array, and function as connections for a permuted addressing scheme for addressing the elements in the array. In order to construct the addressing circuitry, the electrode conductors are fabricated with a controlled geometry at selected crossing-points such that selected circuit elements have increased or decreased cross-sectional area. By applying a programming electrical signal to the electrodes, the electrical characteristics (e.g. resistance) of selected circuit elements can be changed according to the controlled electrode geometry.

Abstract: A semiconductor device with a fuse box includes at least two gate electrodes 8, 9 and a fuse member 6. The two gate electrodes 8, 9 are formed on at least one insulating film 13 on a semiconductor substrate 100. The fuse member 6 is formed on the insulating film 13 on the semiconductor substrate 100. The two gate electrodes 8, 9 are electrically connected each other by the fuse member 6. In addition, the insulating film 13 and a field region 2 constituted by a semiconductor region are arranged adjacent to each other in a frame-like guard ring 1. The guard ring 1 is constituted by a semiconductor region formed on the semiconductor substrate 100.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.

Abstract: A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates that located on a substrate, numerous doped regions, numerous polysilicon layers, numerous cover dielectric layers, a conductor layer and numerous isolation dielectric layers.

Abstract: The present invention relates to a memory and an information apparatus and more specifically realizes a memory having large capacity through a simplified process and an information apparatus utilizing the same memory by generating the data cell region with a process that is different from the process used to generate the system region to control the data cells.

Abstract: In a memory cell array having sub-bit lines and sub-source lines formed of a diffusion layer, a main bit line is arranged commonly to the sub-bit lines arranged in multiple columns. A memory cell area can be reduced without restrictions by pitch conditions of the main bit lines.

Abstract: The present invention relates to a memory and an information apparatus and more specifically realizes a memory having large capacity through a simplified process and an information apparatus utilizing the same memory by generating the data cell region with a process that is different from the process used to generate the system region to control the data cells.

Abstract: There is described a semiconductor device having a copper fuse which prevents damage to a silicon substrate beneath the copper fuse, which would otherwise be caused by a laser beam radiated to blow the copper fuse. A light absorbing layer is formed on the copper fuse layer from material whose light absorption coefficient is greater than that of a copper wiring layer. Light absorbed by the light absorbing layer is transmitted, through heat conduction, to the copper wiring layer beneath the light absorbing layer and further to a barrier metal layer beneath the copper wiring layer. Even when the widely-used conventional laser beam of infrared wavelength is used, the copper fuse can be blown. Since a guard layer is formed below the fuse layer, there can be prevented damage to the silicon substrate, which would otherwise be caused by exposure to the laser beam of visible wavelength.

Abstract: A semiconductor memory array for improving packaging reliability and device speed is disclosed in the present invention. The semiconductor memory array includes a peripheral device region in a center portion of the array, a plurality of memory mat regions enclosing the peripheral device region, a pad region formed in the peripheral device region, a plurality of array control regions between the memory mat regions, each array control region horizontally adjacent to a memory mat region, and a plurality of main amplifier regions disposed between the memory mat regions and the peripheral device region.

Abstract: Mask ROM cell and method of fabricating the same, is disclosed, including a semiconductor substrate of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity type, formed in the semiconductor substrate in one direction, having a predetermined distance therebetween, an insulating layer formed on a portion of the semiconductor substrate, corresponding to each impurity diffusion region, a gate insulating layer formed on the semiconductor substrate, and a plurality of conductive lines formed on the gate insulating layer and insulating layer in a predetermined interval, being perpendicular to the impurity diffusion regions.

Abstract: A low noise, high frequency solid state diode is provided from a plurality of unit diode cells which are interconnected in parallel. Each of the unit diode cells forms an element of an array having rows and columns of unit diode cells. The diode cells include a base region of polysilicon, forming an anode, and an active cathode region which forms a diode junction with the anode. A plurality of overlapping subcollector regions interconnect the cathode regions, to provide a single, continuous collector for the diode arrays. The base region has a minimum perimeter to area ratio which reduces the resistance of each active diode region. A plurality of cathode contacts are connected to the subcollector through a respective reach region of highly doped semiconductor material. One or more metalization layers connect the cathode regions together, and the anodes of the base regions together. By controlling the size and shape of the base region of polysilicon, the series resistance of the resulting diode is minimized.

Abstract: The invention provides a zener zap diode having a high reliability and a method of manufacturing the same that can remove the problems accompanied with the zener zap trimming. In order to attain the object, the zener zap diode according to the invention is constructed such that, in an area adjacent to the surface of a semiconductor substrate, an active base region, an outer base region, and an emitter region are formed. Furthermore, a base lead electrode (one polysilicon layer) is formed to overlay the outer base region, and an emitter lead electrode (another polysilicon layer) is formed above the active base region. A contact between the one polysilicon layer and a metal interconnecting layer is disposed right above the outer base region. Since the insulation film that hinders the filament from being formed is not disposed under the one polysilicon layer, a filament is widely formed into an N-type well region when a PN junction is zapped by the zener zap trimming method.

Abstract: A manufacturing method and a structure for ROM component having a silicon controlled rectifier as the basic memory instead of a channel transistor in a conventional ROM, and using a formation of contact windows for coding a ROM instead of performing an ion implantation process. Also, since a silicon controlled rectifier occupies a smaller component surface area, the level of integration is correspondingly increased. Furthermore, due to interposition of an insulating layer between two bit lines, short circuiting between the adjacent bit lines is prevented. The component of this invention operates by applying a suitable voltage to the word line electrode and the bit line electrode respectively to select a particular memory unit, and as a result, a current will flow in a vertical direction through the memory unit, exit through the common electrode depending on the ON/OFF state of the memory, and be detected there.

Abstract: A read only memory device, which includes a P-type substrate, is provided. Several essentially parallel N-pole regions are located on the substrate. The N-pole regions extends in a first direction, and are separated from each other by a space. The N-pole regions form bit lines. Several N-type diffusion regions are located under selected portions of respective N-pole regions. Several P-type diffusion regions are located over respective selected portions of the N-pole regions. Each respective P-type diffusion region and associated N-pole region forms a diode. Several essentially parallel word lines extend in a second direction. Each word line is separated from an adjacent word line by a space. Each of the word lines is coupled to each of the corresponding P-type diffusion regions.

Abstract: The structure of a buried bit line. A substrate is provided and a trench is, formed within the substrate. Next, a trench insulating layer is located on a portion of the trench surface to expose a top corner of the trench. Then, a first conductive layer is fills the trench and forms a surface. Afterwards, a second conductive layer is formed on the surface and fills the trench, wherein the second conductive layer makes contact with the top corner, and a shallow junction region is located at the top corner and makes contact with the second conductive layer.

Abstract: A light emitting element module is provided including a board and plural chips arranged in the form of an array on the board. Each chip includes at least one light emitting element having a light emitting function and/or a photosensing function. The chips are arranged on the board so that the upper surfaces of adjacent chips which are located opposite to the board are positionally displaced in the height direction of the chips by at least the distance corresponding to the thickness of the chips. This uneven chip arrangement in the height direction may be established by alternately arranging thicker chips and thinner chips on the board.

Abstract: A laser diode package includes a laser diode, a heat sink and a lid. The laser diode has an emitting surface, a reflective surface opposing the emitting surface, and first and second surfaces between the emitting surface and the reflective surface. The laser diode has a diode height defined between the emitting surface and the reflective surface. The heat sink has an interior surface, an exterior surface opposing the interior surface, a top surface and a base surface. The height of the heat sink is defined between the top surface and the base surface and is approximately less than four times the laser diode height. The first surface of the diode is attached to the interior surface of the heat sink with a first solder. The base surface of the heat sink is coupled to a thermal reservoir. The lid is attached to the second surface of the laser diode via a second solder. An upper end of the lid is near the emitting surface of the laser diode.

Abstract: A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A ROM device of the type including an array of diode-type memory cells and a method for fabricating the same are provided. The bit lines of this ROM device are a plurality of diffusion regions formed in an alternate manner on the bottom of a plurality of parallel-spaced trenches and on the top of the solid portions between these trenches. This particular arrangement of the bit lines allows for an increased integration of the diode-type memory cells on a limited wafer surface without having to reduce the feature size of the semiconductor components of the ROM device. The diode-type memory cells that are set to a permanently-ON state involve a P-N junction diode being formed therein, wherein the P-N junction diode is electrically connected via a contact window in an insulating layer to the associated one of the overlaying word lines. Other memory cells that are set to a permanently-OFF state are formed with no P-N junction diode therein.

Abstract: A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut.

Abstract: A read-only memory device having a memory array composed of memory cells formed as P-N junction diodes when programmed to be in an ON state and as blocking capacitors when remaining in an OFF state. A number of insulators are placed on the surface of a P-type substrate isolated from each other and aligned along one first defined direction. Each of a number of N-type bit lines is located on the P-type substrate between every neighboring pair of insulators. Each of a number of switch control layers is located on a corresponding one of the N-type bit lines. Each of a number of P-type word lines is located on the insulators along a direction that is substantially perpendicular to the first direction. A punch-through voltage is applied through the switch control layers at selected memory cell locations, thereby programming the memory cell at such locations to be in an ON state. All other memory cells locations keep their switch control layers intact and are thereby programmed to be in an OFF state.

Abstract: A method for fabricating read only memory, (ROM), devices, has been developed. The programmable cell of this ROM device is comprised of a P/N diode, place in a N+ buried bit line. The diode formation is accomplished using outdiffusion from a P+ polysilicon wordline, that is in direct contact to a specific bit line region.

Abstract: A substantial portion of the material at the pn junction (27) of the photodiode (37, 41) having an implanted region extending to a surface thereof is selectively removed (39), leaving a very small junction region (35, 43) with the remainder of the p-type (23) and n-type (25) material of each photodiode being spaced apart or electrically isolated at what was originally the junction. In the ion implanted n-type on p-type approach, the majority of the signal is created in the implanted n-type region while the majority of the noise is generated in the p-type region. By selectively removing p-type material, n-type material or both from the pn junction of the diode or otherwise electrically isolating most of the p-type and n-type regions from each other at the pn junction and thereby minimizing the pn junction area, noise is greatly reduced without affecting the signal response of the photodiode.

Abstract: A programmable semiconductor memory with filament or point diodes in the intersections of a matrix system can be manufactured with minimum dimensions and thus with a very high density owing to the absence of alignment tolerances. A possible problem is then posed by the strong leakage currents which may arise during programming owing to punch-through between adjoining diodes. Decreasing the leakage current through the use of a higher background concentration of the region in which these diodes are formed is not possible because this reduces the breakdown voltage of the pn junctions of the diodes too much. According to the invention, a more strongly doped surface zone is provided in the region between the diodes, which zone is situated at least at a distance from the diode points. In a specific embodiment, the zone extends less deeply into the region than do the diodes.

Abstract: A semiconductor device includes a programmable element having a doped semiconductor region (4) and a conductor region (6) which are separated from one another by at least a portion of an insulating layer (5). The conductor region (6) is of a material suitable for forming a rectifying junction (8) with the material of the semiconductor region (4). To achieve a comparatively high conductivity connection to the semiconductor region (4), the element is further provided with a contact region (3) which has a comparatively low electrical resistance compared with the semiconductor region (4). The contact region (3) is provided at a side of the semiconductor region (4) remote from the insulating layer (5) and is separated from the insulating layer (5) by the semiconductor region (4). Both the semiconductor region (4) and the contact region (5) are laterally bounded by an isolating region (7) at opposing sides.

Abstract: A memory is formed from an array of switchless integrated circuit memory cells in a high-density configuration. These cells comprise a capacitor and two diodes in a configuration where one diode is used to charge one pole of the capacitor, and the other diode is used to discharge it from that same pole, over separate paired lines used respectively for charging and discharging, as well as reading. The other pole of the capacitor is tied to a single line used for both charging and discharging, and in support of reading. Drive and sense circuitry located at the periphery of the cell array is used to perform interconnect switching functions while writing or reading charges on cells in the array. Alternative high-density switched cell variations are also described. The cell arrays are fabricated on monolithic integrated circuits which are interconnected with one another by using a method which deposits and etches conductive material which links conductive traces between the monolithic dice.

Abstract: A dual gate field effect transistor including first and second gates comprises a conductive region, wherein a potential difference between a second gate electrode section and the conductive region is larger than that between the second gate electrode section and a channel operation region.

Abstract: A semiconductor device includes a number of programmable elements arranged in a matrix of rows and columns. The elements each have a doped semiconductor region (10) and a conductor region (20) which are mutually separated by an insulating layer (8). The conductor region (20) can be a material suitable for forming a rectifying junction (35) with the material of the semiconductor region (10). Within a row, the conductor regions of the programmable elements present therein are coupled to a common row conductor (21 . . . 23), and within a column the semiconductor regions of the programmable elements situated therein are connected to a common column conductor (11 . . . 14). To program an element, a programming voltage V.sub.

Abstract: A semiconductor memory device having a trench-type capacitor configuration is provided. The device comprises an element isolation insulating film formed on the surface of the substrate in the vicinity of the trenches. The insulating film includes a thickness-reducing region to which the inclined end portion of the capacitor electrode is connected.

Abstract: A plurality of strip shaped first polysilicon layers 3 are formed on a monocrystalline silicon substrate 1, a plurality of strip shaped second polysilicon layers 5 are formed thereon crossing the first polysilicon layers 3, and a plurality of strip shaped third polysilicon layers 8 are further formed thereon crossing the second polysilicon layers 5. The first and second polysilicon layers 3 and 5 are laser-annealed and monocrystallined. Contact holes 4 and 7 are selectively formed at the crossing points of the first polysilicon layers 3 and the second polysilicon layers 5, and the crossing points of the second polysilicon layers 5 and the third polysilicon layers 8. A PN junction is formed on each surface layer of the first polysilicon layers 3 and the second polysilicon layers 5 in the portions corresponding to these contact holes 4 and 7. Two layers of memory cell arrays using diode elements as memory cells are piled upon each other.

Abstract: A memory cell array (50) of a DRAM has a so-called divided bit line structure including two regions (50a and 50) divided from each other. One bit line (24) of a bit line pair is connected to a predetermined memory cell in a first memory cell array block (50a) and is kept in unloaded state in a second memory cell array block (50b). The other bit line (25) of a bit line pair is kept in unloaded state in the first memory cell array block (50a) and is connected to a predetermined memory cell in a first memory cell array block (50b). In these structures, the load state is kept same in both bit lines of the bit line pair. In the memory cell array, four memory cells are disposed in a cross-relationship, and are connected to the bit line (24) through a contact portion (17) used in common by the four memory cells. The word lines (20a and 20b) are formed to obliquely cross the bit lines and to extend perpendicularly to each other. Capacitors (3) in the memory cells have portions extended over the word lines.

Abstract: A method for producing a mask ROM having an array of memory cells in which pn junctions obtained by introducing P-type impurities by ion implantation onto the surface of an N-type electrically conductive layers obtained in turn by introducing N-type impurities into the polysilicon layers are formed as memory cells in a matrix configuration. The polysilicon layers that are to be rendered into the N-type electrically conductive layers are previously monocrystallized by laser annealing. In this manner, the N-type electrically conductive layers into which P-type impurities are introduced by ion implantation at the time of formation of the pn junction are turned into a monocrystalline layer so that the surface of the N-type electrically conductive layers may be uniformly and easily converted into the P-type by this ion implantation. In short, the junction surface of the pn junction used as the memory cell becomes uniform.