Abstract: The present invention provides a 3D integrated circuit and a manufacturing method thereof. The circuit structure comprises: a semiconductor substrate; at least one semiconductor device formed on the upper surface of the semiconductor substrate; a through-Si-via through the semiconductor substrate and comprising an insulating layer covering sidewalls of the through-Si-via and conductive material filled in the insulating layer; an interconnection structure connecting the at least one semiconductor device and the through-Si-via; and a diffusion trapping region formed on the lower surface of the semiconductor substrate. The present invention is applicable in manufacture of the 3D integrated circuit.

Abstract: A thin film transistor includes a substrate, a semiconductor layer provided on the substrate and crystallized by using a metal catalyst, a gate electrode insulated from and disposed on the semiconductor layer, and a getter layer disposed between the semiconductor layer and the gate electrode and formed with a metal oxide having a diffusion coefficient that is less than that of the metal catalyst in the semiconductor layer.

Abstract: An internal gettering process for a Czochralski silicon wafers comprises: (1) heating a Cz silicon wafer to 1200-1250° C. at a heating rate of 50-100° C./s under a nitrogen atmosphere, maintaining for 30-150 seconds, cooling the Cz silicon wafer to 800-1000° C. first at a cooling rate of 5-50° C./s, and then cooling the Cz silicon wafer naturally; (2) annealing the Cz silicon wafer obtained in the step (1) at 800-900° C. under an argon atmosphere for a period of 8-16 hours. The present invention only involves two heat treatment steps which require lower temperature and shorter time comparing to the conventional processes. The density of the bulk microdefects and the width of the denuded zone can be easily controlled by the temperature, duration and cooling rate of rapid thermal processing in the first step.

Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.

Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.

Abstract: A solid-state imaging device includes: a photoelectric conversion portion that receives an incident light from a back surface side of a silicon layer to perform photoelectric conversion on the incident light; and a pixel transistor portion that outputs signal charges generated in the photoelectric conversion portion towards a front surface side of the silicon layer, wherein a gettering layer having internal stress is provided on the front surface side of the silicon layer at a position to overlap the photoelectric conversion portion on a plan view layout thereof.

Abstract: A method for removing impurities from at least one semiconductor device layer during manufacturing of a semiconductor device is disclosed. The semiconductor device layer has a compound semiconductor material and/or germanium. Each heating process performed during the manufacturing of the semiconductor device after provision of the semiconductor device layer has a low thermal budget determined by temperatures equal to or lower than about 900° C. and time periods equal to or lower than about 5 minutes. In one aspect, the method includes providing a germanium gettering layer with a higher solubility for the impurities than the semiconductor device layer. The germanium gettering layer is provided at least partly in direct or indirect contact with the at least one semiconductor device layer, such that impurities can diffuse from the at least one semiconductor device layer to the germanium gettering layer.

Abstract: Metal impurities of an upgraded metallurgical grade (UMG) silicon (Si) wafer are reduced. The UMG Si wafer having a 5N (99.999%) purity is chosen to grow a high-quality epitaxial Si thin film through atmospheric pressure chemical vapor deposition (APCVD). Through heat treating diffusion, the epitaxial Si film is used to form sink positions for the metal impurities in the UMG Si wafer. By using concentration gradient, temperature gradient and interface defect, individual and comprehensive effects are built for enhancing purity of the UMG Si wafer from 5N to 6N. Thus, a low-cost Si wafer can be fabricated for Si-based solar cell through a simple, fast and effective method.

Abstract: Phosphorus is implanted into a crystalline semiconductor film by an ion dope method. However, a concentration of phosphorus required for gettering is 1×1020/cm3 or higher which hinders recrystallization by later anneal, and thus this becomes a problem. Also, when phosphorus is added at a high concentration, processing time required for doping is increased and throughput in a doping step is reduced, and thus this becomes a problem. The present invention is characterized in that impurity regions to which an element belonging to the group 18 of the periodic table is added are formed in a semiconductor film having a crystalline structure and gettering for segregating in the impurity regions a metal element contained in the semiconductor film is performed by heat treatment. Also, a one conductivity type impurity may be contained in the impurity regions.

Abstract: An encapsulated device includes a micro device on a substrate, a cover bonded to the substrate thereby forming a chamber to encapsulate the micro device, and a desiccant material on the cover and in the chamber. An anti-stiction material is absorbed in the desiccant material.

Abstract: A semiconductor device has an IC chip with a thickness of equal to or less than 100 ?m and includes a semiconductor substrate. A device forming region is within the depth of approximately equal to or less than 5 ?m from a surface of the semiconductor substrate, and a total thickness of the semiconductor substrate is from 5 ?m to 100 ?m. A BMD layer for carrying out gettering of metal impurities is provided immediately under the device forming region. Since a gettering site is provided immediately under the device forming region, in a device or the like of which extreme thinness is required, degradation of device characteristics and reliability due to contamination of metal impurities can be prevented, and stabilize and improve the device yield.

Abstract: One aspect of this disclosure relates to a semiconductor structure, comprising a gettering region proximate to a device region in a semiconductor wafer. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids through a surface transformation process. Each of the voids has an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region. The structure includes a transistor formed using the device region. The transistor includes a gate dielectric over the device region, a gate over the gate dielectric, and a first diffusion region and a second diffusion region formed in the device region. The first and second diffusion regions are separated by a channel region formed in the device region between the gate and the proximity gettering region.

Abstract: A solid-state imaging device capable of reducing the occurrence of a dark current and a pixel defect is provided. A solid-state imaging device 10 is formed in which a plurality of photoelectric conversion elements 4 are formed in a semiconductor substrate 1; circuits 5 which read out signal charge from each of the plurality of photoelectric conversion elements 4 are respectively formed on the semiconductor substrate 1; light is applied from the opposite side to the circuits 5 which read out signal charge from each of the plurality of photoelectric conversion elements; and a gettering region is provided in an element-isolation area 2 which separate the photoelectric conversion elements 4 adjacent to each other.

Abstract: A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.

Abstract: A bilayer dielectric structure for substantially reducing or eliminating metal contaminants formed during subsequent polysilicon deposition is provided. The bilayer dielectric structure includes an upper surface region that is rich in chlorine located atop a bottom surface region. The upper surface region that is rich in chlorine removes metal contaminates that are present atop the structure during subsequent formation of a polysilicon layer. A method of forming the bilayer structure is also provided.

Abstract: An electronic power device comprising a single crystal silicon segment being characterized in that the segment comprises a non-uniform distribution of minority carrier recombination centers, the minority carrier recombination centers comprising a substitutional metal, with the concentration of the centers in a bulk layer being greater than the concentration in a surface layer. The centers have a concentration profile in which the peak density of the centers is at or near the central plane with the concentration generally decreasing from the position of peak density in the direction of the front surface of the segment and generally decreasing from the position of peak density in the direction of the back surface of the segment.

Abstract: The TFT electric characteristic is ready to be influenced by the channel region in the neighborhood of an interface between a semiconductor and a gate insulating film. The present invention provides TFTs reduced in electric characteristic deviations and a method for manufacturing the same. The invention forms a region or layer containing an inactive element, or rear gas element, in the channel region. As shown in FIG. 1, a rear gas element is contained at least in an upper layer of the channel region.

Abstract: On a silicon layer of an SOI wafer is defined a semiconductor device-forming region to form semiconductor devices thereon and an insulating region to electrically insulate the semiconductor device-forming region. Then, a mask layer is formed of nitride by means of photolithography so as to cover the semiconductor device-forming region. Then, an impurities-removing layer is formed by means of well known technique so as to cover the mask layer and embed the gaps between the adjacent masks of the mask layer. The impurities of the silicon layer of the SOI wafer are absorbed and removed by the distorted layer, the grain boundaries and the lattice defects of the impurities-removing layer.

Abstract: The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wherein the floating gate (230) has a metal control gate (250) located thereover. The semiconductor device (200), in the same embodiment, further includes a dielectric layer (240) located between the floating gate 230 and the metal control gate (250), the dielectric layer (240) having a gettering material located therein.

Abstract: Organic electronic device structures are provided, which comprise: (a) a first portion comprising a substrate and an organic electronic device region (e.g., an OLED region) disposed over the substrate; (b) a second portion comprising a cover and a getter region; and (c) a radiation-curable, pressure-sensitive adhesive layer disposed between the first and second portions and adhering the first and second portions to one another. The adhesive layer is disposed over the entire organic electronic device region and over at least a portion of the substrate. Other aspects of the present invention are directed to methods of making the above structures.

Abstract: An electronic control device includes a power supply circuit, electronic circuits, a ground wiring pattern, and a common ground wiring pattern formed in a multi-layered substrate. The ground wiring pattern is dedicated for the power supply circuit and the common ground wiring pattern is provided for all electronic circuits. Even when an electrical potential of the ground wiring pattern varies due to a switching operation of a switching component included in the power supply circuit, the common ground wiring pattern is not affected.

Abstract: In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source regions are formed on the p-well regions, respectively. A gate electrode is formed through a gate insulation film on a part of each p-well region and that of each n+ source region. The gate electrode is covered with an insulation film. On the insulation film, a source electrode is formed so that the n-channel MOSFET includes body diodes BD imbedded therein. A drain electrode is formed on the single crystal semiconductor substrate. A cluster-containing layer is implanted in the single crystal semiconductor substrate as a gettering layer so that the cluster-containing layer contains a cluster of nitrogen.

Abstract: Disclosed is a terminal structure of a multi-layer substrate and a method for forming the same. In the terminal structure, a plurality of terminals are formed on at least two adjacent substrate layers, each of the terminals being spaced from adjacent ones to a predetermined interval. Openings are formed in at least one of the substrate layers. Each of the openings is formed between each adjacent ones of first terminals in the at least one substrate layer, and spaced from the each first terminals to a predetermined gap, and has a size same as that of the first terminals. The substrate layers are stacked one atop another and compressed together so that second terminals formed on at least one corresponding substrate layer are projected to a plane of an outermost substrate layer on which corresponding terminals are formed. The terminal structure and the method can secure a predetermined interval to a plurality of terminals in a package when the terminals are formed as well as simplify formation thereof.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: The present invention provides an epitaxial wafer wherein a silicon epitaxial layer is formed on a surface of a silicon single crystal wafer in which nitrogen is doped, and a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk is 108 numbers/cm3 or more. And the present invention also provides a method for producing an epitaxial wafer wherein a silicon single crystal in which nitrogen is doped is pulled by Czochralski method, the silicon single crystal is processed into a wafer to produce a silicon single crystal wafer, and the silicon single crystal wafer is subjected to heat treatment so that a density of oxide precipitates having such a size that a gettering capability can be achieved in a bulk of the wafer may be 108 numbers/cm3 or more, and then the silicon single crystal wafer is subjected to epitaxial growth. A silicon single crystal wafer which surely has a high gettering capability irrespective of a device process can be obtained herewith.

Abstract: An electronic control device includes a power supply circuit, electronic circuits, a ground wiring pattern, and a common ground wiring pattern formed in a multi-layered substrate. The ground wiring pattern is dedicated for the power supply circuit and the common ground wiring pattern is provided for all electronic circuits. Even when an electrical potential of the ground wiring pattern varies due to a switching operation of a switching component included in the power supply circuit, the common ground wiring pattern is not affected.

Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.

Abstract: A method of fabricating electronic devices, integrated monolithically in a semiconductor substrate having at least one non-active area contiguous with at least one device active area, which method comprises at least one step of implanting ions of a noble gas, followed by a thermal treatment to form getter microcavities in the semiconductor by evaporation of the noble gas, wherein the implanting step is carried out in the non-active area of the semiconductor.

Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.

Abstract: To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.

Abstract: An SOI semiconductor device includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.

Abstract: A method for producing a multi-layer, micro-mechanical device. The device comprises an internal cavity having a micro-mechanical component therein. The method comprises the steps of forming the micro-mechanical component from a layer of first material, providing a sealing layer on at least one surface of the first material to define the cavity, providing a getter material within the cavity, sealing the first material to the sealing layers by anodic bonding, supplying an inert gas to the cavity to regulate the pressure inside the cavity. A corresponding device produced by the method is also disclosed.

Abstract: There is provided a method of fabricating a silicon-on-insulator substrate, including the steps of (a) forming a silicon substrate at a surface thereof with an oxygen-containing region containing oxygen at such a concentration that oxygen is not precipitated in the oxygen-containing region in later mentioned heat treatment, (b) forming a silicon oxide film at a surface of the silicon substrate, (c) implanting hydrogen ions into the silicon substrate through the silicon oxide film, (d) overlapping the silicon substrate and a support substrate each other so that the silicon oxide film makes contact with the support substrate, and (e) applying heat treatment to the thus overlapped silicon substrate and support substrate to thereby separate the silicon substrate into two pieces at a region into which the hydrogen ions have been implanted, one of the two pieces remaining on the silicon oxide film as a silicon-on-insulator active layer.

Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: An SOI wafer has a set of gettering sites formed in the device layer, optionally extending through the buried insulator; the gettering sites being formed within the source/drain regions of transistors.

Abstract: An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a withstanding voltage between a semiconductor substrate and the buffer layer is lower than the withstand voltage of the pn junction at the edge of the diced cross-section. Therefore, the whole pn junction between the semiconductor substrate and the buffer layer, which has wide area, breaks down, as a result, energy caused by a negative voltage is absorbed, and the withstanding voltage against the negative voltage is improved.

Abstract: A multi-layered metal bond pad for a semiconductor die having a conductive metal layer and an overlying ruthenium electrode layer. The ruthenium electrode layer protects the conductive metal from oxidation due to ambient environmental conditions. An interconnect structure such as a wire bond or solder ball may be attached to the ruthenium layer to connect the semiconductor die to a lead frame or circuit support structure. Also disclosed are processes for forming the ruthenium layer.

Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.

Abstract: The present invention provides an SOI device preventing the floating body effect, and a method for manufacturing the same. Disclosed is a method comprising the steps of: forming an isolation layer on a first silicon substrate; forming a conductive layer on the isolation layer and the first silicon substrate; forming a buried insulating layer on the conductive layer; bonding the second silicon substrate so as to contact with the buried insulating layer; exposing the isolation layer by removing backside of the first silicon substrate by selected thickness thereby defining a semiconductor layer; forming a transistor by forming a gate electrode, a source region and a drain region at selected portions of the semiconductor layer; etching a selected portion of the isolation layer so as to expose the conductive layer; and forming a body electrode to be contacted with the conductive layer within the isolation layer.

Abstract: A semiconductor substrate is provided which maintains its gettering capabilities throughout the manufacturing process of a semiconductor device and which prevents previously gettered contaminating impurities from being released again into an operating region of a semiconductor device. The semiconductor substrate includes a silicon substrate, a polysilicon layer, and a high density boron layer. The silicon substrate has a first main surface and a second main surface opposed to the first main surface, and the silicon substrate is used to form a semiconductor device at least indirectly on the first main surface. The polysilicon film is formed at least indirectly on the second main surface, and the high density boron layer is disposed between the silicon substrate and the polysilicon film. Also a ratio of a highest boron density value in the high density boron layer to a lowest boron density value in the silicon substrate is greater than or equal to approximately 100.

Abstract: This invention is directed to a novel a single crystal silicon wafer. The wafer comprises: (a) two major generally parallel surfaces (ie., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance of at least about 10 &mgr;m from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer.

Abstract: A semiconductor device is provided which is capable of removing the heavy metal impurity in a SOI layer by gettering, and realizing an improvement in breakdown voltage and reliability. The semiconductor device comprises polysilicon regions functioning as a gettering site, which are selectively formed in a buried fashion, such as to make no contact with a gate insulating film and an element isolation insulating film, in a main surface of part of a SOI layer where a drain region and a source region are disposed; and contact holes being filled with polysilicon plug functioning as a gettering site, and extending through an interlayer insulating film between an upper surface of the interlayer insulating film and an upper surface of the polysilicon regions.

Abstract: A boron nitride inclusion sheet is applied on the surface of a mold package enclosing a semiconductor chip so as to prevent soft error caused by a thermal neutron.

Abstract: A semiconductor device and a semiconductor storage device having an SOI structure and being enable sufficient gettering performance without imposing limitations on the freedom of design of an LSI circuit. A semiconductor device includes a semiconductor wafer of SOI structure which has a insulation layer and a silicon layer provided thereon, wherein the semiconductor wafer includes a plurality of element fabrication regions where semiconductor elements are fabricated, and a cutting region provided between the element fabrication regions. Gettering sites are formed in the cutting region by means of embedding a gettering member into grooves of predetermined depth.

Abstract: The present invention relates to a silicon on insulator (“SOI”) structure having a low defect density device layer and, optionally, a handle wafer having improved gettering capabilities. The device layer comprises a central axis, a circumferential edge, a radius extending from the central axis to the circumferential edge, and a first axially symmetric region which is substantially free of agglomerated intrinsic point defects. Additionally, the present invention is directed to such a SOI structure which has a Czochralski single crystal silicon handle wafer which is capable of forming an ideal, non-uniform depth distribution of oxygen precipitates upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process.

Abstract: Disclosed is a simplified technique of introducing a metal element capable of promoting the crystallization of silicon into an amorphous silicon film to be crystallized, and of removing the metal element from the film. An amorphous silicon film 102 is formed on a substrate, a mask 103 is formed thereon, and a nickel-containing PSG film is further formed thereover. This is heated at 560° C. to thereby make nickel diffused in the direction 106, and the film is crystallized. Next, this is further heated at 850° C. to thereby make phosphorus diffused into the region 107, in which nickel is gettered by the thus-diffused phosphorus. Thus, the crystallization of silicon is promoted by the metal element nickel, and the nickel is then removed from the crystallized silicon film.

Abstract: The semiconductor device includes a semiconductor base body (11) formed of a damaged layer (102) serving as a gettering layer, a P+ collector layer (103), an N+ buffer layer (104), and an N− layer (105) laid one on top of another, a gate electrode (27) selectively formed on the upper main surface of the semiconductor base body (11) specifically on the external main surface of the N− layer (105), with a gate insulating film (26) interposed therebetween, an emitter electrode (28) selectively formed on the upper main surface of the semiconductor base body (11), and a collector electrode (106) formed on the lower main surface of the semiconductor base body (11), specifically on the external main surface of the damaged layer (102).

Abstract: A semiconductor substrate is provided which can efficiently exhibit intrinsic gettering (IG) effect, is less likely to cause slipping or dislocation, and causes no significant lowering in mechanical strength. The semiconductor substrate has bulk micro defects dispersed at a density of not less than 1011 micro defects/cm3 in the interior thereof.

Abstract: To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.