Abstract: According to one embodiment, a nonvolatile memory device includes a stacked body including a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer. The recording layer is capable of reversibly changing between a first state and a second state having a resistance higher than a resistance in the first state by a current supplied via the first layer and the second layer. The recording layer includes a first portion and a second portion provided in a plane of a major surface of the recording layer. The second portion has a nitrogen amount higher than a nitrogen amount in the first portion.

Abstract: Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate layer situated over the first gate layer. The contact line includes a height that is less than a combined height of the first gate layer and the subsequent gate layer(s). The MOSFET circuits further include gate spacers situated proximate the gate layers and a single contact line spacer situated proximate the contact line. The gate spacers are taller and thicker than the contact line spacer.

Abstract: A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.

Abstract: Embodiments include a driver circuit that is suitable to prevent a delay in responding to an input of a drive signal and a method for manufacturing the same. Three contact holes are provided for each of the transistors Tr1-Tr4 for connecting the gate electrodes of the transistors to the signal lines Ls, Ls1-Ls4 that are separated from the transistors Tr1-Tr4 by the dielectric layer 14. As a result, the time for an input signal to reach the entire area of the gate electrodes becomes shorter and a response to an input of a drive signal becomes faster.

Abstract: A display panel comprises the following elements. A pixel array arranged by a plurality of pixel devices is applied for producing images according to input signals. A plurality of COG chips are fabricated on a peripheral region of the display panel and connected in series wherein the COG chips can convey the input signals to the pixel array for driving selected the pixel devices. A plurality of WOA lines are defined on the display panel for connecting the COG chips in series to transfer the input signals. And a first bypassing bus is fabricated aside the COG chips and connected separately to two different WOA lines for connecting with at least one the COG chip in parallel so as to bypass the input signals.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: Each connecting pad includes a continuous top metal layer on the top metallization level and having on its top face an area for welding a connecting wire. Also, the pad has a reinforcing structure under the welding area and includes at least one discontinuous metal layer on the immediately next lower metallization level, metal vias connecting the discontinuous metal layer to the bottom surface of the top metal layer, and an isolating cover covering the discontinuous metal layer and its discontinuities as well as the inter-via spaces between the two metallic layers.

Abstract: A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.

Abstract: In a semiconductor device in which an interlayer insulating layer is formed of a low density material (porous silica etc.) and a hole or a trench is formed in the interlayer insulating layer by processing the interlayer insulating layer and an electrically conductive material is coated on the processed surface of the hole or trench for establishing electrical connection, the density of part of the interlayer insulating layer near the processed surface of the hole or trench is increased in comparison with other parts of the interlayer insulating layer. The densification process is conducted by the elimination of microvoids near the processed surface, for example. The densification or the microvoid elimination can be conducted by use of ammonia water, vapor of ammonia water, ammonia plasma treatment, etc. By the densification process, coating of the electrically conductive material (Cu etc.

Abstract: A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.

Abstract: A multiple layer mesh design that provides that a bridge associated with a second layer connects a rail on a first layer to a trunk on a fourth layer. If the trunk on the third layer shadows a plurality of rails on the first layer, preferably the bridge is at least as wide as a sum of the widths of the rails on the first layer which are shadowed by the trunk on the third layer. If the trunk on the third layer shadows a single rail on the first layer, preferably the bridge is at least as wide as twice the width of the rail on the first layer.

Abstract: A method for fabricating an integrated circuit device includes the steps of forming first and second conductive regions on a substrate. The second conductive region is divided into first and second subregions wherein the first subregion is adjacent the first conductive region. More particularly, the surface area of the first subregion is not more than ten times greater than the surface area of the first conductive region. The first and second subregions can then be electrically connected to complete the second conductive region. Related structures are also discussed.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: The multilayer electronic device comprises a dielectric body formed by stacking dielectric layers. Flat first internal electrodes and flat second internal electrodes insulated via dielectric layers and arranged facing to the first internal electrodes are alternately stacked. First through-hole electrodes are connected to the first internal electrodes by penetrating, penetrate the second internal electrodes without connecting thereto and extend crossing the internal electrodes. The second through-hole electrodes are connected to the second internal electrodes by penetrating, penetrate the first internal electrodes without connecting thereto and extend crossing the internal electrodes. The first terminal electrodes are arranged on the outer surface of the dielectric body and connected to the first through-hole electrodes.

Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate; a signal wire, disposed on the semiconductor substrate, for transmitting a signal between circuits; and a dummy wire disposed between the signal wire and the region of the semiconductor substrate to form a parasitic capacitance with the signal wire, wherein a signal, which has the same phase as a phase of a signal supplied to the signal wire, is supplied to the dummy wire.

Abstract: The present invention aims at improving the lifetime of the wiring connecting to the hole nearest to the bonding pad and thereby improving the reliability of the semiconductor device. The invention relates to such semiconductor device and method of manufacturing the semiconductor device. The semiconductor device includes a plurality of first metal layers connected to a bonding pad, and plurality of aluminum wirings respectively connected to the first metal layers. The plurality of aluminum wirings are connected to a single second metal layer and have a length equal to or short than Blech Length.

Abstract: A semiconductor device includes a lead frame, a semiconductor chip, a resin-encapsulated portion, and tie bars. The semiconductor chip is mounted on a die pad of the lead frame. The resin-encapsulated portion resin-encapsulates the semiconductor chip. The tie bars are provided to outer lead portions of the lead frame to prevent resin leakage during resin encapsulation, and are cut and removed in a finishing step of resin encapsulation. A plating surface is formed on a sectional surface of each of the tie bars. A semiconductor device manufacturing method and apparatus are also disclosed.

Abstract: A thin-film laminate type conductor is provided which includes a first conductor that is a metal thin film formed of Al or Al alloy, and a second conductor that is a transparent conductive thin film formed of a metal oxide. The first and second conductors are formed in respective patterns on a transparent substrate, such that at least a part of the second conductor is laminated on at least a part of the first conductor. The transparent conductive thin film is composed of an amorphous film. In another embodiment, the first conductor is composed of laminated metal thin films one of which is formed of Al or Al alloy, and the other of which is formed of a high-melting-point metal. The Al or Al-alloy film is sandwiched between the substrate and the high-melting-point metal film.

Abstract: A capacitor structure (100) including first and second capacitor plates (102, 106) insulatingly spaced from each other by a capacitor dielectric (102). A first set of conductive posts (301) electrically couple to the first capacitor plate (102) and extend away from the capacitor dielectric (104). A first conductive structure (302) comprising a material with lower resistivity than the first capacitor plate (102) is electrically coupled to the first set of conductive posts (301). In a preferred embodiment, a second set of conductive posts (501) are electrically coupled to the second capacitor plate (106) and extend away from the capacitor dielectric (102). A second conductive structure (503) is electrically coupled to the second set of conductive posts (501).

Abstract: There is provided an EEPROM semiconductor device including (a) a plurality of field insulating films each extending perpendicularly to word lines, (b) a plurality of memory cells arranged in a matrix, each memory cell having a floating gate, a control gate formed on the floating gate and doubling as a word line, and source and drain regions located at either sides of the control gate, (c) a common source line extending in parallel with the word lines and connecting source regions of the memory cells with each other, and (d) a first bit line extending perpendicularly to the word lines and connecting drain regions of the memory cells with each other. The above-mentioned EEPROM semiconductor device makes it possible to form CMOS logic circuit together with a non-volatile memory on a common semiconductor substrate without increasing fabrication steps, and also makes it possible for the non-volatile memory to write data thereinto and read data therefrom at a higher rate without an increase in a cell size.

Abstract: A semiconductor integrated circuit includes a gate extending in a first direction, a diffusion-layer region corresponding to the gate, and a plurality of backing wiring lines connected to the diffusion-layer region and extending in a first wiring layer in a second direction substantially perpendicular to the first direction. The semiconductor integrated circuit further includes connection wiring lines providing connections between the plurality of backing wiring lines and provided in a second wiring layer.

Abstract: An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns.

Abstract: A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.

Abstract: Capacitor arrays may be incorporated within silicon integrated circuits as part of analog-to-digital or digital-to-analog converters. Capacitance ratios between individual capacitors need to be controlled to better than 1%. Because of microloading effects during etching, the areas of the electrodes of the capacitors located along the edges of the array have tended to be slightly less than the areas of electrodes located completely inside the array. The present invention solves this problem by providing additional electrodes located along the periphery of the array, spaced the same distance away from the array edge as the spacing between electrodes inside the array.

Abstract: The gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting together the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer. Alternately, the gate resistance is reduced by utilizing a metal line that shorts all of the gate contacts together, and overlies each of the gates. By reducing the gate resistance, the maximum frequency f.sub.MAX of the multi-finger transistor can be increased.

Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36, 38) is disposed between two of the fingers (16,18,20) for dividing current flow.

Abstract: A high frequency bypass capacitor (36, 36') is built into a thin-film portion (16, 16') of a polymer carrier substrate (15) of a PBGA (10). The carrier substrate (15) has both a stiffener (18) and a thin-film portion (16, 16') which has multiple metal layers (24, 28, 30, 32). The power supply planes (28, 30) of these metal layers are used to form built-in bypass capacitors (36, 36'), wherein the power supply planes are specifically designed to be adjacent and parallel layers. An ultra thin film laminate construction provides thin dielectric films (26) between the metal layers to allow the bypass capacitor to be placed very dose to the attached semiconductor die (12) to further reduce parasitic inductance and resistance between die connections (14) and the bypass capacitor. The built-in feature minimizes inherent parasitic series inductance and resistance, thus enabling the filtering of unwanted low pulse width glitches on a power plane connected to VLSI devices at operating frequencies at or above 100 MHz.

Abstract: This invention relates to MOS transistors and a method for fabricating the MOS transistors having LDD (Lightly Doped Drain) structures, which comprises a first conduction type semiconductor substrate, a second conduction type high density source and drain regions formed spaced from each other in the first conduction type semiconductor substrate, a second conduction type low density impurity region formed on sides facing each other of, and adjacent to the second conduction type high density source and drain regions, a first gate insulation film formed on both ends of a upper part of the semiconductor substrate region between the second conduction type low density impurity region, a second gate insulation film formed on upper part of the semiconductor substrate region between the first gate insulation films, a first conduction layer in a form of side wall spacer formed on the first gate insulation film, a second conduction layer formed on the second gate insulation film, a third conduction layer formed on the f

Abstract: In a semiconductor apparatus, a first circuit provided on a major surface of a semiconductor substrate. The first circuit includes a plurality of logic circuits of an identical structure, the logic circuits having input terminals supplied with identical signals. First metal wiring is provided on the semiconductor substrate in a direction identical to a direction of arrangement of the logic circuits, the first metal wiring being connected to one of the input terminals of each of the logic circuits. A second circuit provided on the major surface of the semiconductor substrate in an outside area which does not overlap an area extending in a direction perpendicular to the direction of arrangement of the logic circuits, the second circuit supplying an identical signal to the input terminals of the logic circuits of the first circuit. A second metal wiring is connected between an output terminal of the second circuit and a substantially middle point of the first metal wiring.

Abstract: There is disclosed an LCD element which prevents delamination of a main data line and a redundancy line caused by the stress therebetween and breaking of the data line. It comprises a partially patterned redundancy line which reinforces a data line to prevent wire-breaking of the data line. According to the reinforcement, the stress is reduced, which leads to increasing adhesion between an ITO transparent electrode and the source-drain electrode. The advantages are accomplished by patterning the main data line and the redundancy line in part, forming the ITO and the source electrode in a variety of patterns or changing the lamination order therebetween.

Abstract: A feature in a thin-film structure such as an AMLCD array has an edge with a tapered sidewall profile, reducing step coverage problems. The feature can be produced by producing a layer in which local etch rates vary in the thickness direction of the layer. The layer can then be etched to produce the feature with the tapered sidewall profile. The layer can be produced by physical vapor deposition. The layer can, for example, includes sublayers with different etch rates, either due to different atomic proportions of constituents or due to different etchants. Or local etch rates can vary continuously as a result of changing deposition conditions. Differences in etch rates or differences in etchant mixtures can be used to obtain a desired angle of elevation.

Abstract: At a peripheral area of a semiconductor chip where active elements are not formed, a layer underlying a power supply wiring or ground wiring is provided with an uneven surface. The uneven or corrugated surface at the interface between the wiring and the underlying layer makes the wiring unsusceptible to slide. The uneven surface can be realized by interposing foreign matters between insulating layers, by selectively reducing the thickness of an insulating layer, or by forming openings in an insulating layer.

Abstract: The present invention provides a bonding structure between a dielectric substrate made of a dielectric material and a packaging substrate made of a heat conductive material involved in microwave integrated circuits. Both the dielectric and heat conductive materials have different coefficients of thermal expansions. The dielectric substrate has a top surface formed thereon with a top metallization pattern constituting impedance matching circuits and a bottom surface being bonded through a soldering agent to the packaging substrate. The bottom surface of the dielectric substrate has a bottom metallization pattern being selectively formed in a predetermined area thereon so that the soldering agent is applied only on the bottom metallization pattern to bond the dielectric and packaging substrates with each other. The bottom metallization pattern may be the same as the top metallization pattern.

Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36,38) is disposed between two of the fingers (16,18,20) for dividing current flow.

Abstract: A novel lid for sealing an encapsulant within a cavity of an integrated circuit package is disclosed herein. A ring is formed around a cavity opening, where a semiconductor die is located in an integrated circuit package. A lid, having a radially extending potion biased toward the die, is adapted to engage the cavity opening. According to one embodiment of the invention, a dam ring is disposed on the top surface of an integrated circuit package so as to form the cavity opening. A radially extending potion of the lid is adapted to engage the inner or outer surface of the ring so as to retain the lid in close communication with the cavity opening and seal the encapsulant within the cavity. Alternatively, the lid can be adapted to engage the cavity opening as existing in the top surface of an integrated circuit package. The present invention is especially advantageous in conjunction with ball grid array ("BGA") packages and pin grid array ("PGA") type IC packages.

Abstract: At a peripheral area of a semiconductor chip where active elements are not formed, a layer underlying a power supply wiring or ground wiring is provided with an uneven surface. The uneven or corrugated surface at the interface between the wiring and the underlying layer makes the wiring unsusceptible to slide. The uneven surface can be realized by interposing foreign matters between insulating layers, by selectively reducing the thickness of an insulating layer, or by forming openings in an insulating layer.

Abstract: A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.

Abstract: Short circuits in the power distribution network of a circuit structure are accurately located and isolated by providing selected power distribution lines with areas whose width is reduced sufficiently to produce a highly resolved current-induced hot spot in response to a downstream short circuit. The invention is particularly applicable to crossovers of power distribution lines separated by an insulating layer. The upper line is divided into a plurality of spaced parallel channels in the crossover vicinity. The channels each include areas of further reduced width at their opposite ends, preferably outside of but proximate to the crossover area, where the hot spots are formed. A short circuit on any of the channels is isolated by cutting at the areas of further reduced width on either side of the fault.

Abstract: A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.

Abstract: The present invention provides a semiconductor-type laminated ceramic capacitor with a grain boundary-insulated structure made of Sr.sub.(1-x) Ba.sub.x TiO.sub.3 as a main component, comprising the functions of a conventional capacitor which absorbs low voltage noises and high frequency noises, and a varistor when high voltage noises and electrostatic charges invade, wherein simultaneous sintering of the materials of ceramic capacitor together with the materials of inner electrodes was made possible in the manufacturing process. Besides a material to be made semiconductive is added to the main component of Sr.sub.(1-x) Ba.sub.x TiO.sub.3 with excess Ti, the materials of Mn-Si, which are converted to MnO.sub.2 and SiO.sub.2 in the sintering process, are also added to the main component.