Abstract: An apparatus comprises a stressed glass member and an actuator mounted on the stressed glass member. A power source is coupled to the actuator. An abrasion structure is disposed between the actuator and the stressed glass member. The abrasion structure comprises abrading features in contact with the stressed glass member. The abrading features have a hardness higher than a hardness of the stressed glass member. When energized by the power source, the actuator is configured to induce movement of the abrasion structure that causes the abrading features to create scratches in the stressed glass member to a depth sufficient to initiate fracture of the stressed glass member.

Abstract: Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor and a detector. The at least one tamper-respondent sensor includes conductive lines which form, at least in part, at least one tamper-detect network of the tamper-respondent sensor(s). In addition, the tamper-respondent sensor(s) includes at least one interconnect element associated with one or more conductive lines of the conductive lines forming, at least in part, the tamper-detect network(s). The interconnect element(s) includes at least one interconnect characteristic selected to facilitate obscuring a circuit lay of the at least one tamper-detect network. The at least one interconnect element is undetectable by x-ray, and the conductive lines are detectable by x-ray. In operation, the detector monitors the tamper-detect network(s) of the tamper-respondent sensor(s) for a tamper event.

Abstract: In an example, there is disclosed an electronic apparatus, comprising: a hardware-encoded internal private key; and one or more logic elements comprising a key generation engine to: receive an third-party key; and operate on the third-party key and the internal private key to generate a hardware-generated dynamic identifier (HGDI). There is also disclosed a method of providing an HGDI engine, and one or more computer-readable mediums having stored thereon executable instructions for providing an HGDI.

Abstract: There is provided a device for attachment to an image recording apparatus, the device comprising a blocker, attachable to said image recording apparatus, configured to inhibit said apparatus from recording an image when attached thereto; a transducer, connected to the blocker, configured to detect the change of position of the blocker between an attached position, wherein said apparatus is inhibited, and another position; and a controller, connected to the transducer, configured to store the position of the blocker when attached to said image recording apparatus and indicate if the blocker has changed position after it has been attached.

Abstract: Tamper-respondent assemblies, electronic assembly packages, and methods of fabrication are provided which include multiple, discrete tamper-respondent sensors that overlap, at least in part, and facilitate defining a secure volume about one or more electronic components to be protected, such as an electronic assembly. The tamper-respondent sensors include a first tamper-respondent sensor and a second tamper-respondent sensor, which may be similarly constructed or differently constructed. In certain embodiments, the tamper-respondent sensors wrap, at least in part, over an electronic enclosure, and in other embodiments, the tamper-respondent sensors cover, at least in part, an inner surface of an electronic enclosure to facilitate defining a secure volume in association with a multilayer circuit board to which the electronic enclosure is mounted.

Abstract: One example discloses a breach sensor, comprising: a substrate including an integrated circuit; a passivation layer coupled to the substrate; a breach sensing element coupled to the circuit; wherein the breach sensing element is on a first side of the passivation layer and the substrate is on a second side of the passivation layer; a barrier configured to separate the breach sensing element from an ambient environment; wherein the breach sensing element is responsive to barrier damage.

Abstract: Disclosed is a technique for prevention of false tamper positives experienced by an electronic device by use of a custom profile. The technique includes application of sensors of the device to collect data from the environment. Further, the device determines whether an event causes accidental triggering of tamper response as the environmental data varies. Accordingly, the conditions triggering a tamper response are dynamically changed as the environmental data changes.

Abstract: A secure PIN entry device including a PIN entry assembly operative to receive a PIN from a user, a PIN entry prompter operative when actuated to prompt a user to enter a PIN via the PIN entry assembly, a PIN entry prompt security check enabled controller operative to prevent operation of the PIN entry prompter unless a predetermined security check has been successfully completed and security check functionality operative to check at least part of the PIN entry device for the presence of an unauthorized PIN eavesdropping element thereat and to provide an output to the PIN entry prompt security check enabled controller indicating whether the predetermined security check has been successfully completed.

Abstract: A memory erasing method and apparatus for erasing important data of a nonvolatile memory within the apparatus to prevent illegal access using attitude information measured in an inertial measurement sensor and a low power microprocessor regardless of the power supply state of the apparatus. The apparatus includes a power switching circuit unit for selecting one from among an external power source and a battery. An inertial measurement sensor measures attitude information of the memory erasing apparatus, using power supplied from the external power source or the battery. A low power microprocessor erases important data from a memory device in a first manner using power from the external power source, and in a second manner using power from the battery, the first manner being different from the second manner.

Abstract: An arrangement for the protection of cryptographic keys and codes from being compromised by external tampering, wherein the arrangement is utilized within a multilayered securing structure. More particularly, there is provided a multilayered securing structure for the protection of cryptographic keys and codes, which may be subject to potential tampering when employed in computers and/or telecommunication systems. A method is provided for producing such multilayered securing structures within a modular substrate with the intent to protect cryptographic keys and codes which are employed in computers and/or telecommunication systems from the dangers of potential tampering or unauthorized access.

Abstract: A secure data storage system includes a mechanism that can be activated to inhibit access to stored data. In one embodiment, access to stored data can be prevented without having to erase or modify such data. An encryption key, or data used to generate the encryption key, is stored in an MRAM module integrated within the data storage system. The data storage system uses the encryption key to encrypt data received from a host system, and to decrypt the encrypted data when it is subsequently read by a host system. To render the stored data inaccessible, an operator (or an automated process) can expose the MRAM module to a magnetic field of sufficient strength to erase key data therefrom.

Abstract: Systems and methods of clearing system resources are disclosed. One example method includes the step of detecting a failure to clear a secure portion of a system resource in a device. The method also includes the step of powering off the system resource for a period of power-off time that is sufficient to clear data from the system resource, where the power off is responsive to the failure detection. The method also includes the step of unlocking the secure portion of the system resource, where the unlock is responsive to the period of power-off time having elapsed.

Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.

Abstract: A user interface for a fuel dispenser has a display, a display controller, and control circuitry. The control circuitry includes a processing device, memory, and at least one microswitch. The display controller and the control circuitry are positioned such that the microswitch connects the control circuitry to the display controller. The microswitch is activated if the control circuitry is separated from the display controller. Activation of the microswitch causes any sensitive information stored by the control circuitry to be erased. In one aspect, separation of the display controller from the control circuitry is the only manner by which the processing device and/or the memory may be accessed.

Abstract: When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.

Abstract: The invention relates to a method for manufacturing contactless portable objects having an integrated circuit, and to contactless portable objects having an integrated circuit. The method of the invention is characterized in that it comprises the following steps: providing a dielectric antenna substrate (6) which carries an antenna circuit (7) having at least one turn (7-1, 7-2, 7-3, 7-4) and two contact terminals (8-1, 8-2); providing a bridge (5) having a dielectric bridge substrate (1) and a chip (3) having an integrated circuit; and placing said bridge (5) with said chip (3) onto said dielectric antenna substrate (6) so that the bridge (5) straddles said at least one turn (7-1, 7-2, 7-3, 7-4) and forms an electric connection between said chip (3) and said antenna circuit (7). The invention is particularly useful for HF RFID objects.

Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.

Abstract: Disclosed is a tamper respondent covering. The tamper respondent covering has a cover-shaped structure to cover an electronic part which is exposed. This covering protects electronic parts embedded inside or exposed outside a product, such as ICs that contains data concerning security and certification, communication connectors that transmit data, etc. from a tempering operation or an alternating operation. The tamper respondent covering protects data from a tampering operation or an altering operation by erasing the data or disabling operation of the electronic part containing the data in response to an act of attempting to remove the covering from a printed circuit board of the electronic part or to drill a hole in the covering.

Abstract: An integrated circuit (1) is provided with function modules (2) which comprise a central processing unit (4) for treating data and executing a program and a cache memory (5). Until now, it was complicated and costly to ensure the manipulation security of the modules. The function modules (2) comprise an encoding unit (6) for data encoding and decoding.

Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.

Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.

Abstract: In a device having a plurality of circuits that can store at least a first value and a second value, a method can include configuring at least one circuit to persistently store the first value; determining whether the at least one circuit is storing the second value; and initiating a countermeasure if the at least one circuit is storing the second value. Determining whether the at least one circuit is storing the second value can include detecting whether the device has been attacked. Non-limiting examples of initiating a countermeasure can include resetting a portion of the device, powering down a portion of the device, activating an alarm circuit, causing protected data stored in the device to be erased, causing portions of the device to self-destruct, or causing the device to not respond to input applied to the interface.

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract: A method of fabricating an electronic circuit including forming a first depression on a first surface of a first wafer and forming a second depression on the first surface of the first wafer. The second depression is adjacent the first depression and separated from the first depression by a wall. The method further includes locating an actuator on the wall and attaching a first surface of a second wafer to the first surface of the first wafer to cover the first and second depressions. A first portion of the second wafer and the first depression define a first reservoir to contain a first chemical, and a second portion of the second wafer and the second depression define a second reservoir to contain a second chemical.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: The present invention provides a solution to the following problem: when using an electronic price tag device attached to a POP panel, an advertising content of the POP panel may be inconsistent with a price displayed on the electronic price tag device, and such inconsistency is left as is until a person in charge of a store site notices that. An electronic price tag device 1 includes detecting elements SW1 to SW3. A POP panel 30 is provided with a projected and recessed part 33 at a position, with the electronic price tag device 1 attached thereto, facing a detecting unit 16. The projected and recessed part 33 is formed to have different shapes corresponding to the types of the POP panel. Type information of the POP panel based on a signal output from the detecting elements SW1 to SW3 engaged with the projected and recessed part 33 is output to a display 4.

Abstract: A semiconductor device. The device includes a substrate and an integrated circuit chip. The device also includes an electrically or thermally reactive layer located between a top surface of the substrate and a bottom surface of the integrated circuit chip, wherein the reactive layer is positioned such that detection of tampering causes the reactive layer to be electrically or thermally energized such that the semiconductor device is at least partially destroyed.

Abstract: In order to extend the communication distance of an electronic tag chip, it is required to reduce power consumption of the electronic tag chip. After having formed capacitors and diodes on an SOI (Silicon on Insulator), remove a silicon substrate of the SOI. It becomes possible to reduce the capacitors and diodes of the electronic tag chip in parasitic capacitance relative to the ground, which makes it possible to reduce the power consumption of the electronic tag chip, thereby enabling the electronic tag chip to increase in communication distance thereof.

Abstract: Methods, systems, IC packages, and electrical devices for providing data security for ICs. A substrate-on-substrate connector grid array package with an electrical shield can protect sensitive information in a secure IC from being accessed by physical attacks. A current flow in the electrical shield can be monitored for disturbances which can indicate an attack on the IC package.

Abstract: A semiconductor chip includes a first integrated circuit chip and a depression substrate attached to the integrated circuit chip, wherein the integrated circuit chip and the depression substrate define a cavity therebetween. The semiconductor chip also includes a stress sensitive material located in the cavity and a chemical located in the cavity, wherein detection of tampering causes a reaction by the chemical such that the semiconductor chip is at least partially destroyed.

Abstract: A semiconductor chip includes a first integrated circuit chip and a depression substrate attached to the integrated circuit chip, wherein the integrated circuit chip and the depression substrate define a cavity therebetween. The semiconductor chip also includes a stress sensitive material located in the cavity and a chemical located in the cavity, wherein detection of tampering causes a reaction by the chemical such that the semiconductor chip is at least partially destroyed.

Abstract: Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operate and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the state of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.

Abstract: A security device watches over the secure functionality in a computer system. This “watcher” security device may be integrated within the computer system or may be separate from it. The security device queries the secure functionality to determine whether the state of the secure functionality is acceptable. If no satisfactory state exists, or if no response is received, then a signal is transmitted. The signal may be auditory (a buzzer) or visual (a flashing light) in order to signal to any user that the secure functionality has been compromised. Optionally, human input devices may be disabled, or a monitoring service notified, in conjunction with or in lieu of the signal. If the secure functionality includes a secret shared between the secure functionality and the user, then the security device may signal the secret. For example, where the secret is visual, the security device may display the secret.

Abstract: Wiring lines for the supply of a voltage to feed a drive voltage to an integrated circuit formed in a semiconductor chip are disposed so as to cover a main surface of the semiconductor chip, so that, if the wiring lines are removed for the purpose of analyzing information stored in the semiconductor chip, the integrated circuit does not operates and it is impossible to analyze the information. Further, there is provided a processing detector circuit for detecting that the wiring lines have been tampered with. When the processing detector circuit detects a change in the sate of the wiring lines, the integrated circuit is reset. Thus, it is possible to improve the security of information stored on the card.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: The semiconductor device (11) of the invention comprises a circuit covered by a passivation structure (50). It is provided with a first and a second security element (12A, 12B) which comprise local areas of the passivation structure (50), and with a first and a second electrode (14,15). The security elements (12A, 12B) have a first and a second impedance, respectively, which impedances differ. This is realized in that the passivation structure has an effective dielectric constant that varies laterally over the circuit. Actual values of the impedances are measured by measuring means and transferred to an access device by transferring means. The access device comprises or has access to a central database device for storing the impedances. The access device furthermore may compare the actual values with the stored values of the impedances in order to check the authenticity or the identity of the semiconductor device.

Abstract: A semiconductor device. The device includes a substrate and an integrated circuit chip. The device also includes an electrically or thermally reactive layer located between a top surface of the substrate and a bottom surface of the integrated circuit chip, wherein the reactive layer is positioned such that detection of tampering causes the reactive layer to be electrically or thermally energized such that the semiconductor device is at least partially destroyed.

Abstract: A tamper-resistant packaging approach protects non-volatile memory. According to an example embodiment of the present invention, an array of magnetic memory elements (130-132) in an integrated circuit (100) are protected from magnetic flux(122) by a package (106) including a magnet (120). Flux from the magnet is directed away from the magnetic memory elements by the package. When tampered with, such as by removal of a portion of the package for accessing the magnetic memory elements, the package allows the flux to reach some or all of the magnetic memory elements, which causes a change in a logic state thereof. With this approach, the magnetic memory elements are protected from tampering.

Abstract: A high security microcontroller (such as in a point of sale terminal) includes tamper control circuitry for detecting vulnerability conditions: a write to program memory before the sensitive financial information has been erased, a tamper detect condition, the enabling of a debugger, a power-up condition, an illegal temperature condition, an illegal supply voltage condition, an oscillator fail condition, and a battery removal condition. If the tamper control circuitry detects a vulnerability condition, then the memory where the sensitive financial information could be stored is erased before boot loader operation or debugger operation can be enabled. Upon power-up if a valid image is detected in program memory, then the boot loader is not executed and secure memory is not erased but rather the image is executed. The tamper control circuitry is a hardware state machine that is outside control of user-loaded software and is outside control of the debugger.

Abstract: Arrangement of nanowires with PN junctions between bit lines and word lines are arranged as a ROM memory cell array. A number of the nanowires have dielectric regions and are present only as a dummy. The connections between word and bit lines may also exist as transistors which turn on or turn off only when a gate voltage is applied. A number of these transistors are constructed in complementary fashion and/or have insulating regions built in and serve as a dummy.

Abstract: An example memory includes an address control portion, a protection film, a property deterioration material layer, data storage areas, and bonding pads. The protection film protects an organic semiconductor layer of a semiconductor circuit and prevents intrusion of moisture or chemical molecules in the air, light, or the like, into the organic semiconductor layer. Deterioration of the organic semiconductor layer is started by breaking the protection film and using a specified means, thus starting operation of the lifetime period. The property deterioration material layer contains a material for deteriorating the property of the organic semiconductor and deterioration of the organic semiconductor layer is started, for example, by diffusing the material into the organic semiconductor layer.

Abstract: The semiconductor device has a security coating with embedded magnetic particles and magnetoresistive sensors. This renders possible a measurement of the impedance of security elements defined by magnetoresistive sensors and security coating. If initial values of the impedance are stored, actual values can be compared therewith to see if the device has not been electrically probed or modified. Such a comparison can be used to check the authenticity of the device.

Abstract: When the scribe region 2 is cut off, the dicing detector 53 sends the detection signal A to the changeover circuit 51 and electrically shuts off the pad 50 and the inspection objective circuit 52, and the fixed potential of the input and output passage 54 from the changeover circuit 51 to the inspection objective circuit 52 is monitored by the detector 55. At the same time, the detection objective circuit 52 is changed into a mode, in which a reception of the command of the inspection mode is refused, by the detection signal A. In the case where an abnormality of the fixed potential of the input and output passage 54 is grasped, the inspection objective circuit 52 is changed into the safety mode.

Abstract: A semiconductor device has antenna pads and a testing pad formed on the substrate. An insulating resin layer containing a filler covers the testing pad, and bumps are provided on the antenna pads. Specific data in the semiconductor device are inhibited from being read out or rewritten, by the provision of the insulating resin layer containing a filler.

Abstract: An example memory includes an address control portion, a protection film, a property deterioration material layer, data storage areas, and bonding pads. The protection film protects an organic semiconductor layer of a semiconductor circuit and prevents intrusion of moisture or chemical molecules in the air, light, or the like, into the organic semiconductor layer. Deterioration of the organic semiconductor layer is started by breaking the protection film and using a specified means, thus starting operation of the lifetime period. The property deterioration material layer contains a material for deteriorating the property of the organic semiconductor and deterioration of the organic semiconductor layer is started, for example, by diffusing the material into the organic semiconductor layer.

Abstract: The present invention provides an apparatus and method for detecting if a person has attempted to tamper with an integrated circuit (IC). The apparatus is located on the IC and comprises detection circuitry that detects a build up of electrical charge on the IC and disablement circuitry that disables the IC when the detection circuitry detects a build up of electrical charge on the IC. The method comprises detecting if a build up of electrical charge on the IC has occurred and disabling the IC when a build up of electrical charge on the IC has been detected.

Abstract: The invention relates to a method for exchanging at least one secret initial value between a processing station and a chip card, in an initializing step for the chip card. In the initialization of chip cards in known methods an initial value, e.g. a key, is transmitted from a processing station to the chip card and stored therein. Since this key is transmitted in plaintext this involves security problems. In the present invention the described security problems are solved by only parts of the key being exchanged between processing station and chip card and the key being generated in the chip card and the processing station from the parts.

Abstract: The semiconductor device comprises a substrate (10) with a first (1) and an opposed second side (2), at which first side a plurality of transistors and interconnects is present, which are covered by a protective security covering (16), which device is further provided with bond pad regions (14). The protective security covering (16) comprises a substantially non-transparent and substantially chemically inert security coating (16), and the bond pad regions (14) are accessible from the second side of the substrate (10). The semiconductor device can be suitable made with a substrate transfer technique, in which a second substrate (24) is provided at the protective security covering (16).

Abstract: A system, method and apparatus for protecting circuit components from unauthorized access. The circuit components to be protected are disposed on a first layer of a substrate with a plurality of layers. A cover member composed of a plurality of layers is abutted to the substrate, defining an enclosure space for enclosing the circuit components to be protected. A three-dimensional resistive network sensor surrounds the protected circuit components. The sensor comprises at least one conduction path in at least one of the layers below the first layer of the substrate and at least one conduction path in at least one of the layers of the cover member and also comprises a plurality of vias transverse to and electrically connecting the conduction paths. A short or open in the sensor will be detected by a tamper detection circuit that is disposed on the first layer of a substrate.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.