With Means To Optimize Electrical Conductor Current Carrying Capacity (e.g., Particular Conductor Aspect Ratio) Patents (Class 257/923)
  • Patent number: 8106486
    Abstract: In a method of making an electronic apparatus, electronic devices and a mold are placed in a package such that pads of electronic devices are covered with the mold. An electrical insulator is poured into the package, in which the mold is placed, to fill the package. The mold is removed from the electrical insulator to form a space where the pads are exposed. An electrical conductor is placed in the space such that the pads are electrically connected together through the electrical conductor. The electrical conductor is in the form of a liquid or a solid having both fluidity and deformability.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 31, 2012
    Inventors: Kouji Yamamoto, Hirofumi Higuchi, Masaki Inoue
  • Patent number: 8097952
    Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: January 17, 2012
    Assignee: Richtek Technology Corp.
    Inventor: Yu-Lin Yang
  • Patent number: 8030745
    Abstract: The present invention provides an ID chip or an IC card in which the mechanical strength of an integrated circuit can be enhanced without suppressing a circuit scale. An ID chip or an IC card of the present invention has an integrated circuit in which a TFT (a thin film transistor) is formed from an insulated thin semiconductor film. Further, an ID chip or an IC card of the present invention has a light-emitting element and a light-receiving element each using a non-single-crystal thin film for a layer conducting photoelectric conversion. Such a light-emitting element or a light-receiving element may be formed consecutively to (integrally with) an integrated circuit or may be formed separately and attached to an integrated circuit.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7714429
    Abstract: A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: May 11, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Shouji Sakuma, Yoshiyuki Ishida
  • Patent number: 7202567
    Abstract: A lower interconnection is provided on a semiconductor substrate. A MIM capacitive element is provided on a first interlayer insulation film in which the lower interconnection is buried, and includes a lower electrode, an upper electrode, and a dielectric film sandwiched therebetween. An upper interconnection is provided on a second interlayer insulation film in which the MIM capacitive element is buried. A contact electrically connects the lower electrode and the upper interconnection. The lower electrode is mainly formed of Al, so that they are lower in electrical resistance than barrier metal, and also low in stress value. Therefore, it becomes possible to widen the area of the lower electrode for electrically connecting the contact while restraining their influences on charge accumulation and close contact between the lower electrode and the insulation film. In addition, since the electrical resistance is lowered, the thickness of the lower electrode can be increased.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: April 10, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Kuniko Kikuta, Makoto Nakayama
  • Patent number: 7145234
    Abstract: A circuit carrier and a package structure thereof are provided. The circuit carrier comprises a substrate having a surface, a plurality of passive component electrode pads or a plurality of passive component electrode planes on the surface of the substrate for electrically connecting a passive component corresponding to the plurality of passive component electrode pads, and a solder mask layer covering the surface of the substrate and including at least a solder mask opening, that entirely exposing the passive component electrode pads or a portion of the surface of each the passive component electrode plane corresponding to the passive component. Because there is no solder mask layer between the bottom of the passive component and the substrate, the gap between the passive component and the substrate will become wider. Hence, remaining flux can be entirely removed in order to increase the yield rate of the subsequent high temperature process.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: December 5, 2006
    Assignee: VIA Technologies, Inc.
    Inventors: Kenny Chang, Chi-Hsing Hsu
  • Patent number: 6987040
    Abstract: A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface (56). Source regions (66, 68) are formed along a vertical wall (84) inside of the trench (60). The source regions (66, 68) have a horizontal component along the major surface (56) and a vertical component extending the vertical wall (84). The majority of the source regions (66, 68) are formed along the vertical wall (84) within the trench (60). A typical aspect ratio of the vertical length of the source regions (66, 68) to the horizontal width is greater than 3:1. An Inter-layer dielectric (ILD) layer (74) is formed on the gate structure (62) within the trench (60) below the major surface (56).
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: January 17, 2006
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Prasad Venkatraman
  • Patent number: 6818946
    Abstract: A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface (56). Source regions (66,68) are formed along a vertical wall (84) inside of the trench (60). The source regions (66,68) have a horizontal component along the major surface (56) and a vertical component extending the vertical wall (84). The majority of the source regions (66,68) are formed along the vertical wall (84) within the trench (60). A typical aspect ratio of the vertical length of the source regions (66,68) to the horizontal width is greater than 3:1. An Inter-layer dielectric (ILD) layer (74) is formed on the gate structure (62) within the trench (60) below the major surface (56).
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: November 16, 2004
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Prasad Venkatraman
  • Patent number: 6777771
    Abstract: A method of manufacturing a high-gain, high-frequency device, such as a phased-array antenna, which uses such a switch having movable parts as a micromachine switch. The high-frequency device comprises a dielectric substrate on which are formed a plurality of waveguides for carrying high-frequency signals, a phase control layer, and dielectric spacers arranged between the phase control layer and another layer to provide space in which a switch formed in the phase control layer is enclosed.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: August 17, 2004
    Assignee: NEC Corporation
    Inventors: Tsunehisa Marumoto, Ryuichi Iwata, Youichi Ara, Hideki Kusamitsu, Kenichiro Suzuki
  • Patent number: 6617692
    Abstract: A semiconductor device in a computer system is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon connected to the integrated circuitry. At least one electrically conductive wire bond is made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads, which are not interconnected via the integrated circuitry within the die. The first bond pad can be a lead finger on the active surface and the second bond pad can be an option bond pad electrically connected to a third bond pad selected from the plurality of bond pads on the active surface via the integrated circuitry. Further, the third bond pad can connect to a fourth bond pad selected from the plurality of bond pads via a wire bond.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: September 9, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Schoenfeld
  • Patent number: 6586828
    Abstract: An electrical bus grid (108) for an application specific integrated circuit (ASIC) chip (102). The bus grid is generally formed by mutually orthogonal wires (28′, 30′) contained within two metal layer (M6′, M7′). The bus grid is located within each of a plurality of contiguous rectangular regions (32′), which are defined by electrical contacts (12′). Due to the regular pattern of the electrical contacts, the bus grids within the contiguous rectangular regions are identical to one another, such that the bus grid forms a repeatable pattern. The widths of the wires in each of the two metal layers vary depending upon the magnitude of the current carried by the corresponding wire. The magnitude of the current in the power bus may be determined by simulation and modeling performed prior to placement of cells (e.g., 18, 20, 22) within the ASIC chip.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Yu H. Sun
  • Patent number: 6380577
    Abstract: The tantalum chip capacitor of the present invention includes a anode terminal which is substantially flat. The tantalum wire which extends from the tantalum pellet through the insulating material terminates substantially flush with the insulating material, allowing the termination materials to be applied over a substantially flat surface. The tantalum chip capacitors of the present invention are created by methods which include the step of grinding the anode end of the capacitor so that the tantalum wire is flush with the insulating material. Conductive materials can then be applied to the anode end of the capacitor creating a substantially flat anode terminal.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: April 30, 2002
    Assignee: Vishay Sprague, Inc.
    Inventor: John Yates Cadwallader
  • Patent number: 6229163
    Abstract: A method for utilizing fractal analysis in the design and manufacture of semiconductor structures including transistor devices such as power MOS devices. The method includes using fractal theory to determine optimum source perimeter values to increase aspect ratio. The method is implemented to allow for use of the theoretical values in conjunction with known photolithographic fabrication techniques. The resultant structure thus incorporates the theoretically derived values to approximate a fractal structure.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: May 8, 2001
    Assignee: Fairchild Semiconductor Corp.
    Inventor: Daniel S. Calafut
  • Patent number: 5923089
    Abstract: A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: July 13, 1999
    Assignee: Oki America, Inc.
    Inventors: Chingchi Yao, Ichiro Yamamoto, Shuji Nomura
  • Patent number: 5917197
    Abstract: A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: June 29, 1999
    Assignees: Siemens Aktiengesellschaft, International Business Machines Corporation
    Inventors: Frank Alswede, William Davies, Ronald Hoyer, Ron Mendelson, Frank Prein
  • Patent number: 5864180
    Abstract: A semiconductor device and a method for manufacturing the same, in which a leak current generated in a pn junction formed between a silicon substrate and an epitaxial layer can be reduced. A silicon oxide film is formed on a silicon substrate having a (100) crystal plane. The silicon oxide film is patterned to form an opened portion and an inclined surface on a pattern edge of the silicon oxide film. The inclined surface forms an angle of 54.74.+-.5.degree. with the silicon substrate. An epitaxial layer is formed in the opened portion by selective epitaxial growth.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shizue Hori, Yoshiro Baba, Hiroyuki Sugaya, Hiroshi Naruse
  • Patent number: 5854515
    Abstract: A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
    Type: Grant
    Filed: July 23, 1996
    Date of Patent: December 29, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Basab Bandyopadhyay, H. Jim Fulford, Jr., Robert Dawson, Fred N. Hause, Mark W. Michael, William S. Brennan
  • Patent number: 5818110
    Abstract: An integrated circuit chip wiring structure having crossover and contact capability without an interlock via layer and a method of making the wiring structure all disclosed. The method utilizes a multi-damascene approach, using the standard damascene processing steps to wire the first, then metallization layer, then providing the second, thick metallization layer with first regions for metal wire. A conformal coating is deposited, filling the second regions but not the first regions. When an etch is performed, the layers underlying the second regions are exposed but not those underlying the second regions. Therefore, it is possible to selectively expose the metal lines in the first layer so that electrical connection is made with the metal wire of the second layer in the exposed areas. Electrical isolation is maintained in the narrower, second regions of metal wire.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: October 6, 1998
    Assignee: International Business Machines Corporation
    Inventor: John Edward Cronin
  • Patent number: 5808366
    Abstract: High speed integrated circuits are designed and fabricated by taking into account the capacitive loading on the integrated circuit by the integrated circuit potting material. Line drivers may be sized to drive conductive lines as capacitively loaded by the potting material. Repeaters may be provided along long lines, to drive the lines as capacitively loaded by the potting material. Intelligent drivers may sense the load due to the potting material and drive the lines as capacitively loaded by the potting material. The thickness of the passivating layer on the outer conductive lines may also be increased so as to prevent the potting material from extending between the conductive lines. High speed potted integrated circuits may thereby be provided.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: September 15, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Minkyu Song
  • Patent number: 5793098
    Abstract: In a package including a substrate, a conductive layer formed within the substrate, an internal lead element connected via a first throughhole to the conductive layer, and an external lead element connected via a second throughhole to the conductive layer, notches are formed in the conductive layer in close proximity to the first and second throughholes.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: August 11, 1998
    Assignee: NEC Corporation
    Inventor: Hiroyuki Uchida
  • Patent number: 5731606
    Abstract: Techniques are provided for protecting the cells of an array against deleterious effects of, for example, photolithography, etching and charge contamination. The cell array is designed to have edge cells modified at layout, or inactive edge cells, or guardrings surrounding the active array to contain the above effects, leaving the active cells highly reliable and with identical behavior.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: March 24, 1998
    Inventors: Ritu Shrivastava, Chitranjan N. Reddy
  • Patent number: 5648685
    Abstract: An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during same patterning process.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: July 15, 1997
    Assignee: Seiko Epson Corporation
    Inventors: Toshiyuki Misawa, Hiroyuki Oshima
  • Patent number: 5594281
    Abstract: In a semiconductor apparatus, a first circuit provided on a major surface of a semiconductor substrate. The first circuit includes a plurality of logic circuits of an identical structure, the logic circuits having input terminals supplied with identical signals. First metal wiring is provided on the semiconductor substrate in a direction identical to a direction of arrangement of the logic circuits, the first metal wiring being connected to one of the input terminals of each of the logic circuits. A second circuit provided on the major surface of the semiconductor substrate in an outside area which does not overlap an area extending in a direction perpendicular to the direction of arrangement of the logic circuits, the second circuit supplying an identical signal to the input terminals of the logic circuits of the first circuit. A second metal wiring is connected between an output terminal of the second circuit and a substantially middle point of the first metal wiring.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: January 14, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masami Masuda
  • Patent number: 5583788
    Abstract: A method, according to a hierarchical processing used for a computer-aided design system, for automatically wiring a circuit by dividing a region into a plurality of coarse global grids. The automatic wiring method includes the steps of: setting up and calculating an evaluation function having therein a plurality of evaluation terms for indicating selectability by which the cut-line is preferentially selected so that a wiring congestion is most relaxed; giving weights to the respective plurality of evaluation terms and defining an evaluation function which totals the plurality of the evaluation terms; dividing the region into two by a cut-line having a minimum value in the evaluation functions; determining a position to cross all nets crossing the cut-line; and performing the above steps recursively and hierarchically until the divided regions become a predetermined minimum size.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: December 10, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mototaka Kuribayashi
  • Patent number: 5532501
    Abstract: In a semiconductor device having a plurality of logic cell areas and a plurality of wiring channel areas therebetween, a wiring take-out cell for taking out wiring to the wiring channel areas is provided between specific logic cells which cannot be directly connected by the batting method.
    Type: Grant
    Filed: May 23, 1994
    Date of Patent: July 2, 1996
    Assignee: NEC Corporation
    Inventor: Takeshi Nakamura
  • Patent number: 5532509
    Abstract: A particular layout (38) of transistors along a continuous conductor line (54), such as the transistors in a CMOS inverter, has been found which reduces breaks or voids in the conductor line due to electromigration of the conductor atoms from predominantly unidirectional current flows. The conductor line may be a metal line. By alternating the two types of transistors, p- and n-type (40, 41, 46 & 47), along the length of the metal line, almost the entire length of the line can be changed to one with bidirectional current flow which significantly reduces the mean-time-to-failure for electromigration-related damage. The layout arrangement will find greater advantage for large transistors, long metal lines, relatively large unidirectional current flows and devices that run at high frequency, such as clock drivers.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: July 2, 1996
    Assignee: Motorola, Inc.
    Inventor: Michael L. D'Addeo
  • Patent number: 5414296
    Abstract: Operating characteristics of an electronics device in which alternating currents flow are improved by reducing positive electromagnetic coupling between currents. This is accomplished by altering the direction of a current flow to obtain negative coupling through current flow in the same direction, or by minimizing electromagnetic coupling through perpendicular current flow, or by increasing the spacing between two electromagnetically coupled currents. In a bipolar transistor structure a feed structure for emitter and base current includes wire bonding pads aligned so that emitter current and base current flow to wire bonding pads perpendicular to the direction of collector current flow and with adjacent emitter currents and base currents flowing in the same direction. Each feed structure includes a plurality of interdigitated fingers for contacting emitter and base regions, all emitter and base currents in said interdigitated fingers of all feed structures flowing in the same direction as the collector.
    Type: Grant
    Filed: May 2, 1994
    Date of Patent: May 9, 1995
    Assignee: Spectrian, Inc.
    Inventor: Howard D. Bartlow
  • Patent number: 5410162
    Abstract: An apparatus and method for rapidly changing the temperature of a semiconductor wafer, in order to perform electrical tests or stress at elevated temperature, and then cool rapidly to ambient temperature. The apparatus is comprised of a wafer support 17, capable of supporting the wafer, mounted on top of a rapid thermal processing (RTP) illuminator 20 (lamps, preferably halogen), and including one or more probe needles 22, capable of contacting the wafer to perform electrical measurements. A semiconductor wafer 16 is placed upon the wafer support 17 and the RTP illuminator 20 located beneath is activated, rapidly elevating the wafer to the desired temperature. Electrical tests may be performed as desired during the process.
    Type: Grant
    Filed: October 15, 1993
    Date of Patent: April 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Howard L. Tigelaar, Mehrdad M. Moslehi
  • Patent number: 5329156
    Abstract: The feeds to the emitter, base, and collector of an RF power transistor (source, drain, gate feeds of an RF FET) are configured so that negative mutual coupling therebetween is enhanced and positive mutual coupling therebetween is reduced. The emitter and base feeds include elongated portions which are generally parallel to each other with bonding pads provided on the elongated portions so that emitter and base currents flow in the same direction in the elongated portions and in the same direction as collector currents below. Interdigitated contact fingers extend from the elongated portions and contact the emitter region and the base region, respectively. When positive coupling of collector current and emitter current to the controlling base current is reduced or eliminated, the major thermal imbalance problem of operating RF transistors is also reduced or eliminated. Performance, linearity, efficiency, gain, and ruggedness are all enhanced in devices designed to utilize this invention.
    Type: Grant
    Filed: December 22, 1992
    Date of Patent: July 12, 1994
    Assignee: Spectrian, Inc.
    Inventor: Howard D. Bartlow
  • Patent number: 5317184
    Abstract: Semiconductor devices with elongated well regions in a stripe geometry pattern include uniformly sized source exclude areas that are longitudinally offset with respect to source exclude areas in adjacent well regions. The uniformity of the current density in neck regions is increased, thereby increasing the current carrying capability of the device.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: May 31, 1994
    Assignee: Harris Corporation
    Inventor: Christopher L. Rexer
  • Patent number: 5285110
    Abstract: An interconnection structure of a semiconductor device for electrically connecting a thin conductive layer and a metallization and the fabrication method thereof are disclosed. The interconnection structure includes a semiconductor substrate, an insulating layer coated on the substrate, a thick conductive layer formed on a certain portion of the insulating layer, a first interlaid insulating layer covering the thick conductive layer, a first contact hole formed within the first interlaid insulating layer on the thick conductive layer, a thin conductive layer consisting of vertical structure formed in the first contact hole and horizontal structure formed on the first interlaid insulating layer, a second interlaid insulating layer covering the thin conductive layer, a second contact hole formed within said first and second interlaid insulating layers and crossing the first contact hole, and a metallization filling the second contact hole and formed on the second interlaid insulating layer.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: February 8, 1994
    Assignee: Samsung Electronicw Co., Ltd.
    Inventors: Dong-joo Bae, Sung-nam Chang
  • Patent number: 5248347
    Abstract: In a semiconductor device having a metal electrode on a crystalline semiconductor surface, the metal electrode includes first portions electrically and mechanically connected to the surface and second portions mechanically separated from the surface and having configurations that easily deform. These first and second portions are alternatingly arranged on the surface. Accordingly, stress applied to the semiconductor beneath the electrode is reduced and deformation of the semiconductor element due to thermal stress is prevented, thereby preventing deterioration of element characteristics.
    Type: Grant
    Filed: February 6, 1992
    Date of Patent: September 28, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Seiji Ochi
  • Patent number: 5185651
    Abstract: An apparatus for monitoring the current in an integrated circuit provided with a current conductor which is to supply current to a semiconductor structure at least temporarily and to supply current to other parts of the circuit. The current conductor is locally split into a first and a second parallel partial current conductor, with the semiconductor structure connected to the first partial current conductor. The first and second partial current conductors are connected to respective first and second connection contacts across which a voltage drop can be derived which is a measure of the value of the current flowing through the semiconductor structure.
    Type: Grant
    Filed: July 12, 1990
    Date of Patent: February 9, 1993
    Assignee: U.S. Philips Corporation
    Inventor: Hendrik Boezen
  • Patent number: RE48420
    Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: February 2, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Bernhard P. Lange, Anthony L. Coyle, Quang X. Mai