Bridge Rectifier Module Patents (Class 257/925)
  • Patent number: 8884385
    Abstract: Provided by some aspects of the invention is a relatively low-cost, relatively highly accurate physical quantity sensor, and a manufacturing method thereof, that relaxes thermal stress from an outer peripheral portion of a diaphragm in a silicon-on-nothing (“SON”) structure. By providing a stress relaxation region (trench groove) in an outer peripheral portion of a diaphragm in a SON structure, there can be, in some aspects of the invention, a benefit of relaxing the transmission to the diaphragm of thermal stress generated by the difference in linear expansion coefficient between a package and chip, and it is possible to relax the transmission to an electronic circuit disposed in an outer peripheral portion of mechanical stress generated by a measured pressure. As a result of this, it is possible to provide a highly accurate physical quantity sensor.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Mutsuo Nishikawa, Kazunori Saito
  • Patent number: 8547072
    Abstract: A phase control apparatus includes a first transistor whose source or emitter is connected to one end of an AC power supply and whose drain or collector is connected to one end of a load, a second transistor whose source or emitter is connected to the other end of the AC supply and whose drain or collector is connected to the other end of the load, a diode bridge that rectifies an AC voltage of the AC supply, and a parallel circuit of a zener diode and a capacitor. The parallel circuit generates a high potential relative to a bridge negative output terminal potential, or generates a low potential relative to a bridge positive output terminal potential. First and second transistor control terminal potentials are switched between the high and the bridge negative output terminal potentials, or between the low and the bridge positive output terminal potentials.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: October 1, 2013
    Assignee: Maeda Metal Industries, Ltd.
    Inventor: Takayoshi Obatake
  • Patent number: 8426931
    Abstract: To provide a semiconductor device prevented from giving a limitation on the sensitivity of HEMS devices due to isolation regions thereof and a method of fabricating the same.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: April 23, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Toma Fujita, Hironobu Kawauchi, Haruhiko Nishikage
  • Patent number: 5942797
    Abstract: A power semiconductor module in which a plurality of power semiconductor elements forming a bridge circuit are provided together with control circuits. The module includes a common casing which accommodates a metal base, a main circuit section, and a control circuit section. The main circuit section has a plurality of semiconductor elements of the bridge circuit mounted on a ceramic insulating board which is thermally coupled to the metal base. The main circuit section also supports connecting conductors to which the semiconductor elements are connected. In the control circuit section are mounted control circuits for the semiconductor elements. The control circuits are mounted on a wiring substrate which is formed by wiring conductors on an insulating board. The main circuit section is connected through a bond to the control circuit section. Input and output terminals of the bridge circuit are extended from the connecting conductors of the main circuit section.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: August 24, 1999
    Assignee: Fuji Electric Co. Ltd.
    Inventor: Noriho Terasawa
  • Patent number: 5929519
    Abstract: An inverter device includes plural modules, each module being formed by a series circuit having a parallel circuit of a switching device and a first diode, and a parallel circuit of a second switching device and a second diode, allowing a reduced size, high reliability, high frequency switching and low noise. Each of the semiconductor modules includes a plurality of switching device chips and at least one diode chip formed on a metal substrate. Electrode plates are provided in locations of the module adjacent to the switching device chips and the diode chips to facilitate connection of the electrodes of the respective chips to one another and to the outside of the module.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: July 27, 1999
    Assignee: Hitchi, Ltd.
    Inventors: Mutsuhiro Mori, Ryuichi Saito, Shin Kimura, Syuuji Saitoo, Kiyoshi Nakata, Akira Horie, Yoshihiko Koike, Shigeki Sekine
  • Patent number: 5821618
    Abstract: A semiconductor component includes an insulating housing. A plurality of sheet-metal mounting plates are disposed in one and the same plane and are electrically separated from one another in the housing. Semiconductor switches of a rectifier bridge are electrically conductively secured to the mounting plates. Sheet-metal connection leads are electrically connected to the semiconductor switches. At least one sheet-metal connection lead is electrically connected to the mounting plates.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: October 13, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventors: Alfons Graf, Peter Huber, Xaver Schloegel, Peter Sommer
  • Patent number: 5773885
    Abstract: A power rectifier has a diode blank sandwiched between a pair of contacts which apply progressive compressive loads upon the diode blank as the temperature of the diode assembly increases. Preferably, the contacts are formed from dissimilar metals having different thermal expansion characteristics and are operatively coupled such that the thermal expansion differential translates into the desired compressive load characteristic.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: June 30, 1998
    Assignee: General Motors Corporation
    Inventor: Roy Burton Steele
  • Patent number: 5731606
    Abstract: Techniques are provided for protecting the cells of an array against deleterious effects of, for example, photolithography, etching and charge contamination. The cell array is designed to have edge cells modified at layout, or inactive edge cells, or guardrings surrounding the active array to contain the above effects, leaving the active cells highly reliable and with identical behavior.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: March 24, 1998
    Inventors: Ritu Shrivastava, Chitranjan N. Reddy
  • Patent number: 5592022
    Abstract: An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: January 7, 1997
    Assignee: ChipScale, Inc.
    Inventors: John G. Richards, Hector Flores, Wendell B. Sander
  • Patent number: 5589708
    Abstract: A method is provided for forming a radiation hard dielectric region of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide region, a gate oxide layer and an interlevel dielectric layer are formed over the integrated circuit. Silicon ions are implanted separately into the field oxide region, gate oxide layer and interlevel dielectric layer to a sufficient dosage of less than or equal to approximately 1.times.10.sup.14 /cm.sup.2 to form electron traps to capture radiation induced electrons. This method allows for selective enhancement of radiation hardness of a portion of a circuit, thus providing an on-chip "dosimeter" which can be used to compensate the circuit for the loss of performance due to ionizing radiation.
    Type: Grant
    Filed: January 5, 1995
    Date of Patent: December 31, 1996
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Alexander Kalnitsky
  • Patent number: 5512782
    Abstract: A semiconductor device for converting DC input power to AC output power includes a package having a rectangular shape with four side edges and containing a plurality of semiconductor chips therein. Two pairs of positive and negative terminals of DC input terminals are situated on the side edges to face to each other such that the same polar terminals in the positive and negative terminals face to each other. AC output terminals and control terminals are arranged on the side edges where the DC input terminals are not formed.
    Type: Grant
    Filed: October 4, 1994
    Date of Patent: April 30, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Shinichi Kobayashi
  • Patent number: 5506441
    Abstract: A semiconductor device includes a plurality of groups of transistor elements which are formed on a single semiconductor chip, each group having a first pair of transistor elements which are arranged so as to be symmetrical about a point and a second pair of transistor elements which are arranged, in a direction perpendicular to a direction in which the first pair of transistor elements are arranged, so as to be symmetrical about the point. The first pair of transistor elements in all the plurality of groups are connected in parallel so that a first transistor is formed of the first pair of transistor elements, and the second pair of transistor elements in all the plurality of groups are connected in parallel so that a second transistor is formed of the second pair of transistor elements, the first transistor and the second transistor being paired.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: April 9, 1996
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Misao Furuya
  • Patent number: 5391919
    Abstract: A semiconductor device module is formed of four identical frame sections which each have a flat base and perpendicularly extending strap terminal. Semiconductor chips are soldered to the center of the top surfaces of each base, and the devices are interconnected by flat brass strips having one end soldered to the top of one chip and the other end soldered to the base of an adjacent section. The base sections lie in a common plane at the bottom of an insulative filled insulation cup. The terminals extend parallel and out of the top of the cup.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: February 21, 1995
    Assignee: International Rectifier Corporation
    Inventors: Aldo Torti, Emilio Mattiuzzo
  • Patent number: 5296731
    Abstract: A semiconductor integrated circuit device according to the present invention includes a semiconductor layer of a first conductivity type having a high concentration of impurity atoms which layer is formed in or on predetermined locations of a semiconductor substrate with the first conductivity type which locations requires a resistance to alpha rays. The device of the present invention can decrease the amount of the electron collection to a semiconductor layer of a second conductivity type having a high concentration of impurity atoms which layer is separated from the semiconductor layer of the first conductivity type having a high concentration of impurity atoms. Therefore, the semiconductor integrated circuit device of the present invention can have enhanced resistance to alpha rays without capacitances being increased and maintain a fast speed of circuit operation.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: March 22, 1994
    Assignee: NEC Corporation
    Inventor: Takenori Morikawa
  • Patent number: 5278430
    Abstract: A complementary semiconductor device incorporating semiconductor composed of diamond. Substantially, diamond is insulative. When both III group elementary atoms and V group elementary atoms are doped into diamond, the doped regions respectively turn into p-type and n-type semiconductors. The embodiment discretely dopes both III group elementary atoms and V group elementary atoms into a layer of diamond thin film to eventually form a complementary semiconductor device. The embodiment forms wiring system inside of the diamond thin film by selectively doping either III group elementary atoms or V group elementary atoms therein without forming wiring system only on the inter-layer insulation film.
    Type: Grant
    Filed: February 18, 1992
    Date of Patent: January 11, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakazu Kakumu