Abstract: A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.

Abstract: The invention relates to a rechargeable battery (1) comprising several storage modules (3) for electric current, wherein the storage modules (3) are interconnected via at least one busbar (4), and a cooling device (2), which comprises a single-layer or multi-layer film (5) and with this film (5) lies against the at least one busbar (4), is arranged on the busbar (4).

Abstract: A semiconductor arrangement includes a circuit board having a metallization layer with first and second conductor tracks. The first conductor track has a base section and first, second and third sections, the third section arranged between the first and second sections. The second conductor track has first and second sections. The first section of the second conductor track is arranged between the first and third sections of the first conductor track. The second section of the second conductor track is arranged between the second and third sections of the first conductor track. The third section of the first conductor track is arranged between the first and second sections of the second conductor track. First and second subsets of semiconductor chips are arranged on the first section of the second conductor track. Third and fourth subsets of semiconductor chips are arranged on the second section of the second conductor track.

Abstract: An amplification unit 1 has an output connector 3 for outputting an RF signal output by an amplification circuit 2 for each amplification circuit. The output connectors 3 are disposed so as to be arranged in the horizontal direction. A combining unit 5 has an input connector 6 into which the RF signal output from the output connector 3 of the amplification unit 1 is input for each output connector 3. The input connectors are disposed so as to be arranged in the horizontal direction. The amplification unit 1 and the combining unit 5 are attachable/detachable through the output connectors 3 and the input connectors 6. The surface on which the input connectors are provided of the combining unit 5 is set within the dimension of the surface on which the output connectors are provided of the amplification unit 1.

Abstract: In a rotary electric machine, wound wires are connected to a first terminal and a second terminal. Circuit terminals that are configured from a conductive metal other than aluminum, and the first terminal and the second terminal that are configured from a metal with a principal component of aluminum are joined together inside a circuit chamber that has high water resistant properties. Corrosion is accordingly suppressed at join sites of the circuit terminals with the first terminal and the second terminal. There is therefore no need to coat the join sites with for example a sealing material in order to suppress corrosion at the join sites. Good electrical continuity is accordingly enabled between the circuit terminals and the wound wires while suppressing an increase in costs, even when the wound wire is configured from a metal with a principal component of aluminum.

Abstract: In a rotary electric machine, wound wires are connected to a first terminal and a second terminal. Circuit terminals that are configured from a conductive metal other than aluminum, and the first terminal and the second terminal that are configured from a metal with a principal component of aluminum are joined together inside a circuit chamber that has high water resistant properties. Corrosion is accordingly suppressed at join sites of the circuit terminals with the first terminal and the second terminal. There is therefore no need to coat the join sites with for example a sealing material in order to suppress corrosion at the join sites. Good electrical continuity is accordingly enabled between the circuit terminals and the wound wires while suppressing an increase in costs, even when the wound wire is configured from a metal with a principal component of aluminum.

Abstract: A plurality of parallel capacitors is constructed using an elongate common capacitor electrode with individual capacitors formed from individual capacitor electrodes spaced along and separated from the common electrode by a layer of dielectric material. The layer of dielectric material can be a dielectric film material or a ceramic material. The layer of dielectric material can be tapered along the common electrode, and/or additional dielectric material can be positioned between edges of adjacent individual electrodes. An individual electrode at one end of the common electrode can be made wider to increase its capacitance.

Abstract: The invention discloses a package structure of a driving apparatus of a display. The driving apparatus of the display includes a plurality of driving units. The package structure includes a substrate and a plurality of package units. The substrate is used to carry the plurality of driving units. The plurality of driving units is apart to each other. The plurality of package units is used to package the plurality of driving units respectively to form a plurality of driving unit package body apart to each other. A total output channel number of the driving apparatus of the display equals to a total channel number of the plurality of driving units. This package structure can avoid heat concentration on the driving apparatus of the display to achieve good cooling effect and output effectiveness of the driving apparatus of the display will be not reduced accordingly.

Abstract: Semiconductor packages are provided. The semiconductor packages may include an upper package including a plurality of upper semiconductor devices connected to an upper package substrate. The semiconductor packages may also include a lower package including a lower semiconductor device connected to a lower package substrate. The upper and lower packages may be connected to each other.

Abstract: A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.

Abstract: A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.

Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.

Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

Abstract: In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate.

Abstract: A packaged power supply module (100) comprising a chip (110) with a first power field effect transistor (FET) and a second chip (120) with a second FET conductively attached side-by-side onto a conductive carrier (130), the transistors having bond pads of a first area (210) and the carrier having bond pads of a second area (230) smaller than the first area. Conductive bumps (114, 115, 124, 125) attached to the transistor bond pads and conductive bumps (126) attached to the carrier bond pads have equal volume and are coplanar (150), the bumps on the transistor pads having a first height and the bumps on the carrier pads having a second height greater than the first height.

Abstract: Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments.

Abstract: A power semiconductor device has the power semiconductor elements having back surfaces bonded to wiring patterns and surface electrodes, cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, a transfer mold resin having concave parts which expose the upper surfaces of the communication parts and cover the insulating layer, the wiring patterns, and the power semiconductor elements. External terminals have one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, a bent area which is bent in an L shape and is embedded in the concave part of the transfer mold resin.

Abstract: First chip main surfaces of first semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the first semiconductor chips are bonded to a first electrode. First chip main surfaces of second semiconductor chips are bonded to a heat spreader, and second chip main surfaces of the second semiconductor chips are bonded to a first electrode. A plurality of electrodes are provided by a lead frame. An insulating member is provided on a side opposite to the chips when viewed from the heat spreader. An insulating substrate is provided on a side opposite to the chips when viewed from the first electrodes.

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Abstract: A power semiconductor structure with a field effect rectifier having a drain region, a body region, a source region, a gate channel, and a current channel is provided. The body region is substantially located above the drain region. The source region is located in the body region. The gate channel is located in the body region and adjacent to a gate structure. The current channel is located in the body region and is extended from the source region downward to the drain region. The current channel is adjacent to a conductive structure coupled to the source region.

Abstract: The invention provides semiconductor material (e.g., gallium nitride material) devices (e.g., transistors) and methods associated with the same. The devices may be supported within a package that is formed, in part, of a polymeric material. In other embodiments, the devices may be mounted to a support (e.g., circuit board) and a polymeric material may encapsulate a portion of the device extending from the support.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress can escape. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board serving as a current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and cracks of the cover plate.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.

Abstract: An elastic printed board is provided so that stress applied by the silicon gel is absorbed by the printed board. Further, the printed board is formed to be so narrow that the stress may be escaped. On the other hand, the wires on which a high voltage is applied are patterned on respective printed boards. This serves to prevent discharge through the surface of the same printed board served as current passage. This design makes it possible to hermetically close the power module, prevent intrusion of moisture or contamination as well as displacement, transformation and crack of the cover plate.

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Abstract: A packaged microchip has a base, at least one spacer coupled to the base, and first and second microchips mounted to the at least one spacer. The at least one spacer is configured to substantially prevent leakage current between the first and second microchips.

Abstract: A lead frame facilitates the handling, positioning, attachment, and/or continued integrity of multiple dies, without the use of multiple separate parts, such as jumpers. The lead frame includes a number of structures, each of which is attached to at least one lead. At least one receiving surface, arranged to receive a die, is associated with each structure. When dies are disposed on the receiving surfaces, anodes are similarly-oriented. A number of fingers are attached to the lead frame, and one or more electrode contact surfaces are attached to each finger. Each electrode contact surface can be positioned (for example, bent) with respect to one receiving surface, to facilitate electrical connection between the anode of a die and a lead. The lead frame may be used in connection with surface- and through-hole-mountable electronic devices, such as bridge rectifier modules.

Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.

Abstract: A semiconductor module includes a semiconductor chip, a semiconductor frame, a circuit board, and a screw. The semiconductor frame has a main surface having a concave portion in which the semiconductor chip is mounted. The semiconductor frame is thermally and electrically connected with the semiconductor chip through a die bonding material. The circuit board has a grounding pattern and is arranged above the main surface of the semiconductor frame. The screw electrically connects the main surface of the semiconductor frame and the outer peripheral portion of the concave portion to the grounding pattern of the circuit board and mechanically connects the semiconductor frame to the circuit board.

Abstract: A method for producing a semiconductor chip with an adhesive film, which includes: preparing a laminate in which a semiconductor wafer, an adhesive film and a dicing tape are laminated in that order, the adhesive film having a thickness in the range of 1 to 15 ?m and a tensile elongation at break of less than 5%, and the tensile elongation at break being less than 110% of the elongation at a maximum load, and the semiconductor wafer having a section, for dividing the semiconductor wafer into a plurality of semiconductor chips, which is formed by irradiating with laser light; dividing the semiconductor wafer into a plurality of semiconductor chips without dividing the adhesive film, by expanding the dicing tape; and dividing the adhesive film by picking up the plurality of semiconductor chips.

Abstract: This research discloses an ultra wideband system-on-package (SoP). The SoP includes a package body; a first integrated circuit mounted on the package body; a first signal transmission unit connected to the first integrated circuit; a signal via connected to the first signal transmission unit and including a slab line and a trough line; and a second signal transmission unit connected to the signal via. The technology of the present research can transmit ultra broadband signals by minimizing discontinuity of signals appearing during vertical transition that occurs in the course of a signal transmission to/from an external circuit, and a fabrication method thereof.

Abstract: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).

Abstract: A semiconductor device is provided by the present invention. The semiconductor device includes a first semiconductor die comprising at least a first bond pad; and a second semiconductor die comprising at least a second bond pad with voltage level equivalent to the first bond pad of the first semiconductor die; wherein the first bond pad of the first semiconductor die is electrically connected to the second bond pad of the second semiconductor die via at least a bond wire. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost.

Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.

Abstract: An encapsulated leadless semiconductor package comprises a first semiconductor die and a second semiconductor die which are electrically connected by a bond wire. The lower surface of the first semiconductor die and the lower surface of the second semiconductor die are essentially coplanar with the lower surface of the encapsulation material.

Abstract: Disclosed herein is a semiconductor integrated circuit including: a plurality of standard cells including a transistor having a gate electrode and arranged in combination with each other; a metallic wiring layer interconnecting the standard cells to form a desired circuit; and a plurality of reserve cells having a gate electrode, unconnected with the metallic wiring layer and arranged on a periphery of the standard cells, wherein each of the gate electrodes of the standard cells and the reserve cells has a gate pad section and two gate finger sections extending from the gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad sections of the reserve cells in a direction orthogonal to the predetermined direction is equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance.

Abstract: An electronic circuit arrangement includes a heat sink and a first circuit carrier which is thermally coupled to the heat sink, lies flat on the latter and is intended to wire electronic components of the circuit arrangement. Provided for at least one electronic component is a special arrangement which is associated with a considerably increased heat dissipation capability for the relevant component and, in addition, also affords further advantages in connection with changes in the population and/or line routing which might occur in practice. The important factor for this is that the component is arranged under a second circuit carrier which is held in a recess in the first circuit carrier. The recess passes through to the top side of the heat sink.

Abstract: A high reliability power module which includes a plurality of hermetically sealed packages each having electrical terminals formed from an alloy of tungsten copper and brazed onto a surface of a ceramic substrate.

Abstract: Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are electrically disconnected from any circuit of the die, i.e., “dummy” solder balls, and are used to temporarily hold the die in position with respect to the PCB until the circuit is wire bonded and an underfill material is cured between the die and the PCB to more permanently connect them together. The underfill material is selected to have a coefficient of thermal expansion (CTE) that is substantially equal to the CTE of the solder balls to prevent thermal mismatch problems. An overmolding compound is disposed about the die and the underfill material and about the wire bonds to complete the package. Various arrangements of the solder ball pads on the die include columnar and row, corner, diagonal, cross, and periphery arrangements.

Abstract: In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with an insulating film which applies lower stress than the stresses applied by the above-described two films.

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract: A semiconductor device package includes a substrate with one or more pads and at least one semiconductor device that has one or more of its electrodes electrically connected to the substrate pads. The package also includes one or more terminals in electrical connection with the substrate pads and that provide for external connection to the device.

Abstract: Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

Abstract: A lead frame facilitates the handling, positioning, attachment, and/or continued integrity of multiple dies, without the use of multiple separate parts, such as jumpers. The lead frame includes a number of structures, each of which is attached to at least one lead. At least one receiving surface, arranged to receive a die, is associated with each structure. When dies are disposed on the receiving surfaces, anodes are similarly-oriented. A number of fingers are attached to the lead frame, and one or more electrode contact surfaces are attached to each finger. Each electrode contact surface can be positioned (for example, bent) with respect to one receiving surface, to facilitate electrical connection between the anode of a die and a lead. The lead frame may be used in connection with surface- and through-hole-mountable electronic devices, such as bridge rectifier modules.

Abstract: Electrode plates acting as a heat sink are arranged to sandwich a power transistor and a diode. Electrode plates at their surfaces opposite cooling elements at a portion opposite power transistor and diode are formed to be smaller in thickness at a portion adjacent to power transistor and diode substantially at the center than at a periphery. Cooling elements are disposed geometrically along electrode plates to sandwich electrode plates.

Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.

Abstract: A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. In one embodiment, in which semiconductor devices are to be stacked over and secured to the substrate in a flip-chip type arrangement, the contact areas correspond to bond pads of an upper, second semiconductor device, while other contact areas located within the first region correspond to bond pads of a lower, first semiconductor device. In another embodiment, the contact areas correspond to bond pads of the first semiconductor device, which are electrically connected thereto by way of laterally extending discrete conductive elements, while other contact areas that are located external to the second region correspond to bond pads of the upper, second semiconductor device.

Abstract: Monolithic semiconductor structures having at least two pairs of two lateral semiconductor devices combined on a first surface of a single semiconductor substrate. Embodiments include connected source terminals defining common source terminals.