Barrier Layer Device Making Patents (Class 29/25.02)
  • Patent number: 6563555
    Abstract: An MIM nonlinear device having a large nonlinearity coefficient that represents the sharpness of the voltage-current characteristic, a liquid crystal display panel with high image-quality that uses this device, and a manufacturing method of said MIM nonlinear device are provided. The MIM nonlinear device contains a first conductive film 22, an insulating film 24, and a second conductive film 26 laminated on a substrate 30. The insulating film 24 may contain water, and in the insulating film, in a thermal desorption spectrum, a peak derived from water in the insulating film is 225-300° C. Further, in said thermal desorption spectrum, the number of molecules calculated from the area of the peak derived from the water is preferably 5×1014/cm2 or more.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: May 13, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Inoue, Yasushi Takano, Takeyoshi Ushiki, Takumi Seki
  • Publication number: 20030073263
    Abstract: The present invention is a method of fabricating a semiconductor device by transferring a semiconductor chip supported on a flexible support film to a mount member by means of a robot arm. This method comprises a film bending step of bending a support film so that same has a pickup face that lies along the movement direction of the robot arm and a withdrawal face that lies substantially perpendicular to this movement direction and does not interfere with the robot arm; a step of disposing the mount member, whereon the semiconductor chip is to be mounted, in a position facing the withdrawal face and flanking on the pickup face; and a step of picking up the semiconductor chip from the pickup face by means of the robot arm and transferring the semiconductor chip to the mount member.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 17, 2003
    Inventor: Takayuki Kito
  • Publication number: 20020136971
    Abstract: A laser processing apparatus comprises a laser oscillator for producing a laser beam to selectively remove part of a substrate to be processed, a scanning system for applying the laser beam to an arbitrary position of the substrate and incident means for applying the laser beam to the substrate substantially at right angle.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 26, 2002
    Applicant: KABUSHIKI KAISHA
    Inventors: Shinichi Ito, Tatsuhiko Higashiki, Hiroshi Ikegami, Nobuo Hayasaka
  • Patent number: 6449521
    Abstract: A method and apparatus for reducing fluorine and other sorbable contaminants in plasma reactor used in chemical vapor deposition process such as the deposition of silicon oxide layer by the reaction of TEOS and oxygen. According to the method of the present invention, plasma of an inert gas is maintained in plasma reactor following chamber clean to remove sorbable contaminants such as fluorine. The plasma clean is typically followed by seasoning of the reactor to block or retard remaining contaminants. According to one embodiment of the invention, the combination of chamber clean, plasma clean, and season film is conducted before PECVD oxide layer is deposited on wafer positioned in the plasma reactor.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: September 10, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Anand Gupta
  • Publication number: 20020104206
    Abstract: A substrate processing apparatus comprises a substrate processing chamber for processing a substrate, a load lock chamber, a gas supply line for supplying gas into the load lock chamber, exhaust lines for exhausting the load lock chamber, a moving mechanism provided in the load lock chamber and capable of moving the substrate, local exhaust lines capable of locally exhausting dust generating portions of the moving mechanism, a flow rate controlling device provided in the gas supply line and flow rate controlling devices provided in the local exhaust lines. The flow rates of the flow rate controlling devices are monitored and controlled to control the inside pressure of the load lock chamber to be slightly higher than the atmosphere pressure, thereby preventing the backward flow from the vent line.
    Type: Application
    Filed: March 7, 1997
    Publication date: August 8, 2002
    Inventor: MITSUHIRO HIRANO
  • Patent number: 6423103
    Abstract: First, an anode lead is led out of an anode member. Next, a dielectric film is formed at a surface of the anode member by anodic oxidation to form a capacitor element. Thereafter, a water-repellent agent is applied on a predetermined position of the anode lead. In succession, the capacitor element is immersed in an oxidant solution of a mixture solvent of alcohol and water, followed by drying. The capacitor element is then immersed in an alcoholic solution of a conductive polymeric monomer to polymerize a conductive polymer electrolyte on a surface of the capacitor element by chemical oxidation.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: July 23, 2002
    Assignee: NEC Tokin Toyama, Ltd.
    Inventors: Kenji Araki, Yuuji Aoki, Daisuke Takada, Kenichi Takahashi
  • Patent number: 6423104
    Abstract: A length of metallic lead from having anode terminals and cathode terminals integrally formed with each other extends between upper and lower molds of an apparatus for manufacturing tantalum solid electrolytic capacitors. The cathode terminals are first coated with a thermosetting conductive adhesive, and cathode layers of capacitor elements are then placed on the conductive adhesive. Thereafter, anode leads extending outwardly from the capacitor elements are placed on the anode terminals are joined thereto, respectively, by welding. A pressure is applied to the capacitor elements so that a portion of the conductive adhesive is squeezed out from one surface of each of the plurality of capacitor elements to a neighboring side surface thereof The cathode terminals are then joined to the capacitor elements, respectively, by heat-curing the conductive adhesive, and the capacitor elements are finally covered with a sheathing resin.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: July 23, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Omori, Yoshitsugu Uenishi, Osamu Tomita, Nario Kawakita, Masakuni Ogino, Yoji Masuda, Tsuyoshi Yoshino
  • Patent number: 6409775
    Abstract: A hoop metal lead frame (1) having, solid electrolytic capacitor elements (5) on its terminal sections (2) is provided with a crosspiece (3) bridging both sides in terms of the width direction disposed along the length direction in a region between the capacitor elements (5), one crosspiece for two capacitor elements (5). The metal lead frame (1) is placed on a molding die so that the region without having the crosspiece is locating at the sub runner (8), which has branched out from the main runner (7). The capacitor elements (5) are encapsulated with a molding resin injected through the sub runner (8). Since the molding resin is not covering the crosspiece (3), the main runner portion (7) and the sub runner portion (8) can be severed from the metal lead frame (1) without effecting unwanted stress on the solid electrolytic capacitors (10). The solid electrolytic capacitors (10) thus manufactured have a superior property in the tight hermetic sealing.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: June 25, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masatoshi Tasei, Kenji Kuranuki
  • Patent number: 6409777
    Abstract: A conductive high polymer layer as an electrolyte is formed on the entire surface of fine pores of a dielectric oxide layer of an anode electrode having an undulated surface of fine pores or the like. As a result, a solid electrolytic capacitor having characteristics such as capacitance, impedance, and leak current exactly as designed will be obtained. It comprises a manganese dioxide layer composed of a porous sinter of valve metal or roughened meal foil, placed continuously on the entire surface of the undulated surface of a dielectric oxide layer of an anode electrode having an undulated surface, a conductive high polymer layer formed by electrolytic polymerization, in contact with the surface of the manganese dioxide layer, and a cathode electrode placed on this conductive high polymer layer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: June 25, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Kobatake, Yukihiro Nitta, Kazuyo Saito
  • Patent number: 6334879
    Abstract: A sealed capacitor, which may be hermetic, having a generally flat, planar geometry, is described. The capacitor includes at least one electrode provided by a metallic substrate having a capacitive material contacted thereto. The coated substrate can provide at least one of the casing side walls itself or, be connected to the side wall. A most preferred form of the capacitor has the conductive substrate provided with the capacitive material formed from an ultrasonically generated aerosol.
    Type: Grant
    Filed: March 18, 1999
    Date of Patent: January 1, 2002
    Assignee: Wilson Greatbatch Ltd.
    Inventors: Barry C. Muffoletto, Rodney E. Stringham, Neal N. Nesselbeck, Ashish Shah, Donald H. Stephenson