Abstract: A method, a device, and an electronic apparatus for scan signal generation are provided. The method includes acquiring an initial clock signal, processing the initial clock signal to generate a plurality of target clock signals, encoding the plurality of target clock signals according to a predetermined logic relationship to generate a plurality of ordered logic signals, decoding the plurality of ordered logic signals, and generating a plurality of scan signals according to a decoding result.

Abstract: The present invention relates to an analysis of a waveform of a signal. A waveform of the signal is divided into multiple sections and a signal integrity identifier is assigned to each section. Accordingly, a representation of the respective signal integrity identifier may be provided for each section of the waveform. The representation of the signal integrity identifier may comprise an abstract representation, for example a graphical element, an alphanumeric element, a color or even an audio signal.

Abstract: Systems and methods may provide for determining a start time for an output image scanner to begin scanning an output image to a display device, determining a processing start time for each row of blocks of image pixel data within a rasterizer to ensure its completion before each row of blocks of image pixel data within the output image begin to be scanned out, and scheduling the start of processing of each row of blocks of image pixel data. In one example, the start time for the rasterizer to process a row of blocks of image pixel data uses the number of graphical objects to rendered into the output image and the processing times required by prior images.

Abstract: This specification discloses methods and systems for implementing a chip integrated scope (i.e., chip scope (CS)), which is a feature that allows a user to scope RF signals (internally and externally to the DUT (device under test)), by using the RF receive path (including amplifier, filter, ADC, DSP) to capture and store signal traces. In some embodiments, this specification discloses methods and systems to enhance the sampling rate and resolution of these signal traces by using subsampling techniques where a post-processing merges the subsampled traces (with different phase-shifts of say, for example, 0°, 90°, 180°, and 270°) into a single trace that will appear to have a sampling rate that is higher than a pre-determined sampling rate used to collect these subsampled traces.

Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.

Abstract: Various embodiments relating to controlling ambient environmental conditions to affect one or more human subjects wearing wearable computing systems are disclosed. In one example, a head-mounted computing system includes a see-through display configured to present an augmented reality image in front of an environment when viewed through the see-through display, a logic subsystem, and a storage subsystem. The storage subsystem may hold instructions executable by the logic subsystem to present the augmented reality image via the see-through display, and during presentation of the augmented reality image, send a command to control an environmental control system external to the head-mounted computing system. The command may be configured to trigger adjustment of an environmental parameter of the environment to enhance presentation of the augmented reality image.

Abstract: An oscilloscope includes at least one demonstration signal generator integrated as part of the oscilloscope. The demonstration signal generator generates stimulus signals that consist of digital samples of various different stored waveforms without the need of a separate demonstration board or signal source. The demonstration signal generator may loop through different sections of the stored waveforms to generate respective stimulus signals that include sequences of digital samples from the different waveforms in combination, to provide a broad range of stimulus signals. The stimulus signals may be displayed on the oscilloscope or output from the oscilloscope as demonstration mode stimulus signals to demonstrate the capabilities of the oscilloscope to customers or for training.

Abstract: Sensor information is regularly acquired from a plurality of sensors and stored. For each of the sensors, other sensors whose information is correlated are selected. When sensor information of a sensor is requested from an application program or the like, while if the requested sensor is available the sensor information is acquired directly from the sensor, if the requested sensor is unavailable the sensor information of sensors relevant to the sensor is acquired and the sensor information of the requested sensor is estimated. As a result, in a system comprising a plurality of sensors, sensor information of an unavailable sensor will be estimated in a short period of time.

Abstract: An integrated circuit includes a first signal line, a first circuit, a second signal line, and an attaching circuit. A first signal is transferred via the first signal line. The first circuit is connected to the first signal line and performs image processing upon the first signal being transferred thereto. The second signal line is connected to the first signal line, and a second signal indicating that the first signal has been transferred is transferred via the second signal line. The attaching circuit is connected to the second signal line and attaches, upon the second signal being transferred thereto via the second signal line, information corresponding to the second signal to an image resulting from the image processing performed by the first circuit.

Abstract: A semiconductor device in which variations are controlled is provided. The semiconductor device has a function of converting a digital signal into an analog signal, and includes a digital-analog converter circuit, an amplifier circuit, first to fourth switches, a first output terminal, a second output terminal, and a power source. The amplifier circuit is configured to perform feedback control when the first switch and the fourth switch are on and the second switch and the third switch are off. The amplifier circuit is configured to perform comparison control when the first switch and the fourth switch are off and the second switch and the third switch are on; utilizing this, variations in the digital-analog converter circuit and the amplifier circuit are controlled.

Abstract: A method generates an asynchronous trigger signal in a position-measuring device having a position-sensing unit, a processing unit and an interface unit. The position-measuring device is connectable via the interface unit and a bidirectional data channel to subsequent electronics for communication purposes. A synchronous data stream is generated from an asynchronous data stream arriving at the position-measuring device from a direction of the subsequent electronics by sampling the asynchronous data stream in a time pattern of a clock signal. A gate signal is generated upon an enable condition for outputting the trigger signal being detected by evaluating the synchronous data stream. The asynchronous trigger signal is generated upon the gate signal being present and a signal edge of the asynchronous data stream occurring.

Abstract: Apparatuses, systems, and methods that provide a delayed output signal with reduced sampling error are described. Embodiments include a clock circuit that generates a sample clock signal having a predetermined sample clock period. A sampling circuit may generate samples of a received signal during each sample clock period. An interpolation circuit may estimate a value of the received signal at times between the samples of the received signal based on at least a first sample and a second sample of the received signal. The interpolation circuit may estimate a time that the received signal crosses a threshold, and determine a time delta between the first sample and the estimated time that the received signal crosses the threshold. A delay circuit to generate a time delay substantially equal to the time delta is also included. An output signal changes state after the generated time delay.

Abstract: A method for driving a display apparatus and a display apparatus are provided. With the method for driving a display apparatus according to the present disclosure, the gate driver circuit, the source driver circuit and the reference voltage generation circuit are controlled not to output any signal during an interval between display of two frames of pictures, so as to solve the problems that a gate driver circuit and a source driver circuit in the existing display apparatus have large power consumption, and operate at an excessive high temperature.

Abstract: An apparatus and method of controlling a motion of an object on a touch screen of a device including recognizing pressures at least two positions on the touch screen of the device, and controlling a motion of the object on the touch screen using a difference in pressure between the at least two recognized positions.

Abstract: Embodiments of the invention include a subtitling format encompassing elements of enhanced syntax and semantic to provide improved animation capabilities. The disclosed elements improve subtitle performance without stressing the available subtitle bitrate. This will become essential for authoring content of high-end HDTV subtitles in pre-recorded format, which can be broadcast or stored on high capacity optical media, e.g. the Blue-ray Disc. Embodiments of the invention include abilities for improved authoring possibilities for the content production to animate subtitles. For subtitles that are separate from AV material, a method includes using one or more superimposed subtitle layers, and displaying only a selected part of the transferred subtitles at a time. Further, colors of a selected part of the displayed subtitles may be modified, e.g. highlighted.

Abstract: Bay RAM Five is a very high-speed solid-state data storage device with 4 independently controlled banks of 4 DDR3 SO-DIMM sockets per bank, 4 industry-standard SATA data connectors, and one 12V input DC power connector, all housed within an enclosure compatible with 5.25? drive bays found in common PC chassis. The 4 controllers are independently switched with jumper blocks, allowing backward- and forward-compatibility with SATA chipsets and add-on controllers transmitting data at various speeds. A separate jumper switches the device's firmware from the 8 b/10 b “legacy frame” to the 128 b/130 b “jumbo frame” now in the PCI-Express 3.0 specification. The 5.25? enclosure has room for 3 40×40 mm cooling fans, either 20 mm or 10 mm thick: fans are powered by 3 fan headers integrated onto the PCB, or a separate power supply installed in the PC chassis.

Abstract: Embodiments of the invention include devices and methods for searching IQ-based time-domain traces for events, marking the events, and analyzing intervals of interest at or around the events on a display unit of a test and measurement instrument. The test and measurement instrument can include an input terminal to receive an RF signal, an ADC to digitize the RF signal, a digital downconverter to produce I (in-phase) and Q (quadrature) baseband component information from the digitized RF signal, an acquisition memory to acquire and store a record, a trace generation section to generate one or more IQ-based time-domain traces, and a search unit to scan the IQ-based time-domain traces for one or more events. The search unit can locate and mark the events for display on a display unit of the test and measurement instrument.

Abstract: Device for correcting the line and/or frame fields of a deflector for cathode ray tube comprising: a current sensor for evaluating the value of a line current Il a series of comparators intended to compare the value of the line current Il with reference values a current sensor for evaluating the value of the frame current It an analogue/digital converter for converting the analogue value of the frame current a programmed correction memory which is addressed by the output signals from the comparators and from the analogue/digital converter so as to deliver to at least one digital/analogue converter, data which are dependent on the addressing signals a low-pass filter for filtering the output of the digital/analogue converter at least one correction coil for correcting the deflection fields of the deflector, and generating a correction field as a function of the output value from the low-pass filter.

Abstract: In a circuit and method of controlling the horizontal and vertical screen sizes of a cathode ray tube (CRT) monitor, the circuit includes a horizontal screen size compensation circuit, an east-west correction signal controller, a vertical screen size compensation circuit, and a vertical screen size correction signal controller. The horizontal screen size compensation circuit compares the voltage value of a horizontal screen size correction signal with the voltage value of a horizontal reference voltage to obtain first and second horizontal current signals. In response to a horizontal control signal, the horizontal screen size compensation circuit outputs a horizontal correction current signal obtained by subtracting a horizontal variable current signal from the first horizontal current signal.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: A power supply for a video display tube includes a deflection transformer with a primary winding powered with a scan voltage which has a first value when displaying signal according to a first video standard and a second voltage when displaying video according to a second standard. A secondary winding of the transformer produces filament voltage for the display tube. A variable coupler couples the filament voltage to the filament of the picture tube in an amount established by a control signal. A memory produces a first control signal in response to the first scan voltage and a second control signal in response to the second scan voltage. The first and second control signals are selected so that the voltage coupled from the transformer to the filament is the same at both scan voltages.

Abstract: A display interface is arranged to processes analog input signals to provide digital output signals. The display interface includes a series of programmable current sources, an input buffer circuit, a first reference buffer circuit, a second reference buffer circuit, and an analog-to-digital converter. The programmable current sources are arranged to provide first and second reference signals, which are buffered by reference buffer circuits and provided to the analog-to-digital converter. The input buffer circuit provides a buffered input signal to the analog-to-digital converter, and operates in an open-loop configuration for improved operating speed. The analog-to-digital converter is configured to provide a digital output signal (DOUT) in response to the buffered input signal. The analog-to-digital converter includes gain and offset settings that are changed by adjusting the progranmnable current sources. The programmable current sources and reference buffer circuits are outside of the input signal path.

Abstract: A convergence correction circuit including a coordinate unit which sets a predetermined range with first level values according to a screen length; an interval unit which divides the screen length; an interval decoder which calculates the value of the branch point of each interval determined by the interval unit; an interval gain unit which stores the gain of each interval; a subtracter which subtracts the output of the coordinate unit from the output of the interval decoder; a multiplier which multiplies the output of the subtracter by the output of the interval gain unit; a level shifter which sets an initial and last value of each interval upon horizontal scanning; an adder which adds the output of the multiplier and the output of the level shifter; a digital-analog converter which converts the output of the adder; and a correction coil which corrects the convergence according to the converted output.

Abstract: There is disclosed a vertical deflection circuit for use in a display device employing a CRT. The vertical deflection circuit has a DSP (digital signal processor) for producing a digital current signal during each main period. This digital current signal shows plural current values which increases in first equal increments from a different value during each main period. The digital current value is converted into an analog current signal by a D/A converter and then averaged by a low-pass filter. A vertical deflection current is produced based on the averaged analog current signal. Because plural different current values are averaged, the average value varies linearly. Accordingly, the vertical deflection current varies linearly with each main period.

Abstract: Methods and apparatus are provided for equally aging a cathode ray tube (CRT). A video input terminal is coupled to the CRT and receives an external video signal. Control circuitry is provided, which detects the aspect ratio of the signal and determines whether there is a mismatch between the signal aspect ratio and an aspect ratio of a display screen in association with the CRT. If a mismatch between the signal aspect ratio and the screen aspect ratio exists, an equalization video signal is derived from the external video signal. A primary region of the CRT is illuminated in response to the external video signal, and a secondary region of the CRT, which would otherwise be unilluminated in response to the external video signal due to the mismatch between the signal aspect ratio and the screen aspect ratio, is illuminated in response to the equalization video signal. In this manner, the CRT is uniformly aged.

Abstract: A scanning system for a film recorder utilizes multiple digital-to-analog converters (DACs) to produce a linear output for a vertical deflection circuit which drives a vertical yoke circuit for controlling a CRT beam in a film recorder. The system contains a coarse DAC, a fine DAC, and a delta DAC which provides a signal representing the analog change from line to line. A summing circuit, a difference amplifier, a A/D converter, and a calibration sequence controlled by a DSP create a table to effectively increase the resolution and linearity of the deflection output signal.

Abstract: A scan frequency detector is responsive to a horizontal synchronization signal to generate a data signal that is indicative of the horizontal scan frequency. A digital-to-analog (D/A) converter produces from the data signal an analog, output signal at a first level, when the horizontal frequency is within a first range of values, at a second level, when the horizontal frequency is within a second range of values and at a third level, when the horizontal frequency is within a third range of values. A first switch of a switched S-capacitor arrangement, is turned on, when the output signal is at the first level. The first switch and a second switch of the switched S-capacitor arrangement, are turned on, when the output signal is at the second level. Both the first and second switches are turned off, when the output signal is at the third level. The third and second levels are distinguished by a level detector that includes a zener diode.

Abstract: A digital convergence correction device converts correction data into serial data by using a parallel/serial converter, and further converts the serial data into an analog correction signal by using a serial input type digital/analog converter, and outputs the analog correction signal in order to correct misconvergence.

Abstract: An image display device (1) which includes a cathode ray tube is provided with a cathode system (2) for the emission of a plurality of electron beams (3) whereby a phosphor screen (4) is scanned in order to display an image. The electron beams are modulated on the basis of an electronic image signal by means of a cathode modulator (5). The cathode modulator is arranged to scan different image lines simultaneously by means of separate electron beams. For example, the cathode modulator comprises an extension system (7) and a delay system (8) for deriving extended and delayed extended image line sections from image line sections of the electronic image signal. The cathode modulator also comprises a combination unit (9) for simultaneously supplying an extended image line section and a delayed image line section with which separate electron beams are modulated.

Abstract: A side pincushion control apparatus for compensating for a horizontal picture size control voltage and a side pincushion in a monitor. The apparatus compensates for the horizontal picture size control voltage and the side pincushion of the picture using a microcomputer, so that the picture is prevented from being unstable during the side pincushion compensation.

Abstract: A new sampling technique for waveform measuring instruments (including methods and circuits for implementing same) comprises the step of processing a series of digital signal samples through a decimator to extract a decimated sample value from each decimated sample interval in a series of decimated sample intervals. The series of digital signal samples is simultaneously processed through a digital peak detector to extract maximum and minimum values (peak detect sample values) from each decimated sample interval. For a given decimated sample interval, a difference between the maximum and minimum sample values for the interval is calculated. If the difference exceeds a glitch detect threshold value, the maximum and minimum sample values for the given decimated sample interval are transferred to a video sample memory. If not, the decimated sample value for the given decimated sample interval is transferred to the video sample memory.

Abstract: A parabolic-wave shaping circuit for focus-correction which can output only the necessary part of a parabolic-waveform for focus-correction is constructed so as to clip an output waveform of an output amplifier amplifying a parabolic-wave having a horizontal scanning period for a period of a blanking time of a video signal with a clipping circuit composed of a diode and a variable voltage-regulating resistor for adjusting the clipping level.

Abstract: A periodic signal is produced by counting pulses of a clock during a given period of time. The number of pulses counted is divided by a whole number. A count is then made of the number of pulses of this clock whose number corresponds to the quotient of this division. At each batch, a value of a periodic signal is produced.

Abstract: A vertical deflection waveform generating apparatus is provided to have a memory in which a function of a vertical deflection waveform is previously stored. The function is a function with an order of horizontal scanning lines in which linearity of a raster is corrected as a parameter. The vertical deflection waveform generating apparatus generates a vertical deflection waveform by a digital signal processing circuit substituting a scanning order of the next scanning line in the parameter of the function, and sequentially outputting vertical deflection voltage at each time of detection of a horizontal synchronizing signal. Further, in order to reduce raster moire, timing for generating the vertical deflection waveform is offset for each frame.

Abstract: A display device often includes a correction circuit for correcting a position error which is caused by the fact that the deflection signals are not (any longer) in conformity with the video signals to be displayed. This is caused, inter alia by the fact that the deflection coils and the display tube are not ideal. By providing the display device with a waveform generator generating a (line deflection) reference signal and by causing this reference signal to traverse the same "signal path" as the video signal, variations in the delay etc. can be corrected. Both the video signal and the reference signal are stored in a memory and read from the memory under the control of the correction circuit. Inputs of the correction circuit receive the (line deflection) reference signal delayed via the memory and a signal related to the (real) line deflection. With reference to these input signals, the correction circuit applies a (read) clock signal to the memory.

Abstract: A display apparatus for displaying a video image operates with plural horizontal scanning frequencies. The apparatus includes a horizontal scanning frequency oscillator for generating a signal in synchronism with a horizontal synchronous signal of an input video signal; and a control unit for controlling a frequency of an output of the horizontal scanning frequency oscillator corresponding to the horizontal synchronous signal of the input video signal. A multi-scan video monitor may be provided for displaying the image relative to any of the plural horizontal scanning frequencies without any turbulence.

Abstract: A deflection apparatus comprises a deflection amplifier coupled to a deflection waveform modulation circuit such as a diode modulator. An East-West modulation signal is generated by a digital to analog convertor in accordance with a reference potential coupled thereto. The modulation signal has a DC component for width control, and is coupled to an input of a comparator. The reference potential is also coupled to an input of the comparator to establish a reference bias therefor. The comparator has an output coupled to the deflection waveform modulation circuit to provide the East-West modulation.

Abstract: A display device comprising a CRT having a reduced number of components for automatic cutoff adjustment. The device needs an IC having a less number of connection pins. The device adds reference pulses to given portions within every field of video signals. The resulting cathode currents are converted into voltage pulses. These voltage pulses are compared with a reference voltage by a comparator. The output signal from this comparator is counted by forward-backward counters for three primary colors, respectively, and converted into analog form. Level shift circuits for the three primary colors, respectively, control the DC components of the video signals according to the output signals from the D/A converters. In this way, the cutoff characteristics of the CRT are controlled.

Abstract: To avoid burn in a scanning cathode ray tube, the address of the scanning spot at each clock period is recorded in a memory. During each frame period, the logarithms of the number of occurrences of each address are fed to a peak detector. The peak value is used to determine a maximum allowable beam current for the next frame. In another embodiment, the number of occurrences of each address during a line period is monitored and if this number exceeds a given number the CRT is blanked.

Abstract: A raster distortion correcting signal synthesizer includes a multiplier, an adder, a memory for storing data and a coefficient, and a controller for controlling the multiplier, adder and memory in accordance with a count value of a horizontal sync. signal. The controller calculates a desired raster distortion correcting signal of a high order by utilizing the multiplier and adder on the basis of the count value, and multiplies the count value by a predetermined coefficient to obtain a new count value.

Abstract: An image correction device includes a memory (70) for storing correction data, an address generator (15,31) for supplying addresses to the memory, a regulation pattern generator (40), a DA converter (71) for converting an output of the memory into an analog signal, convergence yoke (CY) coils (74), CY drive amplifiers (73) for converting the analog signal into current for driving the CY coils, a CPU (20) for controlling operation of the image correction device, deflection current detection circuits (10,11) for reading vertical and horizontal deflection currents in the CPU and a memory (60) for storing correction data and deflection currents.

Abstract: Disclosed is a system having a memory mapped deflection to control the position of an electron beam within a CRT used to project a color image onto a photographic medium for printing. A horizontal position counter is incremented at a linear rate, and the counter value is translated, using a translation table stored in memory, into a current used to drive the yoke of the CRT. The translation introduces non-linearities into the output voltage which results in a linear forward sweep across the CRT. A sweep direction signal is used as an address bit of the translation table, to allow an optimized retrace motion profile which results in an improved linear beam motion across the face of the CRT during the forward sweep immediately following retrace.

Abstract: A data display apparatus with a function for correcting the effect of external magnetic field including a display, a driving circuit for driving the display, an adjuster for adjusting a display position of input signal, a detector for detecting an output voltage of the driving circuit, and a difference detection circuit. The difference detection circuit detects a difference between an output of the detector when a predetermined reference signal is inputted as the input signal and an output of the detector when a display position of the predetermined reference signal is adjusted to a reference position on the screen of the display by the adjuster. The difference is stored in a memory as calibration data for correcting the effect of external magnetic field or the like.

Abstract: The free-running frequency of a bus controlled horizontal oscillator is adjusted by programming of a first data signal that is coupled to a digital-to-analog converter. The programming causes the first data signal to be non-alterable. The programming is done during manufacturing of a wafer that includes the oscillator. A second data signal that is coupled from a microprocessor via a bus and via a second analog-to-digital converter to the oscillator can vary the oscillator free-running frequency to provide for tolerance compensation. The first data signal is immune against data errors. The second data signal is not immune against data errors, but can vary the oscillator frequency within only a relatively narrow range of values. Consequently, data errors are prevented from causing a significant change in the oscillator free-running frequency that might have occurred had both data signals been alterable.

Abstract: A remote registration and calibration system for a hybrid video display. The registration and calibration functions are performed by a computer. Display mounted switches are advantageously employed. The computer system samples the state of an array of switches and then performs calibration functions based on the state of the switches.

Abstract: The digital convergence correction device is used for a projection-type television receiver having a Braun tube with an aspherical surface fluorescent screen and a projection lens system with an aspherical surface plastic lens attached to the display screen of th Braun tube. In the digital convergence correction device, a digital memory stores digital correction data corresponding to correction values at the convergence adjustment points on the display screen that is divided in the horizontal and vertical directions. A multiplexer reads the digital correction data out of the digital memory, and implements the time division multiplexing for the data. A D/A converter receives the multiplexed data from the multiplexer, and converts it into an analog signal. The device is provided with sample-holding circuits for making coincident timing for the outputs of the time division multiplexing process, so that no phase shift arises at the time division process and multi-channel time division process is made possible.

Abstract: A compensation arrangement for a display system that adaptively compensates the display parameters thereof for each pixel position to provide a precise display image that automatically adapts to the scan rate and aspect ratio of its sweep circuit. The sweep signals are sensed directly to define the actual instantaneous scan position. The sweep position is used to generate a compensation parameter for compensating the display signals. In a preferred embodiment, a lookup table is used to store compensation parameters, a compensation parameter is accessed from the table in response to the sweep signals, and the accessed compensation parameter is used to compensate the display signals.

Abstract: Methods and apparatus for providing pixel brightness correction in monitors. The methods and apparatus disclosed herein provide significant cost reductions in gamma correction circuitry by first degamma correcting pixel value data stored on a frame buffer, and then gamma correcting the degamma corrected pixel value data before the data is stored back on the frame buffer. Circuits for providing pixel brightness correction in a monitor comprise logic circuits for generating upper bits of a data word representing pixel intensity, shifter circuits interfaced with the logic circuits for generating lower bits of the data word representing pixel intensity, and combining circuits interfaced with the logic circuits and the shifter circuits for generating intermediate bits of the data word representing pixel intensity.

Abstract: The invention relates to a device for the optical recording of rapid proceses with a TV camera, which comprises means for deviating and suppressing the beam, in order to make the scanning beam run successively and cyclically over N lines of a picture plane on which the processes are projected.A cyclic line counter (14) carries out one counting step for each line pulse and supplies a counting end pulse after p line pulses respectively, N/p being in integer >>1.The end-of-count pulse is applied to the beam suppression circuit (13) of the TV camera (1) for the picture beam suppression and to a sawtooth generator (12), which controls the vertical deviation (4) of the beam.

Abstract: A convergence correction circuit according to the present invention has a phased locked loop including a programmable counter. The programmable counter has programmable count start and end points. The output of the programmable counter is supplied to a memory storing convergence distortion correcting data therein. As the horizontal screen size is increased, a value closer to the lower limit 0 of the start point as compared with that taken when the horizontal size is small is set as the count start point of the programmable counter, and a value closer to the upper limit (2.sup.7 -1) of the end point as compared with that taken when the horizontal size is small is set as the count end point. In accordance with the horizontal screen size, the count start and end points of the programmable counter are changed. Correct convergence correction is performed even if the horizontal screen size is changed.