Abstract: A power management circuit is disclosed that includes a boost converter, a pass transistor, and an overcurrent detect circuit. The boost converter is configured to convert an input voltage into a first power supply voltage. The pass transistor is configured to transfer the first power supply voltage as a second power supply voltage after a predetermined time from a time point at which the first power supply voltage is activated. The overcurrent detect circuit is configured to perform an overcurrent detect operation by sensing a current flowing through the pass transistor. A display device is also disclosed that includes the power management circuit.

Abstract: An electrostatic discharge (ESD) circuit includes an ESD detection circuit, a clamp circuit and an ESD assist circuit. The ESD detection circuit is coupled between a first and a second node. The first node has a first voltage. The second node has a second voltage. The clamp circuit includes a first transistor having a first gate, a first drain, a first source and a first body terminal. The first gate is coupled to at least the ESD detection circuit by a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node, and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

Abstract: Disclosed is a voltage regulator, which makes a low dropout regulator stop working by controlling a sampling circuit of the low dropout regulator to break in a sleep mode, and makes an output voltage of the low dropout regulator follow an output voltage of a first bias voltage generating circuit by using a first MOS transistor connected between an voltage input end and an voltage output end of the low dropout regulator in a source follower structure, and is capable of controlling an output voltage of the whole voltage regulator by a generated bias voltage applied to the first bias voltage generating circuit by a first bias current source.

Abstract: The disclosure relates in some aspects to electrostatic discharge (ESD) protection for an electronic circuit. In some aspects, the ESD protection includes a buffer circuit that increases the slew rate of a signal that controls a discharge circuit. In some aspects, the ESD protection includes a voltage-dependent resistance circuit that adjusts a time constant of a resistive-capacitive filter based on a voltage on a supply node.

Abstract: A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.

Abstract: A power supply modulator includes: a linear regulator; a switching regulator; and a mode-based connection circuit. The mode-based connection circuit includes a coupling circuit configured to drop an output signal of the linear regulator by a target coupling voltage in an envelope tracking (ET) modulation mode; and a coupling voltage management circuit configured to monitor a coupling voltage of the coupling circuit in another modulation mode, and selectively apply a voltage to the coupling voltage based on a monitoring result such that the coupling voltage is maintained at the target coupling voltage.

Abstract: Systems and methods are provided and include a charging circuit, a converter network, and a voltage regulator. The voltage regulator couples the charging circuit to the converter network. When the system is in the charging mode, the charging circuit is configured to receive a serial communication signal that charges the charging circuit. When the system is in the communication mode, the voltage regulator is configured to limit an amount of voltage discharge from the charging circuit, and the converter network is configured to receive the serial communication signal and convert the serial communication signal to a second signal having a second type. The second type has a different communication protocol than the serial communication signal. When the system is in the communication mode, the converter network is configured to transmit the second signal to a remote device.

Abstract: A power supply modulator includes: a linear regulator; a switching regulator; and a mode-based connection circuit. The mode-based connection circuit includes a coupling circuit configured to drop an output signal of the linear regulator by a target coupling voltage in an envelope tracking (ET) modulation mode; and a coupling voltage management circuit configured to monitor a coupling voltage of the coupling circuit in another modulation mode, and selectively apply a voltage to the coupling voltage based on a monitoring result such that the coupling voltage is maintained at the target coupling voltage.

Abstract: Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Abstract: A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes.

Abstract: A floating core network for secure isolation of a circuit from an external supply interface is described. Isolation of a core is accomplished through a dynamic current limiting network providing an isolated core voltage to the core; and an isolated supply for the corresponding core that is continuously recharged by the dynamic current limiting network. The dynamic current limiting network can include two control loops, one control loop providing a fixed gate voltage to a p-type transistor supplying current to the isolated supply and another control loop providing a fixed gate voltage to an n-type transistor sinking current from the isolated supply.

Abstract: An object of the disclosure is to provide cancelling of the output voltage deviation in a switching converter, caused by Equivalent Series Inductance (ESL) of the output capacitor, using switching node information. A further object of the disclosure is to eliminate a step-like voltage deviation in the equalized output, further eliminating the need to increase the Panic comparator offset reference, and eliminating the need to reduce the bandwidth of the pulse-width modulation control loop. Still further, another object of the disclosure is to merge some of the new components depending on the circuit topology. Still further, another object of the disclosure is to implement the new components with the same silicon as the control block, for matching the output voltage ripple and the cancelling signal control.

Abstract: The present invention relates to an electric discharge machining device. The electric discharge machining device includes: a first switch provided between the positive pole of a power supply and a work piece; a second switch provided between the negative pole of the power supply and the work piece; a third switch provided between the negative pole of the power supply and a tool electrode; a fourth switch provided between the positive pole of the power supply and the tool electrode; and a pulse generating device. In order to supply current pulses with a straight polarity, the pulse generating device repeatedly switches on and off either the first or third switch while the other switch is on. In order to supply current pulses with a reverse polarity, the pulse generating device repeatedly switches on and off either the second or fourth switch while the other switch is on.

Abstract: In accordance with an embodiment, a low dropout voltage regulator includes an error amplifier connected to an output driver. The error amplifier has an output connected to an input of the output driver and an input connected to an input of the output driver. The output driver has an input coupled for receiving an input signal. In accordance with another embodiment, a method for regulating a voltage is provided that includes operating a voltage regulator under control of an output voltage regulation loop in response to the voltage regulator not being in a low dropout region. The voltage regulator is operated under control of a quiescent current regulation loop in response to the voltage regulator being in a low dropout region.

Abstract: A floating output power supply includes circuitry for indirectly sensing an output current and output voltage of the floating output power supply. The circuitry includes a circuit ground referenced current sensing resistor placed in between diodes forming one leg of a full wave rectifier. The voltage of this current sensing resistor is circuit ground referenced and representative of an output current of the floating output power supply. A resistive network is coupled between a negative output and a positive output of the floating output power supply. The resistive network includes a circuit ground referenced resistor whose voltage is representative of the output voltage of the floating output power supply. A controller of the floating output power supply determines output voltage, current, and/or power from these sensed voltages and currents and adjusts an operating parameter of an input power supply as a function of the determined output voltage, current, and/or power.

Abstract: Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor based on a resistance of a shunt path of the transistor relative to the size of the antenna and the size of the transistor. The method also includes comparing the determined figure of merit to a limit. The method further includes deeming the transistor to pass the antenna rule when the figure of merit is less than the limit, and deeming the transistor to fail the antenna rule when the figure of merit is greater than the limit. The determining and the comparing are performed by a computer device.

Abstract: Provided is a voltage regulator configured to suppress overshoot and undershoot so as to output a stabilized voltage. The voltage regulator includes: a high pass filter configured to detect a fluctuation in power supply voltage; a high pass filter configured to detect a fluctuation in output voltage; transistors connected in series, which are each configured to cause a current to flow in accordance with an output of corresponding one of the high pass filters; and a clamp circuit configured to clamp a drain voltage of one of the transistors connected in series. The voltage regulator controls a gate voltage of an output transistor based on a drain voltage of a transistor that includes a gate controlled by the drain voltage of the one of the transistors connected in series.

Abstract: Multi-stage amplifiers which provide a constant output voltage subject to load transients are presented. The amplifier has a pass device to source a load current at an output voltage. The amplifier has a first driver circuit to control the pass device based on a reference voltage and based on a first feedback voltage. The amplifier has a sink transistor to sink a first current from the output node to a low potential. Furthermore, the amplifier comprises a bypass transistor configured to couple a sense voltage, to sink a second current from the output node to the low potential. There is a second driver circuit to control the sink transistor and the bypass transistor, based on the reference voltage and based on a second feedback voltage. A voltage divider derives the first feedback voltage, the second feedback voltage and the sense voltage from the output voltage.

Abstract: An insulated state detection device includes a positive-side input terminal, a negative-side input terminal, a ground electrode, a ground fault resistance value calculation unit, a measuring state identification unit, a timing information generation unit that generates a timing information, automatically updates a value of the timing information by a predetermined value each time the ground fault resistance value calculation unit generates a new insulation resistance value, and reflects a state of the identification of the measuring state identification unit on the value of the timing information, and an information transmission unit that transmits the insulation resistance value calculated by the ground fault resistance value calculation unit and the timing information generated by the timing information generation unit to a host control device.

Abstract: An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

Abstract: A power supply circuit includes a first circuit connected to a first line, to which a power supply voltage is applied, and a second line, and a power supply clamp circuit connected to the first and second lines. The power supply clamp circuit includes a current path circuit which connects the first and the second lines to each other, and a control circuit which outputs a control signal to the current path circuit. The current path circuit includes a transistor and a diode group. The power supply clamp circuit is driven during a period in which a first voltage is applied to the first line and controls a potential of the first line so as to become a potential lower than the first voltage.

Abstract: A power supply device includes a first converter which converts an input voltage to a first voltage, a second converter which converts the first voltage from the first converter to a second voltage, a voltage comparison section which compares the first voltage outputted from the first converter with a predetermined reference voltage, a voltage comparison result output section which outputs a first signal until the first voltage is determined to be higher than the predetermined reference voltage by the voltage comparison section and retains a second signal as an output after the first voltage is determined to be higher than the predetermined reference voltage, and a converter control section which controls the second converter to stop when the first signal is outputted from the voltage comparison result output section and controls the second converter to operate when the second signal is outputted from the voltage comparison result output section.

Abstract: An overshoot reduction circuit within a low dropout voltage regulator eliminates an overshoot at an output terminal resulting from a transient fault condition occurring at an input or output terminal. The overshoot reduction circuit monitors to sense if there is a transient fault condition occurring at the input or output terminal and provides a Miller capacitance at the output terminal of a differential amplifier of the low dropout voltage regulator to prevent the output of the differential amplifier from being discharged to ground during the transient. A control loop circuit balances current within an active load of the differential amplifier to clamp the output of the differential amplifier to its normal operating point. When the transient fault condition ends, the output voltage of the differential amplifier is set such that a pass transistor of the low dropout regulator responds quickly to resume the regulation to reduce or eliminate the overshoot.

Abstract: The reversal of the flow of output current in a voltage regulator is prevented by equipping the voltage regulator of a regulation transistor controlled by an analog voltage control, having its current terminals connected between the control terminal of the fifth transistor power of the regulator and the power supply line or the common ground node of the regulator. The regulation transistor is configured to provide an electrical path of conduction between the control terminal and the power supply line or the ground node and is controlled by an analog voltage control that varies in a continuous manner between a first level, suitable to extinguish the regulation transistor, and a second level suitable for biasing it in an operating condition of deep conduction, as the difference between the supply voltage and the regulated output voltage approaching an offset voltage.

Abstract: A regulator structure includes a first differential amplifier having a first input coupled to a reference voltage node. A second differential amplifier has a first input coupled to the output of the first differential amplifier. A third differential amplifier has a first input coupled to the output of the first differential amplifier. A first pmos transistor has its gate coupled to the second differential amplifier output, and its drain coupled to a second input of each of the first and second differential amplifiers. A second pmos transistor has its gate coupled to the third differential amplifier output, and its drain configured to output a regulated voltage which is also a second input of the third differential amplifier. A circuit is configured to replicate the regulated voltage and couple the replicated regulated voltage to the drain of the first pmos transistor.

Abstract: A low dropout (LDO) voltage regulator includes a scaling amplifier for receiving a bandgap voltage, Vbg, and outputting a scaled Vbg. A reference MOSFET device is included for reducing the scaled Vbg by a first voltage Vgs formed across gate and source nodes of the reference MOSFET device. This forms a reduced level of the scaled Vbg. An RC network filters the reduced level of the scaled Vbg and outputs a filtered voltage. An output buffer is included for receiving and increasing the filtered voltage by a second voltage Vgs in order to recover the scaled Vbg. The scaled Vbg is used as the desired regulated voltage output. The second voltage Vgs, which is produced by the output buffer, is equal to the first voltage Vgs, which is produced by the reference MOSFET device.

Abstract: In one general aspect, an apparatus can include a controller, and a power stage coupled to the controller and configured to be coupled to a power source. The power stage is configured to deliver an output voltage to a load module in response to the controller. The apparatus also includes a reference voltage circuit coupled to the controller and configured to be grounded to a first ground voltage different from a second ground voltage associated with the load module.

Abstract: A voltage generator includes a controllable voltage divider, a pull-up circuit and a first pull-down circuit. The controllable voltage divider is utilized for generating an output voltage at an output node of the controllable voltage divider according to a first reference voltage, a second reference voltage, and a control signal, wherein the second reference voltage is lower than the first reference voltage. The pull-up circuit is coupled to the output node of the controllable voltage divider and the first reference voltage, and is utilized for selectively connecting the first reference voltage to the output node of the controllable voltage divider. The first pull-down circuit is coupled to the output node of the controllable voltage divider and the second reference voltage, and is utilized for selectively connecting the second reference voltage to the output node of the controllable voltage divider.

Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

Abstract: A circuit comprises a cascode core circuit and a current adjustor circuit. The cascode core circuit has an output node and a current path (ID). The current adjustor circuit is configured to change a current on the current path in response to a change in a voltage at the output node. The cascode core circuit comprises a first transistor, a second transistor, and a third transistor. A first terminal of the first transistor is coupled to a second terminal of the second transistor and to a third terminal of the third transistor. A first terminal of the second transistor is configured as the output node. A first terminal of the third transistor is coupled to a third terminal of the second transistor. The current path is through the first terminal of the third transistor.

Abstract: A voltage regulator includes an output stage including a control terminal and a load path, with the load path coupled between the input terminal and the output terminal. The voltage regulator also includes a control circuit with an input stage, a first current mirror, and a second current mirror. The input stage includes a first control input configured to receive a first reference voltage, a second control input configured to receive a second reference voltage, a feedback input coupled to the output terminal, a first output terminal, and a second output terminal. The first current mirror includes a reference current path coupled between a first supply terminal and the first output terminal of the input stage, and an output current path coupled between the first supply terminal and the control terminal of the pass device.

Abstract: A method for operating an electric power generating system (EPGS) includes, in one aspect, detecting current limiting conditions in the SSPC, wherein the SSPC includes a main solid state switch in series with an output filter that includes a first solid state switch, and wherein a decoupling filter comprises a second solid state switch. Another aspect includes, based on the detection of the current limiting conditions in the SSPC, opening the first solid state switch and the second solid state switch; detecting an absence of current limiting conditions in the SSPC; and, based on the detection of the absence of current limiting conditions in the SSPC, closing the first solid state switch and the second solid state switch, and powering a direct current (DC) load by a generator of the EPGS via the output filter and the SSPC.

Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

Abstract: A power regulation scheme includes a first voltage regulation portion having a first voltage regulator, a second voltage regulator, and a switching system. The first voltage regulation portion is connected in parallel with a second voltage regulation portion. The second voltage regulation portion regulates an input voltage if an open condition occurs within the first voltage regulation portion. The switching system forces the second voltage regulator to regulate the input voltage if a short condition occurs within the first voltage regulator.

Abstract: A power source apparatus includes: a switch circuit to receive an input voltage; a control circuit to switch the switch circuit from a second state to a first state at a timing corresponding to a comparison result between a feedback voltage generated based on a first voltage corresponding to an output voltage and a reference voltage generated based on a standard voltage set in accordance with the output voltage; and a voltage generation circuit to add a compensation voltage generated by voltage-converting a time period in which the switch circuit switches from the second state to the first state to one of the first voltage and the standard voltage, to generate the feedback voltage, to add a slope voltage which changes at a slope to one of the first voltage and the standard voltage, and to generate the reference voltage.

Abstract: The present invention discloses an adaptive two-stage voltage regulator and a method for controlling the same. The adaptive two-stage voltage regulator includes: a voltage regulator for converting an input voltage (Vin) to a middle voltage (Vm), wherein Vin?Vin_max; a linear regulator for converting the middle voltage to an output voltage (Vout); and a middle voltage controller for adjusting the middle voltage according to (1) an input voltage indicator and one of (2a) an output voltage indicator and (2b) a predetermined reference signal, such that when Vin?Vout, Vm=Vout+?V and (Vout+?V)<Vin_max.

Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

Abstract: A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies.

Abstract: A power regulation scheme includes a first voltage regulation portion connected in parallel with a second voltage regulation portion that regulates a voltage if an open condition occurs within the first voltage regulation portion. Each voltage regulation portion may include a first voltage regulator connected in series with a second voltage regulator that regulates the voltage if a short condition occurs within the first voltage regulator. Each voltage regulation portion may utilize a switching element to route an output voltage of the first voltage regulator past the second voltage regulator if the output voltage has been regulated and/or to force the output voltage to be regulated by the second voltage regulator if the output voltage has not been regulated.

Abstract: The invention discloses a voltage regulating apparatus which includes: an output stage providing the apparatus with an output voltage and producing a partial voltage of the output voltage; an error amplifier coupled to the output stage and comparing the partial voltage with a reference to produce a first voltage; a PWM unit coupled to the error amplifier and comparing the first voltage with a voltage signal to produce second and third voltages; a selection unit coupled to the error amplifier and the PWM unit and outputting a fourth voltage equalling either the first or the second voltage; a first transistor coupled to the selection unit and receiving the fourth voltage and a DC voltage; and a second transistor coupled to the PWM unit, the first transistor, and a ground and receiving the third voltage; wherein a connection point of the first and second transistors is connected to the output stage.

Abstract: The invention discloses a voltage regulating apparatus, which includes: a linear regulator generating a first error signal; a switching regulator generating a first and a second PWM signals; a selecting unit coupled to the linear and switching regulators, receiving the first error signal and the second PWM signal, and outputting a regulating signal; a first power transistor coupled to the switching regulator and receiving the first PWM signal; and a second power transistor coupled to the selecting unit and receiving the regulating signal; wherein the voltage regulating apparatus can be put either in a linear mode of operation if the first error signal is selected as the regulating signal, or in a switching mode of operation if the second PWM signal is selected as the regulating signal.

Abstract: An exemplary switching power supply circuit includes a transformer, a switching control circuit, a DC-DC converter, and a signal selecting circuit. The transformer converts a DC voltage into a first DC voltage and a second DC voltage. The switching control circuit controls a current flowing on the transformer for generating the first DC voltage and the second DC voltage. The DC-DC converter converts the first DC voltage or the second DC voltage into a third DC voltage. The signal selecting circuit selects the first DC voltage or the second DC voltage for the DC-DC converter to generate the third DC voltage.

Abstract: A semiconductor device monitors a voltage between a reference potential and an input potential and obtains a constant output potential regardless of a value of the voltage, after the voltage exceeds a predetermined threshold voltage in such a manner that the semiconductor device divides a voltage between the reference potential and the input potential using a plurality of first non-linear elements and at least one linear element to constantly generate a first bias voltage regardless of a value of the voltage, divides a voltage between the reference potential and the input potential using a plurality of second non-linear elements with reference to the first bias voltage to constantly generate a second bias voltage regardless of a value of the voltage, and determines the output potential with reference to the second bias voltage.

Abstract: A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.

Abstract: In a sensor driving/measuring system, specifications required by a sensor which requires a high applied voltage are implemented with const increase suppressed. A semiconductor integrated circuit for use in a sensor driving/measuring system driven by a battery includes: a sensor driver for outputting a given voltage to be applied to a sensor; a measuring circuit for receiving and measuring a voltage obtained, through current-voltage conversion, from a current generated in the sensor; and a booster. The booster boosts a given pre-boost voltage to obtain a boosted voltage and supplies the boosted voltage as a power supply voltage to the sensor driver and the measuring circuit.

Abstract: A power regulation circuit includes at least a first regulator connected to a second regulator in series forming a first regulator pair and a third regulator connected to a fourth regulator in series forming a second regulator pair. The first regulator pair is connected in parallel with the second regulator pair. Each individual regulator is configured to separately regulate an input voltage to a predetermined regulated output voltage. The second regulator pair regulates the input voltage if a short condition occurs within the first regulator pair and the second and fourth regulators each regulate the input voltage if an open condition occurs within the first or third regulator respectively.

Abstract: A power supply circuit includes a first voltage regulator, a second voltage regulator, and a voltage comparator. The first voltage regulator is connected to a direct current power supply, and regulates a direct current supply voltage down to a first voltage level to output a first voltage at a first output terminal. The second voltage regulator is connected to the first voltage regulator, and regulates the first output voltage down to a constant, second voltage level to output a second voltage at a second output terminal. The voltage comparator is connected to the first and second voltage regulators, compares the first output voltage against a given threshold level greater than the second voltage level, and deactivates the second voltage regulator until the first output voltage exceeds the given threshold level upon startup of the power supply circuit.

Abstract: A regulator comprising a linear regulator. The linear regulator may comprise a preamplifier, a first radio frequency (RF) transistor and a second radio frequency (RF) transistor. An output of the preamplifier stage may be provided to a biasing terminal of the first RF transistor and a biasing terminal of the second RF transistor. Also, the first and second RF transistors may be electrically connected in series between a positive supply voltage and a negative supply voltage.

Abstract: In general, in one aspect, the disclosure describes a voltage regulator (VR) that includes a first amplifier receiving a first reference voltage and a feedback voltage as inputs. A second amplifier receiving a second reference voltage and an output of the first amplifier as inputs. A drive component (e.g., transistor(s)) coupled to the second amplifier to drive current to an output based on an output of the second amplifier. A shunt component (e.g., transistor(s)) coupled to the first amplifier to shunt current from the output based on the output of the first amplifier. Current variations in the shunt component are controlled.

Abstract: Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with the voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.