Calibration Patents (Class 324/601)
  • Patent number: 11892534
    Abstract: A frequency characteristic measurement apparatus includes a calibration circuit configured to perform a SOLT calibration on cable end surfaces, a first measurement circuit measuring S-parameters of a first substrate provided with a DUT, after the SOLT calibration by the calibration circuit, a second measurement circuit measuring S-parameters of a second substrate after the SOLT calibration by the calibration circuit, and an extraction circuit performing a vector operation of a measurement result of the first measurement circuit and a measurement result of the second measurement circuit to extract S-parameters of the DUT. The extraction circuit assumes that a reflection of each of first second fixtures obtained by virtually dividing the second substrate into two parts at the center, on an end surface of the second substrate is equal to or smaller than a reflection on an end surface of the second substrate without the virtual division at the center.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: February 6, 2024
    Assignee: ROHM Co., LTD.
    Inventor: Kenji Hamachi
  • Patent number: 11874361
    Abstract: Systems, devices, methods, and techniques for self-correcting current measuring are disclosed. Advanced material inductive measuring devices can obtain a reading of a monitored current in a monitored source. The advanced material allows the measuring device to operate at low temperatures disproportionate to saturation levels. Readings by the measuring device that are beyond a top-end limit of the measuring system or otherwise outside of a desired band can be transformed or transposed by employing a transformation to correct the reading to be within an acceptable ratio error band.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: January 16, 2024
    Assignee: Vutility, Inc.
    Inventor: Micheal M. Austin
  • Patent number: 11840465
    Abstract: A sensor is configured to sense a parameter of an aqueous liquid. The sensor has an analog output port configured to provide an analog signal indicative of a sensed parameter, and a calibration memory device storing individual digital information indicative of a calibration of the sensor. A digital output port provides a digital signal indicative of the digital information. A treatment system and method is matched to the sensor.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: December 12, 2023
    Assignee: Digital Concepts of Missouri, Inc.
    Inventors: Jack Greenwood, Christopher Seay Green, Kenneth W. Law
  • Patent number: 11789076
    Abstract: A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips include at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip transmits an output signal to the second chip via the chip-to-chip connection, and the second chip processes an input signal that is derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system calibrates a chip setting of at least one of the first chip and the second chip for pulse width calibration of the input signal.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: October 17, 2023
    Assignee: MEDIATEK INC.
    Inventor: Ko-Ching Su
  • Patent number: 11613293
    Abstract: A capacitive detection device that may include at least one electrode of a capacitive sensor, an alternating voltage source, a device for measuring a complex value of impedance or admittance between the detection electrode and an electrical circuit reference point and a calibration resistor, and a switching device arranged so as to connect the voltage source to the electrode, in the measurement mode, and to connect the voltage source to the calibration resistor and disconnect the voltage source from the electrode, in the calibration mode. The measuring device is arranged so as to measure a first complex value of the calibration resistor, during operation in the calibration mode; to measure a second complex value between the electrode and the electrical circuit reference point during operation in measurement mode, and to correct the second measured complex value according to the first measured complex value.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 28, 2023
    Inventor: Pierre Sabourin
  • Patent number: 11561248
    Abstract: A resistance mapping device includes: a first chip including a first surface, a second surface positioned at a side opposite to the first surface, and a plurality of first electrodes provided at the first surface; a second chip including a third surface facing the first surface, a fourth surface positioned at a side opposite to the third surface, and a plurality of second electrodes provided at the third surface; and a measurement part, the measurement part being configured to measure a resistance of a portion of a measurement object, the portion of the measurement object being between the first electrode and the second electrode that correspond to each other among the plurality of first electrodes and the plurality of second electrodes, and acquire mapping data in which measured values of the resistances are associated with positions of the measurement object corresponding to the plurality of first electrodes.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: January 24, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Akira Tanaka
  • Patent number: 11543448
    Abstract: A method is provided for dynamically determining measurement uncertainty (MU) of a measurement device for measuring a signal output by a device under test (DUT). The method includes storing characterized test data in a nonvolatile memory in the measurement device, the characterized test data being specific to the measurement device for a plurality of sources of uncertainty; receiving a parameter value of the DUT; measuring the signal output by the DUT and received by the measurement device; and calculating the measurement uncertainty of the measurement device for measuring the received signal using the stored characterized test data and the received parameter value of the DUT.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: January 3, 2023
    Assignee: Keysight Technologies, Inc.
    Inventors: Su Ann Lim, Ghazali Bin Hussin, Hwei Liat Law, Wei Zhi Ng
  • Patent number: 11516029
    Abstract: Described is a process measurement device having an interface for connecting a plug-in memory, in which a processing measurement device includes a memory operating device that can switch the process measurement device into a memory access mode when the memory is connected to the process measurement device. Also described is a power supply that ensures that the energy demand required for read access or write access to the process measurement device is automatically covered after the connection of the memory by increasing the amount of electrical energy that is freely available in the process measurement device. Undesired undersupply of the process measurement device can thereby be effectively avoided.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: November 29, 2022
    Assignee: VEGA GRIESHABER KG
    Inventors: Roland Welle, Karl Griessbaum, Joerg Boersig, Holger Staiger, Clemens Hengstler, Thomas Oehler, Manuel Harter
  • Patent number: 11460504
    Abstract: A cabinet box comprises a plurality of independent, explosion-proof chambers. A battery wiring assembly for receiving and testing a battery is attached to an inner wall of an explosion-proof door, and an electrical connector is provided on an outer wall of the door. The assembly is placed inside a chamber, and the door seals the chamber. The temperature in each chamber is controlled independently, allowing batteries to be tested simultaneously at different temperatures. An air-circulating temperature-control module can be in a chamber, or a temperature controller with a refrigeration sheet can be integrated with the battery wiring assembly for direct battery contact. Separate, independent explosion-proof chambers effectively eliminate the possibility of a battery explosion in one chamber causing a chain-reaction explosion in another chamber. Modularity allows damaged parts to be replaced easily. An external battery testing machine can connected to the connector on each door.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: October 4, 2022
    Inventor: Chaojiong Zhang
  • Patent number: 11428770
    Abstract: A method of calibrating a setup comprises: performing at least one calibration of the setup, thereby obtaining calibration data; setting a quantity representing forward tracking to be equal with a quantity representing reverse tracking; solving a system of equations having at least an unknown quantity representing the forward tracking or the reverse tracking, thereby obtaining at least one equation having the unknown quantity squared; creating based on the calibration data obtained two phase over frequency relationships for the respective quantity; determining two lines having a linear change in phase over frequency for the phase over frequency relationships created; extrapolating the lines determined to a frequency of 0 Hz; and determining the respective quantity by selecting one line of the lines extrapolated that is closer to a phase of zero, 2? or a multiple thereof at the frequency of 0 Hz.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 30, 2022
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Jan-Patrick Schultheis, Werner Held
  • Patent number: 11418021
    Abstract: The invention relates to a device circuit breaker having intelligent limit value determination. In a training phase, the device circuit breaker is adjusted to a specific device and its load behavior. In a subsequent monitoring phase—based on the values determined in the training phase—present values or values derived from those are compared and, if necessary, the current flow is interrupted.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: August 16, 2022
    Assignee: PHOENIX CONTACT GMBH & CO. KG
    Inventors: Gerhard Wölk, Martin Striewe, Alexander Fomenko, Guido Nahles
  • Patent number: 11385175
    Abstract: A calibration method includes: acquiring eight error models obtained after a preliminary calibration of a Terahertz frequency band system; based on the eight error models, determining a first mathematical model according to a first S parameter related to a first calibration piece, the first mathematical model comprising parallel crosstalk terms between probes, and determining a second mathematical model according to a second S parameter related to a second calibration piece, the second mathematical model comprising series crosstalk terms between the probes; determining a third mathematical model according to a third S parameter related to a measured piece; and solving and obtaining a Z parameter of the measured piece based on the first mathematical model, the second mathematical model and the third mathematical model, and acquiring an S parameter of the measured piece according to the Z parameter of the measured piece.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 12, 2022
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yibang Wang, Aihua Wu, Faguo Liang, Chen Liu, Peng Luan, Ye Huo, Jing Sun, Yanli Li
  • Patent number: 11356186
    Abstract: Disclosed are example embodiments of methods and systems for calibrating the second and third order intermodulation intercept points of a radio transceiver. The calibration circuit comprises: a common mode voltage (VCM) calibration circuit having a complementary to absolute temperature (CTAT) voltage node coupled to one or more VCM nodes of the radio transceiver, wherein the VCM calibration circuit is configured to adjust the CTAT voltage to reduce a third-order intermodulation (IM3) at an output of the radio transceiver; and a bulk terminal calibration circuit configured to bias one of a VBP and VBN voltages at one or more bulk terminals of one or more transistors of the RF circuit to reduce a second-order intermodulation (IM2).
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: June 7, 2022
    Assignee: Sequans Communications SA
    Inventors: Arash Abbasi, Bertrand Debray
  • Patent number: 11340286
    Abstract: The present application is applicable to the technical field of terahertz on-wafer measurement, and provides a new on-wafer S-parameter calibration method and device. The method includes: performing two-port calibration on a waveguide end face when a probe is not connected to a test system; performing one-port calibration on each of two probe end faces when the probe is connected to the test system; and fabricating a crosstalk calibration standard equal to a device under test in length on a substrate of the device under test, and correct a crosstalk error of the test system according to the crosstalk calibration standard. The present application can realize accurate characterization and correction of crosstalk error in a high-frequency on-wafer S-parameter calibration process, and improve the accuracy of error correction in high-frequency on-wafer S-parameter measurement.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: May 24, 2022
    Assignee: THE 13TH RESEARCH INSTITUTE OF CHINA ELECTRONICS
    Inventors: Aihua Wu, Chong Li, Chen Liu, Yibang Wang, Xingchang Fu, Faguo Liang, Xiuwei Tian, Yanan Liu, Jian Cao
  • Patent number: 11335540
    Abstract: In one embodiment, an impedance matching network includes a mechanically variable capacitor (MVC), a second variable capacitor, and a control circuit. The control circuit carries out a first process of determining a second variable capacitor configuration for reducing a reflected power at the RF source output, and altering the second variable capacitor to the second variable capacitor configuration. The control circuit also carries out a second process of determining an RF source frequency, and, upon determining that the RF source frequency is outside, at a minimum, or at a maximum of a predetermined frequency range, determining a new MVC configuration to cause the RF source frequency, according to an RF source frequency tuning process, to be altered to be within or closer to the predetermined frequency range. The determination of the new MVC configuration is based on the RF source frequency and the predetermined frequency range.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 17, 2022
    Inventors: Imran Bhutta, Michael Ulrich
  • Patent number: 11324432
    Abstract: A signal processing apparatus includes an input voltage selector configured to select an input voltage from a plurality of input voltages; an input element connected to the input voltage selector; and an input current controller configured to control an inflow of an input current in conjunction with an operation of the input voltage selector.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 10, 2022
    Assignees: Samsung Electronics Co., Ltd., THE INDUSTRY & ACADEMIC COOPERATION IN CHUNGNAM NATIONAL UNIVERSITY (IAC)
    Inventors: JongPal Kim, TakHyung Lee, Hyoung Ho Ko
  • Patent number: 11320320
    Abstract: An example device includes a first temperature sensor configured to provide a first current signal indicative of a temperature of a first circuit based on a voltage of a first temperature sensing element. The first circuit includes a power switch device and the first temperature sensing element. A second temperature sensor is configured to provide a second current signal indicative of temperature of a second circuit based on a voltage of a second temperature sensing element. The second circuit includes the second temperature sensing element. A trim circuit is configured to trim current in at least one of the first temperature sensor or the second temperature sensor to compensate for mismatch between temperature coefficients of the first and second temperature sensing elements.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eung Jung Kim, Abidur Rahman
  • Patent number: 11296697
    Abstract: An on-die termination circuit may include a resistance combination circuit, a first calibration circuit, a second calibration circuit, and a termination circuit. The resistance combination circuit may have an additional resistance value for setting a combined resistance value by combining the additional resistance value with a reference resistance value, and may be configured to set the additional resistance value based on a second calibration code. The first calibration circuit may be configured to generate a first calibration code corresponding to the reference resistance value or the combined resistance value according to a calibration sequence. The second calibration circuit may be configured to generate the second calibration code corresponding to the first calibration code. The termination circuit may be coupled to an input/output pad, and may be configured to set a termination resistance value corresponding to the first and second calibration codes.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventor: Bo Ram Kim
  • Patent number: 11275103
    Abstract: The disclosure provides a calibration method, a system and a device of an on-wafer S parameter of a vector network analyzer. The method comprises the steps of: acquiring a first parameter of a first crosstalk calibration piece measured by the vector network analyzer; obtaining a main crosstalk error term based on the first parameter of the first crosstalk calibration piece and a calibration parameter of the first crosstalk calibration piece; acquiring a second parameter of a second crosstalk calibration piece measured by the vector network analyzer based on the main crosstalk error term; and obtaining a secondary crosstalk error term based on the second parameter of the second crosstalk calibration piece and a calibration parameter of the second crosstalk calibration piece, wherein the main crosstalk error term and the secondary crosstalk error term are used for calibrating the vector network analyzer.
    Type: Grant
    Filed: September 19, 2020
    Date of Patent: March 15, 2022
    Assignee: The 13th Research Institute of China Electronics Technology Group Corporation
    Inventors: Yibang Wang, Aihua Wu, Faguo Liang, Chen Liu, Xuefeng Zou, Zhifu Hu, Jian Cao, Ye Huo
  • Patent number: 11276453
    Abstract: A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Bill Nale
  • Patent number: 11266004
    Abstract: The present disclosure relates to a plasma generator having a matching apparatus for matching impedances, and an impedance matching method. The plasma generator includes an RF power supply unit, a load device part including a standard load having a predetermined impedance and an antenna-plasma device configured to generate plasma, and a matching unit configured to connect the RF power supply unit to any one of the antenna-plasma device or the standard load, and match impedances of the RF power supply unit and the antenna-plasma device when the RF power supply unit is connected to the antenna-plasma device, wherein the matching unit is configured to detect a parasitic impedance according to parasitic components inside a circuit by connecting the standard load and the RF power supply unit, connect the antenna-plasma device, when the parasitic impedances are detected, calculate reactance required for the impedance matching, and change capacitance.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 1, 2022
    Assignee: KOREA ATOMIC ENERGY RESEARCH INSTITUTE
    Inventors: Sunho Kim, Bongki Jung
  • Patent number: 11238260
    Abstract: Non-biological objects, biological specimens and living tissues are examined using electric fields to identify regions of differing permittivity and conductivity. Substantially parallel electrodes are deployed in capacitive alignment with an object and energization pulses are generated for application to any of the electrodes as a transmitter. Output signals from any remaining electrode are monitored, in which a peak value of an output signal is indicative of permittivity and a decay rate of an output signal is indicative of conductivity. A first set of n electrodes (one to fifteen) is selected, each of which is capacitively coupled with a second set of m electrodes (two to eight) that are the nearest neighbouring electrodes to an electrode selected from the first set.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 1, 2022
    Assignee: Zedsen Limited
    Inventor: Hrand Mami Mamigonians
  • Patent number: 11226752
    Abstract: Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 18, 2022
    Assignee: Apple Inc.
    Inventors: Rakesh L. Notani, Robert E. Jeter, Suhas Kumar Suvarna Ramesh, Naveen Kumar Korada, Mohammad Rizwan, Alma L. Juarez Dominguez, John H. Kelm, Matthew R. Johnson
  • Patent number: 11212467
    Abstract: A switch driver circuit includes a first transistor coupled between a voltage supply and a first output node. A second transistor is coupled between the first output node and a first discharge node. A first slope control circuit is coupled to the first discharge node to discharge the first discharge node at a first slope. A third transistor is coupled between the voltage supply and a second output node. A fourth transistor is coupled between the second output node and a second discharge node. A second slope control circuit coupled to the second discharge node to discharge the second discharge node at a second slope. The first and second slopes are mismatched.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: December 28, 2021
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Zhe Gao, Ling Fu, Yu-Shen Yang, Tiejun Dai
  • Patent number: 11187498
    Abstract: Systems and methods for calibrating a conducted electrical weapon (“CEW”) to provide a predetermined amount of current for each pulse of the stimulus signal. Providing the predetermined amount of current, close thereto, increases the effectiveness of the stimulus signal in impeding locomotion of a human or animal target. The calibration process enables a CEW to calibrate the amount of charge in a pulse of the stimulus signal in the environmental conditions where the tester operates and also in the field where the environmental conditions may be different from the environmental conditions during calibration.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 30, 2021
    Assignee: Axon Enterprise, Inc.
    Inventors: Magne H. Nerheim, Valerie Renee Barry Barber-Axthelm, Eric Heindel Goodchild, Siddharth Heroor
  • Patent number: 11175332
    Abstract: A method for measuring current-voltage characteristics representing the relationship between the drain current and the drain-source voltage of a first transistor includes: a first step of setting the drain current and the drain-source voltage using a voltage source and a current source connected in series with the first transistor and a rectifying element connected in parallel with, with the reverse polarity to, an inductive load as the current source; a second step of measuring the gate-source voltage and the gate current in the switching transient state of the first transistor; and a third step of calculating the voltage applied to the gate oxide film of the first transistor using the results of the measurement of the gate-source voltage and the gate current and acquiring the current-voltage characteristics of the first transistor using the result of the calculation.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 16, 2021
    Assignee: Rohm Co., Ltd.
    Inventors: Yohei Nakamura, Tatsuya Yanagi
  • Patent number: 11162790
    Abstract: A drive signal is applied to a MEMS gyroscope having several intrinsic resonant modes. Frequency and amplitude of mechanical oscillation in response to the drive signal is sensed. At startup, the drive signal frequency is set to a kicking frequency offset from a resonant frequency corresponding to a desired one of the intrinsic resonant modes. In response to sufficient sensed amplitude of mechanical oscillation at the kicking frequency, a frequency tracking process is engaged to control the frequency for the drive signal to sustain mechanical oscillation at the frequency of the desired one of the plurality of intrinsic resonant modes as the oscillation amplitude increases. When the increasing amplitude of the mechanical oscillation exceeds a threshold, a gain control process is used to exercise gain control over the applied drive signal so as to cause the amplitude of mechanical oscillation to match a further threshold. At that point start-up terminates.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 2, 2021
    Assignee: STMicroelectronics, Inc.
    Inventors: Deyou Fang, Chao-Ming Tsai, Yamu Hu
  • Patent number: 11137470
    Abstract: A TRL calibration kit including THRU, REFLECT and a set of DELAY line standards and associated thread extension and holding device, allowing for employing more than one DELAY line standard without modifying the configuration, for higher wideband calibration accuracy. The thread extension allows inserting and securing multiple DELAY lines without removing the device by just inserting and releasing set screws in-situ. This provides for best repeatability of the connections.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 5, 2021
    Inventor: Christos Tsironis
  • Patent number: 11129245
    Abstract: A method for matching an impedance of a system comprising a cavity and one or more feeds to an impedance of one or more sources of electromagnetic radiation irradiating a plurality of frequencies into the cavity via the feeds, comprising: determining a plurality of s-parameter of the system for a frequency band; determining the system impedance based on the s-parameters; and modifying the system impedance according to the difference between the impedance of the system and the impedance of the source.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: September 21, 2021
    Assignee: GOJI LIMITED
    Inventors: Eran Ben-Shmuel, Alexander Bilchinsky
  • Patent number: 11125777
    Abstract: A hermetically sealed adjustable link for low loss coaxial airline connection between the seamless connection of coaxial RF connector of external instruments with 30- or 45-degrees wafer probes allows continuous, micro-positioner controlled, 3-axis horizontal and vertical probe movement. A flexible sealing ring ensures airtight and/or RF-EMI shielded operation. A metallic or plastic collar ensures wafer testing under EMI shielded and high temperature conditions.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: September 21, 2021
    Inventor: Christos Tsironis
  • Patent number: 11101109
    Abstract: An impedance matching device includes: a variable capacitor in which a plurality of first capacitance elements or a plurality of second capacitance elements are connected in parallel; a calculation unit that calculates an impedance or a reflection coefficient on the load side using information regarding the impedance acquired from the outside; and a control unit that determines an ON/OFF state to be taken by each of semiconductor switches included in the variable capacitor using the impedance or the reflection coefficient calculated by the calculation unit and turns on or off the semiconductor switches included in the first or second capacitance element based on the determined state. The control unit cyclically switches semiconductor switches to be turned on or off in a predetermined order.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 24, 2021
    Assignee: DAIHEN Corporation
    Inventor: Tatsuya Morii
  • Patent number: 11087331
    Abstract: A first device may receive an error log relating to an error associated with accessing content that is associated with a toll-free data campaign. The error log may include information identifying the error. The first device may determine a cause of the error based on the error log. The first device may determine an updated status of the content or the toll-free data campaign. The first device may generate an error explanation based on the cause of the error and the updated status. The error explanation may identify the cause of the error or the updated status. The first device may cause the error explanation to be provided to a second device that is associated with the error log.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 10, 2021
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Gong Zhang, Jian Huang
  • Patent number: 11079429
    Abstract: An ATE testing system (900, 1000) for millimetre wave (mmW) packaged integrated circuits (820) includes: at least one packaged integrated circuit (820); a radio frequency, RF, socket (700) configured to receive the at least one packaged integrated circuit (820) and facilitate routing RF signals thereto via at least one input connector and at least one output connector; and at least one interface configured to couple a tester to at least one packaged integrated circuit (820). The RF socket (700) includes a mmW absorber (1010) located adjacent the at least one output connector of the RF socket (700).
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 3, 2021
    Assignee: NXP B.V.
    Inventors: Abdellatif Zanati, Holger Mahnke
  • Patent number: 11081316
    Abstract: In one embodiment, an RF impedance matching network for a plasma chamber is disclosed. The matching network includes a mechanically variable capacitor (MVC) and a second variable capacitor. A control circuit is configured to carry out a first process for altering the second variable capacitor and the RF source frequency to reduce reflected power. The control circuit is further configured to carry out a second process of, upon determining that the alteration of the RF source frequency has caused the RF source frequency to be outside, at a minimum, or at a maximum of a predetermined frequency range, determining a new MVC configuration to cause the RF source frequency, according to the first process, to be altered to be within or closer to the predetermined frequency range. The new MVC configuration is based on the RF source frequency and the predetermined frequency range.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: August 3, 2021
    Inventors: Michael Gilliam Ulrich, Imran Ahmed Bhutta, Chingping Huang
  • Patent number: 11073590
    Abstract: A calibration array for calibrating a network analyzer, the array having multiple calibration points for direct or indirect connection to a network analyzer, and a main body connected to the calibration points, at least one of the calibration points being rotatable in relation to the main body.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 27, 2021
    Assignee: ROSENBERGER HOCHFREQUENZTECHNIK GMBH & CO. KG
    Inventors: Marcel Panicke, Markus Müller, Ronny Mark
  • Patent number: 11054450
    Abstract: A method of calibrating a measurement and analyzing device for measuring a frequency-converting device under test, comprises the steps of connecting a first port of the measurement and analyzing device with a radio frequency port assigned to the frequency-converting device under test as well as connecting a second port of the measurement and analyzing device with an intermediate frequency port assigned to the frequency-converting device under test. Further, a scalar-mixer calibration is performed at the radio frequency port and the intermediate frequency port, thus providing a precise calibration conversion amplitude. A relative calibration is performed between the radio frequency port and the intermediate frequency port by using a calibration mixer. At least one correction coefficient is determined by the difference between the results obtained from the scalar-mixer calibration and the relative calibration. The at least one correction coefficient is used to correct an error term applied.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: July 6, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Werner Held, Jan-Patrick Schultheis, Jakob Hammer
  • Patent number: 11054445
    Abstract: The invention relates to a measuring device and a measurement method for the display of a measurement signal connected to the measuring device. The measuring device comprises a measurement-signal input, a measurement-parameter input, a calculation unit and a display unit for the display of calculated statistical signals. The measuring device is set up to display a plurality of statistical signals in parallel on the display unit in real-time.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: July 6, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Matthias Keller, Wolfgang Wendler
  • Patent number: 11041894
    Abstract: A vector network analyzer comprises a first measuring port, a first digital interface, connected to the first measuring port, adapted to be connected to a digital input or output of a device under test, and a second measuring port, adapted to be connected to a radio frequency input or output of the device under test. It also comprises a processor, adapted to determine S-parameters of the device under test based upon measuring signals transmitted to the device under test and receive from the device under test by the first measuring port and the second measuring port.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 22, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Steffen Heuel, Steffen Neidhardt, Thilo Bednorz
  • Patent number: 11003370
    Abstract: A system on chip includes a clock generator that adjusts a duty cycle of a clock to be output to a memory device depending on a first code, a reference voltage generator that adjusts a level of a reference voltage used to determine a first data input/output signal output from the memory device depending on a second code, a data receiver that aligns a first data strobe signal and the first data input/output signal output from the memory device, when one of the first code and the second code is changed, and a training circuit that calculates a plurality of read valid window margins for a plurality of combinations of the first code and the second code based on the first data strobe signal and the first data input/output signal.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongseob Kim, Minho Seo
  • Patent number: 10976428
    Abstract: The present disclosure relates to an apparatus and method for synthetically making an ultra-wide imaging bandwidth in millimeter-wave frequencies, resulting in improved image resolutions to values previously unattained. The synthetic approach sums up a number of available sub-bands (channels) to build an unavailable ultra-wideband system. Each channel contains an antenna unit which is optimized for operation within that specific sub-band. The number and position of the channels can be adjusted to cover any frequency range as required for the specific application.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: April 13, 2021
    Assignee: THE TRUSTEES OF THE STEVENS INSTITUTE OF TECHNOLOGY
    Inventors: Negar Tavassolian, Amir Mirbeik-Sabzevari
  • Patent number: 10969421
    Abstract: A test instrument, including an embedded VNA circuit, for testing a DUT. The test instrument includes a first receiver for receiving an incident RF signal through a first coupling device; a second receiver for receiving a reflected RF signal through a second coupling device; a test port for connecting to an interconnect, which is connectable to a calibration device in a calibrating stage, during which the interconnect is characterized, and to the DUT in a testing stage, during which at least one parameter of the DUT is tested; an RF source for generating the incident RF signal during the calibrating stage; and a processing unit programmed to determine S-parameters of the interconnect based on the incident RF signal and the reflected RF signal, the S-parameters compensating for error introduced by the interconnect when testing the at least one parameter of the DUT in the testing stage.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Keysight Technologies, Inc.
    Inventors: Keith F. Anderson, Alex Grichener
  • Patent number: 10949005
    Abstract: The present disclosure relates to a testing device and techniques of testing semiconductor structures and, more particularly, to an absolute phase measurement testing device and technique of testing semiconductor structures. The structure includes: a first frequency input source which provides a first signal to an up-converter at an input side of a test fixture; a down-converter on an output side of the test fixture; a second frequency signal source which provides a second signal at a higher frequency than the first signal to the up-converter and the down-converter on the output side of the test fixture; a bypass path which bypasses the test fixture and provides connection between the up-converter and the down-converter; and a digitizer that is connected to an output side of the down-converter.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: March 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Mustapha Slamani, Kaushal Kannan, Ritin Nambiar, Timothy M. Platt
  • Patent number: 10897316
    Abstract: A test system for determining a response function of a transmission channel is disclosed. The transmission channel comprises an input, a mixer, a device under test and a coupling unit. The test system comprises a local oscillator, a delay unit, a combiner and an analysis module. The analysis module is configured to determine the response function of the transmission channel based on a superposed signal, wherein the superposed signal comprises an output signal of a device under test and a delayed oscillator signal. Further, a method for determining a response function of a transmission channel is disclosed.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 19, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Michael Feilen
  • Patent number: 10890604
    Abstract: A test and measurement instrument having a signal generator circuit and a waveform monitor circuit for monitoring a waveform received at a device under test (DUT). The signal generator circuit generates a waveform based on an input from a user, while the waveform monitor circuit sends captured signals to a processor to determine a waveform received at the DUT. The waveform monitor captures a signal at a first test point and a second test point, via a switch, and the processor receives the captured signals and using linear equations determines both an incident waveform and a reflected waveform from the DUT.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: January 12, 2021
    Assignee: Tektronix, Inc.
    Inventors: Jianjie Huang, Sicong Zhu, Hu Tang, Yufang Li, Jin Qian
  • Patent number: 10890642
    Abstract: A method of calibrating an impedance measurement device for measuring DUT impedance includes performing short calibration measurements using a short calibration standard to obtain short raw data; performing first shunt calibration measurements using a first shunt calibration standard to obtain first raw data, the first shunt calibration standard having known first resistance and unknown first inductance; performing second shunt calibration measurements using a second shunt calibration standard to obtain second raw data, the second shunt calibration standard having known second resistance and unknown second inductance; determining first and second complex impedances of the first and second shunt calibration standards by calculating the first and second inductances using the short, first and second raw data applied to a specific error model; and determining general error coefficients for an error model using the first and second complex impedances and the first and second raw data applied to a one-port calibrat
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 12, 2021
    Assignee: Keysight Technologies, Inc.
    Inventor: Manuel Kasper
  • Patent number: 10871540
    Abstract: A measurement device for measuring a current calibration coefficient includes: a host computer and a current source, wherein the host computer is configured to acquire current calibration coefficients including a current calibration coefficient at a temperature T1 and a current calibration coefficient at a temperature T2, and transmit the current calibration coefficients to the current detection device.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: December 22, 2020
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Yizhen Hou, Zhimin Dan, Wei Zhang, Jia Xu
  • Patent number: 10871458
    Abstract: Transmit patches lie on the outer set of conductive patches that are coupled to the transmitter via the signal splitter. The receive patches lie on the outer set of conductive patches that are coupled to one or more receivers to receive a radio frequency field (e.g., fringing field) associated with the transmitted signal of one or more adjacent corresponding transmit patches. A detector is associated with one or more respective receivers for determining or estimating an attenuation of the radio frequency field (e.g., fringing field). An electronic data processor is arranged for evaluating the estimated attenuation to estimate the grain loss content and material other than grain content of the agricultural material.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: December 22, 2020
    Assignee: DEERE & COMPANY
    Inventors: William D. Todd, Gurmukh H. Advani, Noel W. Anderson
  • Patent number: 10863672
    Abstract: Transmit patches lie on the outer set of conductive patches that are coupled to the transmitter via the signal splitter. The receive patches lie on the outer set of conductive patches that are coupled to one or more receivers to receive a radio frequency field (e.g., fringing field) associated with the transmitted signal of one or more adjacent corresponding transmit patches. A detector is associated with one or more respective receivers for determining or estimating an attenuation of the radio frequency field (e.g., fringing field). An electronic data processor is arranged for evaluating the estimated attenuation to estimate the amount, volume, mass or flow (e.g., yield) of harvested agricultural material and/or other than grain content of the agricultural material.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 15, 2020
    Assignee: DEERE & COMPANY
    Inventors: William D. Todd, Gurmukh H. Advani, Noel W. Anderson
  • Patent number: 10860506
    Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 8, 2020
    Assignee: NETLIST, INC.
    Inventors: Hyun Lee, Jayesh R. Bhakta
  • Patent number: 10859433
    Abstract: An assembly line in-situ calibration arrangement, optical sensor arrangement and a method for calibration of an optical sensor arrangement are presented. A calibration arrangement comprises a calibration head comprising at least one calibrated light source located behind an aperture in a housing and being electrically connected to a power terminal. A power source is connected to the power terminal, the power source comprising a switching unit electrically connected to the at least one light source. An interface unit is connected to the switching unit by means of an interface connection, wherein the interface unit is arranged to control the switching unit. A control unit is connected to the interface unit, wherein the control unit is arranged to drive the interface unit such that the at least one light source is switched to emit a calibration pulse sequence to be received by the optical sensor arrangement to be placed with respect of the aperture.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: December 8, 2020
    Assignee: AMS AG
    Inventor: David Mehrl