Noise Patents (Class 324/613)
  • Patent number: 8093909
    Abstract: A method and a device for measuring the phase noise of a signal registers the measurement signal (V) with a given measurement frequency (f1) and with a superimposed phase noise (f1(t)), divides the measurement signal (V) into a first and second measurement signal (V1?, V2?), derives a first signal (V1) with a first frequency ((f1+f1(t))/N) reduced relative to the measurement frequency (f1) and the superimposed phase noise (f1(t)) and a second signal (V2) with a second frequency ((f1+f1(t))/M) reduced relative to the measurement frequency (f1) and the superimposed phase noise (f1(t)), determines a third signal (V3) with a third frequency (f3(t)) compensated by the measurement frequency (f1) relative to the first frequency ((f1+f1(t))/N) of the first signal (V1) and a fourth signal (V4) with a fourth frequency (f4(t)) compensated by the measurement frequency (f1) relative to the second frequency ((f1+f1(t))/M) of the second signal (V2) and determines a correlation spectrum from the third and fourth signal (V3,
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: January 10, 2012
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Wolfgang Wendler, Alexander Roth, Hagen Eckert
  • Publication number: 20120001643
    Abstract: A noise suppression method for a capacitance-to-voltage converter varies a sequence of sensing signal edges during a plurality capacitance measurements to produce a number of noise responses. The sensing signal edges are varied in a repetitive rising and falling edge pattern for each sequence. Three or more such sequences can be used, and the sequence with the highest noise is eliminated and the others are averaged. The noise suppression method can be implemented during calibration and then used for a number of normal acquisitions. The noise suppression method can be applied to capacitance-to-voltage converters having monitoring and integration phases.
    Type: Application
    Filed: July 1, 2010
    Publication date: January 5, 2012
    Applicant: STMicroelectronics Asia Pacific Pte Ltd.
    Inventor: Kusuma Adi Ningrat
  • Patent number: 8089286
    Abstract: A system and method for characterizing noise in a quantum system includes determining pulse sequences for unitary twirling operations. Twirling processes are applied to a quantum system to calibrate errors and to determine channel parameters. Noise characteristics are determined from calibration data collected to calibrate the errors and to determine the channel parameters. The noise characteristics are characterized to determine if the noise is independent relaxation of qubits or collective relaxation of qubits.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: January 3, 2012
    Assignee: NEC Laboratories America, Inc.
    Inventors: Marcus Silva, Martin Roetteler
  • Publication number: 20110298474
    Abstract: A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 8, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kennedy K. Cheruiyot, Joel T. Ficke, David M. Friend, Grant P. Kesselring, James D. Strom
  • Patent number: 8067947
    Abstract: A low noise differential charge amplifier circuit for measuring discrete (e.g., pico coulomb) charges in noisy, elevated temperature and corrosive environments. An input stage of a differential charge amplifier circuit includes a twisted and or untwisted two pair cable with a grounded shield. One twisted and or untwisted pair can be connected to a sensor and a first charge amplifier and a second twisted and or/untwisted pair can be connected to a sensor electrical equivalent impedance circuit and or kept open and a second charge amplifier. The output from the charge amplifiers can be directed to a differential amplifier in order to provide an amplified sensor signal without external noise signal mainly from power supply mains. The differential amplifier and the charge amplifiers can include an auto offset correction circuit to reduce errors due to offsets.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: November 29, 2011
    Assignee: Honeywell International Inc.
    Inventors: Ramsesh Anilkumar, Baburaj Kaimalilputhenpura Prabhakaran
  • Patent number: 8030947
    Abstract: Second and third ports of a network analyzer are individually connected via cables to predetermined connection points on a differential transmission circuit on an object to be measured. A differential cable is connected to the differential transmission circuit. An antenna for receiving an electromagnetic wave radiated from the differential cable is connected to a first port of the network analyzer via a first cable. The network analyzer measures a three-port S parameter of the first, second, and third ports and calculates common-mode and normal-mode components of noise radiated from the differential cable. As a result, the source of noise in an electronic apparatus can be determined, and common-mode noise and normal-mode noise can be separately measured.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: October 4, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Ko Yamanaga, Takahiro Azuma
  • Publication number: 20110227599
    Abstract: A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 22, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Chiaki MIMURA, Kazuhiko Shimabayashi
  • Patent number: 8013593
    Abstract: A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: September 6, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung-Soo Kim, Yong-Ju Kim, Jong-Woon Kim, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang
  • Patent number: 8008926
    Abstract: Disclosed is a UHF partial discharge and its location measuring device for high-voltage power devices. The measuring device includes a partial discharge sensor, an external noise sensor, an analogue-digital converter, a peak detector, a partial discharge signal processor, an arrival time detector, a discharge location processor, and a display unit.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: August 30, 2011
    Assignee: Korea Electric Power Corporation
    Inventors: Ki-Jun Park, Sun-Geun Goo, Jin-Yul Yoon, Ki-Son Han, Hyung-Jun Ju
  • Publication number: 20110181298
    Abstract: Provided is a measurement apparatus that measures a signal under measurement input thereto, comprising a plurality of signal measurement circuits that measure a level of a signal input thereto, according to a sampling clock provided thereto; a noise measuring section that measures a noise component propagated from a first signal measurement circuit to a second signal measurement circuit, among the plurality of signal measurement circuits, based on a measurement result output by the second signal measurement circuit; and a clock supplying section that, when the signal under measurement is being measured, supplies the first signal measurement circuit and the second signal measurement circuit with sampling clocks having the same period and that, when the noise component is being measured, supplies the first signal measurement circuit and the second signal measurement circuit with sampling clocks having different periods.
    Type: Application
    Filed: October 14, 2010
    Publication date: July 28, 2011
    Applicant: ADVANTEST CORPORATION
    Inventors: Yasuhide KURAMOCHI, Masayuki KAWABATA
  • Patent number: 7983880
    Abstract: Extended linear superposition methods, computer program products and systems to calculate Simultaneous Switching Noise (SSN) on victim Input/Output (I/O) pins of an electronic component caused by aggressor I/O pins is provided. A method includes calculating the quiet output voltage on a victim pin caused by the power supply only, and then calculating an aggressor noise response induced on the victim pin caused by a single aggressor pin and the power supply. To calculate SSN for a combination of aggressors, the SSNs for the different aggressors are linearly combined, and then the effects of the power supply are discounted by using the calculated quiet output voltage. Additionally, a linear victim substitution model is introduced to replace a full buffer model for a victim pin with a resistor with different resistance values depending on the induced voltage. Further, an alternate transmission line model is introduced to simplify SSN simulations of transmission lines.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: July 19, 2011
    Assignee: Altera Corporation
    Inventors: Joshua David Fender, Paul Leventis
  • Patent number: 7969161
    Abstract: Electrical tomography drive frequency selection systems and methods are disclosed. One aspect of the present invention pertains to a system for optimally selecting a drive frequency of an electrical tomography which comprises a sensor electrode stably associated with a tissue site within an internal organ of a subject for generating an induced signal based on a noise signal over a range of frequency bands, wherein an electrical field for the electrical tomography is turned off. In addition, the system comprises a noise processing module for isolating the induced signal for each frequency band over the range of frequency bands. Furthermore, the system comprises a frequency select module for selecting a drive frequency of the electrical field for the electrical tomography by comparing the induced signal for each frequency band over the range of frequency bands.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: June 28, 2011
    Assignee: Proteus Bomedical, Inc.
    Inventors: Yashar Behzadi, Kenneth C. Crandall
  • Patent number: 7969158
    Abstract: A noise-reduction method for processing a port is applied to a test target for testing or being burned in with software. At least one zero-Ohm resistor is provided with a first end thereof electrically connected to a device under test (DUT) of the test target and a second end thereof connected to a test port. Moreover, at least one grounding zero-Ohm resistor is provided with one end connected to ground and the other end is a floating end. After the test target is finished debugging or burned in with software, the connection of the first end and the DUT is disabled, and the second end is connected to ground through the floating end to reduce noise generation and improve a flexibility in circuit layout.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: June 28, 2011
    Assignee: Foxconn Communication Technology Corp.
    Inventors: I-Chen Chen, Chien-Jung Lin, Chien-Hsun Ho
  • Patent number: 7952364
    Abstract: A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: May 31, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
  • Patent number: 7948228
    Abstract: To accurately measure power source noise generated inside an integrated circuit, the power source noise measuring device comprises: a mutual inductor pair placed inside an integrated circuit, the mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: May 24, 2011
    Assignee: Fujitsu Limited
    Inventors: Takahito Takemoto, Akihiko Harada, Kazuhiro Furuya
  • Publication number: 20110109459
    Abstract: A system is disclosed for detecting and calculating the level of ambient and/or environmental noise, such as electromagnetic interference generated by electric power lines, ambient lights, light dimmers, television or computer displays, power supplies or transformers, and medical equipment. In some embodiments, the system performs frequency analysis on the interference signal detected by light photodetectors and determines the power of the interference signal concentrated in the analyzed frequency bands. The worst-case interference level can be determined by selecting the maximum from the computed power values. In some embodiments, the determined interference signal power can be compared with the noise tolerance of a patient monitoring system configured to reliably and non-invasively detect physiological parameters of a user. The results of the comparison can be presented to the user audio-visually. In some embodiments, the system can be used to perform spot check measurements of electromagnetic interference.
    Type: Application
    Filed: July 22, 2010
    Publication date: May 12, 2011
    Applicant: MASIMO Laboratories, Inc.
    Inventors: Jeroen Poeze, Jesse Chen, Mathew Paul, Marcelo Lamego, Massi Joe E. Kiani
  • Patent number: 7940838
    Abstract: This invention provides a system for evaluating the performance of electronic components and systems by minimizing or eliminating intersymbol interference (ISI). The apparatus includes a transmitter, a device under test, a receiver, and at least one electrical connection between the transmitter and receiver that bypasses the device under test. The electrical connection between the transmitter and receiver transmits information characterizing the intersymbol interference of the transmitted signal to the receiver. The receiver includes an equalizer that uses the information characterizing the intersymbol interference of the transmitted signal to minimize or eliminate intersymbol interference in the received signal where the distortion introduced by the device under test can be isolated and characterized.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: May 10, 2011
    Assignee: Applied Wave Research, Inc.
    Inventor: Kurt R. Matis
  • Patent number: 7932731
    Abstract: A device for testing noise immunity of a circuit includes: an analog circuit, an internal stable reference signal source, an internal power supply module to receive a high level voltage supply, and a signal modulator to provide a noisy signal to the power supply module. The power supply module outputs a noisy power supply to the circuit, in response to the noisy signal, and the device outputs a signal representative of a noise immunity of the circuit. A method includes: providing a high level supply voltage to an internal power supply module, receiving signals representative of the performance of an analog circuit, providing a noisy signal to an input of the power supply module, providing a noisy supply voltage to the circuit, by the power supply module, in response to the noisy signal, and evaluating a noise immunity characteristic of the circuit in response to the received signals.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 26, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Yehim-Haim Fefer, Valery Neiman
  • Patent number: 7933559
    Abstract: A system for testing radio frequency (RF) communications of a device capable of such communications is provided. The system includes a chamber for isolating the device from RF interference, an antenna that is suitable for RF communications with the device wherein the antenna is capable of communications over a range of frequencies, the antenna being located within the chamber, and a digital communication link for providing non-RF communications with the device.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: April 26, 2011
    Assignee: Psion Teklogix Inc.
    Inventor: Zivota Zeke Stojcevic
  • Patent number: 7902835
    Abstract: A transmission line driving circuit that can support a high-rate signal transmission and further can perform appropriate loss compensation in accordance with a signal pattern. A transmission line driving circuit 1 comprises a plurality of driver input circuits 20 that serve as signal analyzing unit for analyzing the content of the signal pattern of an input signal; a plurality of lowpass filters 30; a plurality of gain adjusting circuits 40; a plurality of adders 50; and adder 52; and a driver output circuit 60 that outputs, in accordance with a signal analysis result, a signal the phase of which has been adjusted in such a direction that cancels the timing deviation caused by a loss occurring when the input signal is transmitted to the transmission path. The output signal from the driver output circuit 60 is transmitted to the transmission path 2.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: March 8, 2011
    Assignee: Advantest Corporation
    Inventors: Takayuki Nakamura, Takashi Sekino
  • Publication number: 20110043220
    Abstract: The transient load current of a circuit powered by a power distribution network is increased in a plurality of steps, with the step transition times being adjusted based on the transient noise of the power distribution network. This reduces the resonance noise that would otherwise occur in the supply current of the power distribution network.
    Type: Application
    Filed: May 5, 2009
    Publication date: February 24, 2011
    Applicant: RAMBUS INC.
    Inventors: Brian S. Leibowitz, Haechang Lee
  • Publication number: 20110025346
    Abstract: A power-supply noise measuring circuit includes a voltage fluctuation detecting circuit, a unit time generating circuit: a current measuring circuit, and a sampling circuit. The voltage fluctuation detecting circuit generates a detection current in accordance with a voltage fluctuation of a power supply. The unit time generating circuit generates a unit time in accordance with a clock signal. The current measuring circuit treasures an amount of the detection current per unit time. The sampling circuit samples the amount of the detection current measured by the current measuring circuit, every unit time. The present invention provides the power-supply noise measuring circuit that has a small circuit area and enough accuracy.
    Type: Application
    Filed: June 10, 2010
    Publication date: February 3, 2011
    Inventor: Mikihiro KAJITA
  • Patent number: 7880477
    Abstract: An integrated circuit arrangement has a signal input 20 and a signal output 60, a signal processing unit 100 which is connected to the signal input 20 and to the signal output 60, a noise source 50 for generating a noise signal, and a noise line 55 which connects the noise source 50 to the signal input 20.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Johann Peter Forstner
  • Patent number: 7868626
    Abstract: The present invention provides a burst noise canceling apparatus which can remove burst noises even in a one-time data, without the need of a large amount of memory.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: January 11, 2011
    Assignee: GE Medical Systems Global Technology Company, LLC
    Inventor: Nobuhiro Yoshizawa
  • Publication number: 20100321035
    Abstract: There is provided a shield-structured loop element which can suppress noise via a silicon substrate and can be manufactured by a semiconductor process. The loop element includes: a first well of a first polarity that is formed on a substrate; a deep well of a second polarity that is formed below the first well; a ring-shaped second well of a second polarity that is formed on the deep well along an outer periphery of the deep well; a third well of the first polarity that is formed in an island area surrounded by the deep well and the second well; a looped conductor that is formed in a layer above the third well and has smaller outer dimensions than those of the third well; and a first path that connects the second well to a bias power supply. The second well and the deep well are electrically connected to each other.
    Type: Application
    Filed: March 27, 2009
    Publication date: December 23, 2010
    Inventor: Norio Masuda
  • Publication number: 20100315098
    Abstract: In a method for determining a state variable of an electric arc furnace, especially for determining the level of the foamed slag (15) in a furnace, the energy supplied to the furnace is determined with the aid of at least one electric sensor while solid-borne noise is measured in the form of oscillations on the furnace. The state variable is determined by a transfer function which is determined by evaluating the measured oscillations and evaluating measured data of the electric sensor. The state of the foamed slag level can thus be reliably recognized and be monitored over time. The foamed slag level is decisive for the effectiveness with which energy is fed into the furnace. Furthermore, losses caused by radiation are reduced by covering the arc with the foamed slag. The improved measuring method allows the foamed slag level to be automatically controlled or regulated in a reliable manner.
    Type: Application
    Filed: August 24, 2010
    Publication date: December 16, 2010
    Inventors: Dieter Fink, Detlef Gerhard, Thomas Matschullat, Detlef Rieger, Reinhard Sesselmann
  • Publication number: 20100283481
    Abstract: System and methods for performing EMI susceptibility testing of a device is disclosed. A system may include an EMI generation unit that includes a plurality of EMI generating devices, where each EMI generating device generates EMI having substantially similar characteristics relative to EMI generated by other EMI generating devices in the system. Each EMI generating device is controlled by a controller that is configured to emulate at least partly a live cellular network.
    Type: Application
    Filed: May 7, 2010
    Publication date: November 11, 2010
    Inventor: Andrew N. Lemmon
  • Patent number: 7804304
    Abstract: A method for measuring the noise factor (FDUT) of a device under test, which requires exclusively a network analyzer. The noise factor (FDUT) is calculated from the internal noise (NNWA) of the network analyzer determined in a calibration process, the power amplification (GDUT) of the device under test determined by measuring the S-parameters of the device under test, and the measured value (PNOISE) of the noise output (NNWA) applied at a first gate of the device under test without exciting the device under test with a noise signal.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 28, 2010
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Werner Held
  • Publication number: 20100231233
    Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.
    Type: Application
    Filed: February 17, 2010
    Publication date: September 16, 2010
    Applicant: QUALCOMM INCORPORATED
    Inventor: Sachin D. Dasnurkar
  • Patent number: 7791330
    Abstract: An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, the circuit including a latch for latching and comparing the arrival time of the signal of interest to the reference clock, a clock counter in signal communication with the latch for counting the number of reference clock cycles received and latched, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, middle stages, and a last stage, and a voltage controller in signal communication with at least one of the middle stages of the delay chain for controlling the delay of the arrival time of the reference clock, wherein the voltage controller controls the first and last stages of the delay chain to retain a full voltage swing independent of the delay.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: David F. Heidel, Keith A. Jenkins
  • Publication number: 20100194405
    Abstract: A noise measurement system in power stabilization network, a variable filter applied to the same and a method for measuring noise in power stabilization network are disclosed, wherein the system comprises: a power stabilization network including a power input unit for receiving an external power, a power output unit for supplying a power to a power line communication modem and an output unit for a measurement instrument; a filter connected to the power stabilization network; and an EMI (Electromagnetic Interference) measurer.
    Type: Application
    Filed: December 9, 2009
    Publication date: August 5, 2010
    Inventor: Young Gyu Yu
  • Publication number: 20100188103
    Abstract: The effect of chattering on the measurement of the pulse period is reduced. The pulse period representing the rise interval of target pulses appearing in a pulse signal PI is measured. The pulse signal PI is sampled in synchronization with a measurement clock CLK. Measurement of a designated inhibition period is started in synchronization with the fall of the signal PI. Measurement of the current pulse period is completed and measurement of a new pulse period is started if the inhibition period has elapsed at the rise of the signal PI. Counting of the current pulse period is continued if the inhibition period has not elapsed.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 29, 2010
    Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.
    Inventor: Kazumasa Takai
  • Patent number: 7741828
    Abstract: A method and apparatus are disclosed for detecting disturbances in an alternating current (AC) supply. A method includes a step of indicating a relationship between supplied AC voltage and a threshold voltage for at least a portion of each cycle of the supplied AC voltage. A circuit for detecting disturbances in supplied alternating current (AC) is provided. The circuit includes a threshold detector coupled to a source of supplied AC. The threshold detector provides a signal indicating a relationship of the supplied AC levels to a threshold level for at least a portion of each cycle of the supplied AC.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: June 22, 2010
    Assignee: Thomson Licensing
    Inventor: Brian Albert Wittman
  • Publication number: 20100127714
    Abstract: A flicker noise test system includes a guarded signal path and an unguarded signal path selectively connectable to respective terminals of a device under test. The selected signal path is connectable a terminal without disconnecting cables or changing probes.
    Type: Application
    Filed: November 16, 2009
    Publication date: May 27, 2010
    Inventors: Kazuki Negishi, Mark Hansen
  • Patent number: 7719288
    Abstract: A device for measuring and isolating noise-creating imbalances in a paired telecommunications line has an internal circuit which comprises a balanced center tapped termination consisting of precisely equal resistor pairs. The circuit includes an adjustable sine wave burst generator which generates a low voltage longitudinal ac signal that is transmitted across the balanced pathways. A differential amplifier in the circuit measures this difference and displays it in units of noise or balance. The output of the differential amplifier is transmitted to an analog-to-digital converter. A microprocessor collects the samples in an array, and filters the results for presentation on a display. Advantageously, the microprocessor provides for adjustable and selectable bandpass filtering.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: May 18, 2010
    Assignee: Greenlee Textron Inc.
    Inventor: Robert Crick
  • Patent number: 7688057
    Abstract: An analysis circuit in an electromagnetic flowmeter provides diagnostic operating conditions and identifies one or more of the diagnostic operating conditions for which the coil current is stable during a sample interval. A diagnostic operating condition is selected as a measurement operating condition as a function of a noise floor measurements of the electrode voltage.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: March 30, 2010
    Assignee: Rosemount Inc.
    Inventors: Scot R. Foss, Robert K. Schulz
  • Publication number: 20100060296
    Abstract: Depending on a sensor signal, a noise signal which suppresses a useful signal spectrum of the sensor signal is determined by filtering using a filter. A noise variable, which is a measure of a noise of the sensor signal, is determined depending on the noise signal. An error of the sensor signal is identified depending on the noise variable determined.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 11, 2010
    Inventors: Zheng-Yu Jiang, Matthias Kretschmann, Herbert Preis, Christoph Resch
  • Patent number: 7675293
    Abstract: Disclosed are methods and apparatuses for determining an impedance of an energy-output device using a random noise stimulus applied to the energy-output device. A random noise signal is generated and converted to a random noise stimulus as a current source correlated to the random noise signal. A bias-reduced response of the energy-output device to the random noise stimulus is generated by comparing a voltage at the energy-output device terminal to an average voltage signal. The random noise stimulus and bias-reduced response may be periodically sampled to generate a time-varying current stimulus and a time-varying voltage response, which may be correlated to generate an autocorrelated stimulus, an autocorrelated response, and a cross-correlated response. Finally, the autocorrelated stimulus, the autocorrelated response, and the cross-correlated response may be combined to determine at least one of impedance amplitude, impedance phase, and complex impedance.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: March 9, 2010
    Assignee: Battelle Energy Alliance, LLC
    Inventors: Jon P. Christophersen, Chester G. Motloch, John L. Morrison, Weston Albrecht
  • Publication number: 20100026316
    Abstract: Second and third ports of a network analyzer are individually connected via cables to predetermined connection points on a differential transmission circuit on an object to be measured. A differential cable is connected to the differential transmission circuit. An antenna for receiving an electromagnetic wave radiated from the differential cable is connected to a first port of the network analyzer via a first cable. The network analyzer measures a three-port S parameter of the first, second, and third ports and calculates common-mode and normal-mode components of noise radiated from the differential cable. As a result, the source of noise in an electronic apparatus can be determined, and common-mode noise and normal-mode noise can be separately measured.
    Type: Application
    Filed: October 16, 2009
    Publication date: February 4, 2010
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Ko Yamanaga, Takahiro Azuma
  • Publication number: 20090278551
    Abstract: Embodiments of capacitive sensors (500, 600) and methods for reducing noise in capacitive sensors are provided. Embodiments of capacitive sensors include a gain stage (510, 610), a capacitive sensor output, and an active filtered-sampling stage (550, 650). The an active filtered-sampling stage includes a first resistive element (555, 655) coupled to the gain stage output, a second resistive element (565, 670) coupled to the capacitive sensor output, a node (560, 660) between the first and second resistive elements, and a switch (575, 675) selectively coupling the first node to an integrator circuit (550, 650), where the integrator circuit is coupled to the capacitive sensor output.
    Type: Application
    Filed: July 22, 2009
    Publication date: November 12, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Dejan Mijuskovic, Liviu Chiaburu
  • Patent number: 7598764
    Abstract: A transistor arrangement having a multiplicity of transistors interconnected with one another, having a noise detection device, which is set up for detecting the 1/f noise of at least one portion of the transistors, having a selection device, which is set up for selecting at least one of the transistors, on the basis of the ascertained 1/f noise characteristic of the transistors, in the case of which the 1/f noise is sufficiently low.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: October 6, 2009
    Assignee: Infineon Technologies AG
    Inventor: Ralf Brederlow
  • Patent number: 7583088
    Abstract: An apparatus and method are provided for reducing noise in a capacitive sensor (200). One apparatus includes a gain stage (210) including an output, the gain stage configured to generate a first signal having a noise component and a second signal having a desired output component and the noise component, and a filtered-sampling stage (250) having an input coupled to the gain stage output, the filtered-sampling stage configured to sample the first signal, store the first signal, and subtract the first signal from the second signal to produce a desired output signal. A method includes generating a first signal having a first noise component of the gain stage (710), storing the first signal (725), generating a second signal comprising a desired output component and the first noise component (730), and subtracting the first signal from the second signal to produce a first output signal having the desired output component (750).
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: September 1, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dejan Mijuskovic, Liviu Chiaburu
  • Patent number: 7579843
    Abstract: Methods and apparatus for analyzing electrical insulation of an electrical machine are provided. The method includes receiving a first signal that includes a plurality of partial discharge pulses from the electrical machine and a plurality of noise pulses, receiving other signals that includes information relative to at least one process parameter associated with the electrical machine, determining the plurality of partial discharge pulses from the plurality of noise pulses, identifying characteristics of the plurality of partial discharge pulses relating to the location and character of partial discharges in the electrical machine, and determining a condition of the electrical insulation using the identified characteristics and the received information relative to at least one process parameter.
    Type: Grant
    Filed: October 13, 2006
    Date of Patent: August 25, 2009
    Assignee: General Electric Company
    Inventors: Abdelkrim Younsi, Sameh Ramadan Salem
  • Patent number: 7569780
    Abstract: A force-measuring device (100) with at least one housing (20) has an interior space and at least one force-measuring cell (110) installed therein. At least one parameter characterizing an existing high-frequency electromagnetic field is determined by a sensor (50) arranged in the interior space or a sensor arranged outside of the housing, the sensor being adapted for detecting high-frequency electromagnetic fields. After an electromagnetic field is detected and compared to a threshold value, a response action of the force-measuring device is triggered if the detected parameter value exceeds the threshold value.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 4, 2009
    Assignee: Mettler-Toledo AG
    Inventors: Hans-Peter Von Arb, Jean-Christophe Emery, Daniel Reber, Cyrill Bucher, Stefan Buehler, Hansruedi Kuenzi
  • Patent number: 7554338
    Abstract: Time variation of phase noise characteristics is displayed for measurement. A peak power of a signal under test is detected to define the frequency as a reference frequency. An offset frequency from the reference frequency is repetitively changed and each time the phase noise power is integrated for a predetermined frequency width to evaluate an integration value. The integration values are divided by the predetermined frequency width. The divided values are further divided by the peak power to evaluate noise power ratios relative to the peak power. Then, relationship between the offset frequencies, noise characteristic values and time is displayed in a graph that shows the time variation of the phase noise characteristics.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: June 30, 2009
    Assignee: Tektronix, Inc.
    Inventor: Akira Nara
  • Publication number: 20090134883
    Abstract: A method for testing a noise immunity characteristic of an analog circuit of an integrated circuit. The device includes: an analog circuit, an internal stable reference signal source, an internal power supply module connected to the analog circuit and adapted to receive, via first input, a high level voltage supply, the device is characterized by including: a signal modulator that is adapted to provide, during a test period, a noisy signal to a second input of the internal power supply module; whereas the internal power supply module is adapted to output a noisy power supply to the analog circuit, in response to the noisy signal; whereas device is adapted to output an output signal representative of a noise immunity characteristic of the analog circuit. The method includes: providing a high level supply voltage to a first input of an internal power supply module of an integrated circuit and receiving signals from the integrated circuit representative of the performance of the analog circuit.
    Type: Application
    Filed: February 9, 2006
    Publication date: May 28, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Sergey Sofer, Yehim-Haim Fefer, Valery Neiman
  • Publication number: 20090102490
    Abstract: The present invention provides a circuit for performing a stress test on a paired line. The circuit provides for first and second balanced outlet pathways for applying an AC signals to the paired line. Although each of these first and second balanced outlet pathways include balanced capacitors, the need to vet these capacitors in order to achieve proper operation of the circuit is eliminated.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 23, 2009
    Inventors: Curtis Clifford Taylor, Edwin Glenn Yancey
  • Publication number: 20090079441
    Abstract: An electronic circuit includes several (at least two) oscillating and/or resonant devices. The circuit uses a measuring device to measure the phase noise of one of the two oscillating/resonant devices. This measuring device is integrated on a chip on which said oscillating/resonant device to be measured is also integrated. The circuits and methods described find application in the area of radiofrequency/high frequency electronics RF/HF, in particular adapted to general public applications in mobile communication systems and/or to metrology.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 26, 2009
    Inventors: Andrea Cathelin, Sylvain Godet, Olivier Llopis, Eric Tournier, Stephane Thuries
  • Patent number: 7443173
    Abstract: Various embodiments for radio frequency (RF) noise cancellation are described. In one embodiment, an apparatus may comprise an RF noise cancellation system arranged to sense platform noise observed by a radio subsystem, create an inverse version of the sensed platform noise, and add the inverse version of the sensed platform noise to a received RF signal to remove the platform noise from the received RF signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventor: Gregory L. Ebert
  • Patent number: RE42872
    Abstract: A plurality of battery-operated transceivers encapsulated by lamination to form a sheet of independent transceivers is tested in a two piece fixture that forms an enclosure surrounding each in-sheet transceiver. Each enclosure has an antenna for transmitting a command signal to the transceiver at a known power level and for receiving a reply message from the transceiver containing a power level measurement made by the transceiver. Test methods using the fixture of the present invention are also described. Flexible radio frequency identification (RFID) devices are coupled to a roll of flexible material. Each RFID device coupled to the roll is advanced into a wireless communication region. An antenna in the region separately communicates with each of the RFID devices in a manner that isolates the communication from other REID devices counted to the roll outside the region.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: October 25, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Mark E. Tuttle, Rickie C. Lake, Steven F. Schicht, John R. Tuttle