Abstract: A memory chip is applied to the memory system, and the memory chip is configured to perform counting and obtain a count value after the memory chip is powered on and started, wherein the count value is used to represent a process corner of the memory chip, the memory chip further has a reference voltage with an adjustable value, the value of the reference voltage is adjustable based on the count value, and the memory chip adjusts, based on the reference voltage, a delay from reading out data from a memory cell to outputting the data through a data port.

Abstract: A test and measurement instrument including a signal generator configured to generate a waveform to be sent over a cable to a device under test (DUT) and a real-time waveform monitor (RTWM) circuit. The RTWM is configured to determine a propagation delay of the cable, capture a first waveform, including an incident waveform and a reflection waveform at a first test point between the signal generator and the DUT, capture a second waveform including at least the incident waveform at a second test point between the signal generator and the DUT, determine a reflection waveform and the incident waveform based on the first waveform and the second waveform, and determine a DUT waveform based on the incident waveform, the reflection waveform, and the propagation delay. The DUT waveform represents the waveform generated by the signal generator as received by the DUT.

Abstract: A method for testing a temperature measuring instrument is presented, where the instrument includes at least one sensor that changes its electrical resistance, and/or an electrical voltage that it produces, in response to being exposed to a change in temperature, and where the instrument is configured to be coupled to an object of interest. The method includes changing the temperature of at least one sensor by an amount that is detectable given the measurement resolution of the at least one sensor, by driving an electrical manipulation current through this sensor; obtaining one or measurement values from at least one sensor; and evaluating a state of the measuring instrument, a state of one or more of its sensors, and/or a state of a coupling to an object of interest, from the one or more measurement values.

Abstract: Embodiments of the invention provide a pulsed-output constant voltage LED driver comprising a PDM stage configured to provide power to an LED load by supplying energy at either a first or second predetermined voltage during each of a plurality of segments of a predetermined time period, wherein the number of segments during which the first voltage is supplied is correlated with the power provided to the LED, and wherein the positions within the time period of the segments during which the first voltage is applied are random.

Abstract: A test device determines error in a fronthaul network of a radio access network. A first Global Navigation Satellite System (GNSS) receiver receives GNSS signals from a GNSS satellite through a reference GNSS signal distribution system (GSDS) having a known signal propagation delay. The first GNSS receiver calculates and outputs a corresponding reference One Pulse Per Second (1 PPS) signal. A second GNSS receiver receives the GNSS signals through a device under test including a GSDS having an unknown signal propagation delay. The second GNSS receiver calculates and outputs a corresponding DUT 1 PPS signal. The test device determines the unknown signal propagation delay of the DUT by comparing the reference 1 PPS signal to the DUT 1 PPS signal.

Abstract: A hardware in the loop simulation and test system that includes a phased array antenna simulation system providing dynamic range and angle of arrival signals simulation and synchronizing for input into a system under test (SUT) that includes a phased array signal processing system along with related methods. Embodiments include system elements that increase precision of signal simulation to include reduced error in angular resolution.

Abstract: Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.

Abstract: A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components configured to conduct a signal. A test device is configured to obtain values of the component test structure and to perform operations on these values.

Abstract: A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.

Abstract: A system for measuring noise characteristics of a device under test (DUT) includes one or more computers and memory, a first receiver connected to a first port of the DUT, a second receiver connected to a second port of the DUT, the second receiver being synchronized with the first receiver and a non-transitory computer readable storage medium having instructions thereon that when read and executed by the one or more computers causes the system to transmit signals to the DUT, receive signals from the DUT, and characterize noise associated with the DUT within the received signals.

Abstract: A method and system is disclosed for measuring a characteristic loop sensitivity (SLC) for an acoustic transducer. A pulse signal is employed as a wideband reference signal Vr(t); and, in a pulse-echo measurement a corresponding wideband echo signal Ve(t) is obtained. A characteristic loop sensitivity (SLC) for the acoustic transducer is defined as a ratio of an energy density of Ve(t) to an energy density of Vr(t) in decibel, in which the energy density of a given signal is calculated as a ratio of an energy of the signal to a bandwidth of the signal.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transmit signals in isolated gate drivers. An example apparatus includes a first encoder including: an edge detector coupled to a first sensor; a first clock counter coupled to the edge detector; a first signal selector coupled to the first clock counter; and a first multiplexer coupled to a signal generator, the first clock counter, and the first signal selector; and a second encoder including: a level detector coupled to a second sensor; a second clock counter coupled to the level detector; a second signal selector coupled to the level detector and the second clock counter; and a second multiplexer coupled to the first multiplexer, a reference voltage, the second signal selector, and a modulator.

Abstract: In one embodiment, a method includes: obtaining a power loss value for a cable that couples a device to a power source, where the power loss value is indicative of an amount of power lost through the cable during power transmission from the power source to the device; and determining, based at least in part on the power loss value for the cable, a power budget value indicative of an amount of power received by the device from the power source.

Abstract: A method for measuring hydrogen concentration in a gas includes exposing a PdNi alloy thin-film gas sensor to the gas, alternately controlling the temperature of the PdNi alloy thin-film gas sensor between a first temperature for a first period of time and a second temperature for a second period of time while the PdNi alloy thin-film sensor is exposed to the gas, continuously monitoring the resistance of the PdNi alloy thin-film gas sensor during the first and second periods of time, and calculating the hydrogen concentration as a function of a transient in the resistance of the PdNi alloy thin-film sensor measured at a time that the temperature transitions between the first temperature and the second temperature.

Abstract: A semiconductor device includes a period defining block suitable for generating a period defining signal corresponding to a predetermined test time period based on a test mode signal and one or more command signals; and a monitoring block suitable for generating a monitoring signal corresponding to an oscillation signal during the test time period based on the period defining signal.

Abstract: A Power over Ethernet method and device, where the Power over Ethernet method includes: determining, by PSE, a maximum power of a PD according to a classification class of the PD; obtaining, by the PSE, a length of a network cable between the PSE and the PD; determining, by the PSE, a type of the network cable; calculating, by the PSE, a loss power of the network cable according to the length of the network cable and the type of the network cable; and using, by the PSE, a sum of the maximum power of the PD and the loss power of the network cable as a supply power, to supply power to the PD. The Power over Ethernet method and device provided in the present disclosure improves usage efficiency of the PSE supply power.

Abstract: A method and apparatus for simulating radio frequency propagation paths between radio frequency devices are provided. In an illustrative embodiment, the apparatus comprising a system controller for receiving and processing test data, a data sequencer configured to interact with attenuators and RF devices, and RF paths designed to simulate RF propagation paths. The method comprising steps to execute a full simulation.

Abstract: A method and apparatus for simulating radio frequency propagation paths between radio frequency devices are provided. In an illustrative embodiment, the apparatus comprising a system controller for receiving and processing test data, a data sequencer configured to interact with attenuators and RF devices, and RF paths designed to simulate RF propagation paths. The method comprising steps to execute a multiple propagation path simulation based on various inputs including attenuators and electromagnetic environment inputs in accordance with various embodiments.

Abstract: A device comprises a coarse timing skew characterization circuit having a buffer chain and a coarse delay cell calibration circuit comprising a first flip-flop, a second flip-flop and a logic gate, wherein the coarse delay cell calibration circuit is configured to measure a delay between an input of the buffer chain and an output of the buffer chain.

Abstract: The invention relates to a DC-DC converter which is designed to supply a low-voltage network comprising a low-voltage battery and a battery sensor circuit with a low voltage, having a pulse generation device which is designed to feed electrical pulses into the low-voltage network in order to test the low-voltage battery using the battery sensor circuit.

Abstract: An integrated circuit die has one or more through-body-vias and a testing circuit on board the die which tests for defects in a through-body-via by driving of pulses of current into a node. Pulses are counted until the voltage of the node reaches a threshold voltage to provide a pulse count which is a function of the capacitance of the node. A determination is made as to whether the through-body-via of the node has a defect as a function of the pulse count.

Abstract: Systems, methods, and other embodiments associated with testing a cable are described. According to one embodiment, an integrated circuit device includes a transmitter, a receiver, cable tester logic and a cable test control logic. The transmitter is configured to transmit signals to a cable. The receiver is configured to receive signals from the cable. The cable tester logic includes an echo tester configured to identify peaks corresponding to echo canceller coefficients that model an impulse response of reflected signals received by the receiver and a power-based cable tester configured to determine a power-based cable length based on an attenuation of a signal received from the link partner. The cable test control logic is configured to selectively activate one or both of the echo tester and the power-based tester and to determine a cable length based, at least in part, on the power-based cable length and the identified peaks.

Abstract: A method including determining a test duration for testing each of a plurality of memory arrays individually coupled to a plurality of array built-in-self test (ABIST) engines, the test duration is equal to a time period required by each of the plurality of ABIST engines to test each of the plurality of memory arrays, determining a corresponding delay value for each of the plurality of ABIST engines, each of the corresponding delay values is based on the test duration for each of the plurality of memory arrays, and consecutively delaying the start of processing of each of the plurality of ABIST engines by providing each of the corresponding delay values to each of a plurality of programmable delay units individually coupled to each of the plurality of ABIST engines, the start of processing of each of the plurality of ABIST engines is delayed by a different corresponding delay value.

Abstract: A test system (and methodology) suitable for testing a resonant sensor circuit configured to drive a sensor resonator with a negative resistance. Example embodiments include a test sensor resonator setup configured to simulate a sensor resonator with a selectable loss factor Rs, and includes, in a single-ended configuration, a first oscillator signal source that generates a first oscillation signal, coupled to a first controllable resistor that provides a controlled resistance R1 that simulates a selectable sensor resonator loss factor Rs, which together generate a first oscillation voltage signal based on the controlled resistance R1. A DUT resonant sensor circuit is coupled to receive the first oscillation voltage signal at a first input, and generate a negative resistance ?Ra that substantially counterbalances the resistance R1 (corresponding to sustained oscillation).

Abstract: A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.

Abstract: A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.

Abstract: A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

Abstract: Distance between two devices is determined by sending a digital signal from a first device to a second device, and receiving a repeated signal from the second device in the first device. The repeated signal includes the digital signal sent from the first device resent by the second device. A time difference between the sent digital signal and the received repeated signal is determined by providing both the sent digital signal and the received repeated signal to a logic gate, the output of the logic gate indicating whether the digital signal and the received repeated signal are at same or different states. The output of the logic gate is evaluated to determine an approximate distance between the first device and the second device.

Abstract: A method uses time-domain reflectometry to measure a signal reflection delay in a conductive trace formed on a specific passive printed circuit board, and uses the measured signal reflection delay as an index into a table storing a predetermined association between signal reflection delay and passive printed circuit board manufacturing information, wherein the table includes a plurality of predetermined signal reflection delay values, and wherein each of the predetermined signal reflection delay values is associated with unique passive printed circuit board manufacturing information. During manufacturing of the passive printed circuit board, a hole is drilled through the passive printed circuit board so that the hole intersects with the conductive trace and divides the conductive trace into a proximal segment extending from the connector to the hole and a distal segment that is electrically isolated from the proximal segment by the hole.

Abstract: Techniques for obtaining a propagation delay through first and second transmission lines having substantially equal propagation delays may include: providing a first signal to the first transmission line; providing a second signal to the second transmission line; detecting an incident edge of the first signal on the first transmission line; detecting a reflected edge of the second signal on the second transmission line; and determining the propagation delay based on times of detection of the incident edge and detection of the reflected edge.

Abstract: A circuit includes a signal generator, a delay pulse generator and a time-to-current converter. The signal generator is configured to generate a first signal including information on a rise delay and a second signal including information on a fall delay. A delay difference exists between the rise delay and the fall delay. The delay pulse generator is configured to provide an additional delay to one of the first and second signals. The time-to-current converter is configured to extract the delay difference.

Abstract: A method is provided for detecting a state of a connection between an electrically driven motor vehicle (1) and a corresponding charging station. The motor vehicle (1) has a control pilot (CP) function with a vehicle-side control pilot (CP) line (3). The method includes using a power line communication (PLC) chip (2) of the motor vehicle (1) to measure the length of a control pilot line between the motor vehicle and the charging station.

Abstract: Systems and methods for transition delay measuring are presented. A transition delay measuring method can include oscillating a signal between states and tracking an indication associated with an isolated attribute of the transitions between the states. Oscillations can include asymmetric transitions between the states and the tracked isolated attribute can be a delay in completing transitions between the states in one direction or vice versa. The asymmetric transitions can include transitions between the first state and the second state that are faster than slower transitions between the second state and the first state or vice versa. The tracked indication can be utilized in analysis of the isolated transition delay characteristics. The results can be utilized in analysis of various further features and characteristics (e.g., examination of leakage current related power consumption, timing of asymmetric operation, etc.). The analysis can include examination of fabrication process and operating parameters.

Abstract: A novel and useful direct memory based ring oscillator (DMRO) circuit and related method for on-chip evaluation of SRAM delay and stability. The DMRO circuit uses an un-modified SRAM cell in each delay stage of the oscillator. A small amount of external circuitry is added to allow the ring to oscillate and detect read instability errors. An external frequency counter is the only equipment that is required, as there is no need to obtain an exact delay measurement and use a precise waveform generator. The DMRO circuit monitors the delay and stability of an SRAM cell within its real on-chip operating neighborhood. The advantage provided by the circuit is derived from the fact that measuring the frequency of a ring oscillator is easier than measuring the phase difference of signals or generating signals with precise phase, and delivering such signals to/from the chip. In addition, the DMRO enables monitoring of read stability failures.

Abstract: Various embodiments concern a method for forming a trace array by modeling a trace array having a plurality of traces, each trace having a plurality of trace segments corresponding to elements of a filter circuit having alternating high and low impedance elements. The alternating high and low impedance elements can correspond to inductors and capacitors. For each trace segment, a delay constant is measured between a plurality of nodes that are longitudinally arrayed along the trace segment. The delay constant can be a phase delay. The length of each trace segment is set based on the delay constant of the trace segment. The length of each trace segment can be set such that the trace has a linear group delay response across an operational frequency range of the flexure. A trace array is then formed based on the set lengths.

Abstract: A timing skew characterization apparatus comprises a coarse timing skew characterization circuit, a fine timing skew characterization circuit and a coarse delay cell calibration circuit. The coarse timing skew characterization circuit comprises a plurality of coarse delay cells whose delays can be calibrated through the coarse delay cell calibration circuit. The calibration of fine delay cells can be implemented through a trail and error process. Both coarse delay step and fine delay step can be characterized through a single measurement setup. As a result, the timing skew characterization apparatus provides a high resolution setup and hold time measurement.

Abstract: A voltage polarity determination circuit includes an integration circuit, a switch, and a time measurement circuit. The integration circuit includes an operational amplifier circuit having an input offset voltage which is larger than the maximum value of a voltage input to the integration circuit or smaller than the minimum value of the input voltage of the integration circuit. The switch switches the input voltage of the integration circuit between a voltage whose polarity is to be determined and a reference voltage. The time measurement circuit measures a time interval which it takes for the output voltage of the integration circuit to reach a set voltage, and based on the result of the measurement, determines the polarity of the input voltage of the integration circuit.

Abstract: A measure initialization path for a delay line structure includes: a forward path, comprising a plurality of delay stages coupled in series; a first output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path; and a second output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path. When a signal is propagated through the measure initialization path, the signal successively propagates through a delay stage of the forward path, a delay stage of the first output path and a delay stage of the second output path for performing measure initialization.

Abstract: An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test.

Abstract: Provided is a test apparatus that tests a device under test having a plurality of output terminals. The test apparatus comprises an executing section that executes a test command sequence for testing the device under test; a storage section that stores a plurality of pieces of setting data designating one or more output terminals among the plurality of output terminals; a detecting section that detects whether a value of an output signal from an output terminal designated by one of the pieces of setting data matches an expected value; and a selecting section that selects different pieces of setting data in the storage section when at least two detection commands, which change execution sequencing of the test command sequence according to the detection results of the detecting section, are executed, and supplies the selected pieces of setting data to the detecting section.

Abstract: An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test.

Abstract: A method for monitoring operation of a solenoid valve having an armature and a poppet coupled to the armature includes the steps of energizing a coil in the valve to generate a current signature reflecting current vs. time, detecting a first inflection point in the current signature, wherein the first inflection point occurs when the armature starts to move from one of the open and closed positions toward the other of the open and closed positions, and detecting a second inflection point in the current signature. The second inflection point occurs when the armature moves completely to the other of the open and closed positions. In one embodiment, the first inflection point indicates when the valve begins to open, making it possible to accurately determine the elapsed opening time of the valve.

Abstract: A delay tracker utilizes a special code on the tracked signal in order to recognize such signal and ascertain any delays associated therewith.

Abstract: A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element to maintain a constant voltage across the resistive element. The charge reservoir is connected to the voltage supply to provide a current through the resistive element. The current source is connected to the charge reservoir to repeatedly supply a pulse of current to recharge the reservoir upon depletion of electronic charge from the reservoir, and the pulse counter provides a count of the number of pulses supplied by the current source over a predetermined time. The count represents a logic state of the memory cell element.

Abstract: A high speed test circuit receives a tester clock from a tester and it conducts a test on a circuit under test. The high speed test circuit generates a high frequency clock according to the tester clock, so it is capable of operating in two frequencies. The high speed test circuit tests the circuit under test according to the high frequency clock, and it performs a low speed operation according to a low frequency clock, which is for example the tester clock.

Abstract: A method and apparatus for determining at least one property of a target material is disclosed. The method is constituted of: providing a time varying signal at comprising frequency content over a range of frequencies; transducing the provided signal so as to interact with the target material; receiving the provided time varying signal after interaction with the target material; mixing the received time varying signal with a portion of the provided time varying signal; determining the propagation delay associated with the target material of the received provided time varying signal at each of a plurality of frequencies within the range of frequencies; and determining at least one property of the target material responsive to the determined propagation delay at each of the plurality of frequencies.

Abstract: An integrated circuit includes a circuit aging sensor that provides information regarding operational degradation of the integrated circuit due to aging. The aging sensor includes a ring oscillator that includes inverting drivers and tuning circuits. The drivers are sequentially coupled to form a ring. An output of each of the drivers is coupled to an input of one of the tuning circuits, and an input of each of the drivers is coupled to an output of one of the tuning circuits. Each of the tuning circuits includes a first signal path and a second signal path. The first signal path selectably applies a tuning delay to an input signal received from one of the drivers for provision to an input of a successive one of the drivers. The second signal path selectably routes the signal received around the tuning delay to the input of the successive one of the drivers.

Abstract: A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file.

Abstract: Example embodiments relate to a method performed by an apparatus for analyzing time of a semiconductor chip. The method may include defining a netlist, defining time delays of devices defined in the netlist, performing a normality test using the time delays, judging a p-value based on the normality test, and determining a time delay of the semiconductor chip.

Abstract: Prediction of a channel capacity is accomplished based on a TDR echo without explicitly estimating the topology of the line. The prediction is based on obtaining a measured TDR echo, determining a theoretical TDR echo for a plurality of loop lengths, estimating the equivalent TDR length based on an optimization, updating the equivalent TDR length and utilizing the updated TDR length to predict one or more of the upstream and downstream data rates.