Abstract: Disclosed approaches for dynamically creating one or more scan chains in a programmable integrated circuit (IC) include placing elements of a circuit design on first registers of the programmable IC. A processor can determine second registers of the programmable IC that are unused by the circuit design after placing the elements of the circuit design. Data-out pins of the first registers are coupled to data-in pins of the second registers, respectively, and the second registers are coupled into a scan chain.

Abstract: A method of detecting a fault in a circuit design undergoing emulation, includes in part, computing N signatures of a corresponding reference circuit design during each of the N cycles, computing N signatures of the circuit design undergoing emulation during each of the N cycles, comparing, for each of the N cycles, the signature of the reference circuit design to the signature of the circuit design undergoing emulation, and detecting whether a mismatch exists between the reference circuit design signature and the signature of the circuit design undergoing emulation during each of the N cycles. The method further includes comparing the signatures of the submodules of the reference circuit design to the signatures of the corresponding submodules of the circuit design undergoing emulation to enable root causing submodule functional failures. Optionally, each signature may computed by performing a logic function on a multitude of output signals of the circuit design.

Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

Abstract: The independent claims of this patent signify a concise description of embodiments. A hardware emulation system is configured to define a variable delay associated with each of a multitude of design clocks used in the circuit design, compute a compression value in accordance with the multitude of variable delays, detect a change in one or more of the variable delays, and recompute the time compression value in response to the detected change. The hardware emulation system is further configured to recompute the time compression using programmable circuitry disposed in the hardware emulation system and without stopping the hardware emulation system. Such circuitry may be disposed in a single programmable device disposed in the hardware emulation system or a multitude of programmable devices disposed in the hardware emulation system. This Abstract is not intended to limit the scope of the claims.

Abstract: A method of detecting a fault in a circuit design undergoing hardware emulation, includes, in part, comparing, in each cycle K of a clock and at the hardware emulation system, the cycle K register values of a reference circuit with the cycle K register values of the circuit design undergoing emulation. The method further includes detecting, in each cycle K of the clock and at the hardware emulation system, whether a mismatch exists between the cycle K reference circuit design register values and the cycle K register values of the circuit design undergoing emulation. Alternatively the comparison may be made between the respective signatures computed from the register values. The register values of the reference circuit design for all K cycles may be transferred to the emulation system prior to emulation. Alternatively, for each cycle K, the register values may be transferred to the hardware emulation system during that cycle.

Abstract: A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

Abstract: A technology is described for a device diagnosis station. The device diagnosis station may be configured to identify an electronic device physically connected to the device diagnosis station, evaluate an operational state of the electronic device by executing testing instructions configured to test the functionality of the electronic device and collect operational state information for the electronic device. The device diagnosis station may be configured to determine the operational state of the electronic device and execute recovery instructions to restore the electronic device to an improved state when a recoverable error is detected. The device diagnosis station may be configured to initiate a device return procedure for the electronic device when a non-recoverable error state is detected.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: Electrical component location is provided. Employed location techniques may include providing a cycling signal, having components to be located sense the cycling signal at the same time, report back the sensed signal, and determining relative locations for one or more of the components using the sensed signals reported by the components.

Abstract: A printed circuit board includes a substrate and at least one electrical circuit provided at least partially on a surface layer of the printed circuit board. The electrical circuit includes an electrical trace that is in electrical connection with a test pad provided for accessibility on the surface layer, the test pad being sized and shaped for probing to test an aspect of the circuit, the test pad having a conductive probe surface that is structured to provide at least one vertical surface that extends from the probe surface toward the surface layer and thus providing an edge between the vertical surface and the probe surface, the probe surface having a coating of a material to protect the conductive probe surface from corrosion.

Abstract: According to a synchronization method, a basic timing signal generation circuit generates a basic timing signal. A communication control circuit generates a first communication cycle timing signal, measures an input difference between the basic timing signal and a predetermined one of first communication cycle timing signals, divides a compensation value responsive to the input difference by the number of first communication cycle timing signals, adds up a value resulting from the division in a communication cycle, compensates for timing of generating the first communication cycle timing signal with timing equal to or greater than a predetermined value, and transmits timing compensation data to external equipment. The external equipment generates a second communication cycle timing signal, compensates for timing of generating the second communication cycle timing signal based on timing of receipt of the timing compensation data, and synchronizes with the first communication cycle timing signal.

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

Abstract: Methods, apparatuses, and systems for image-based abnormality detection for periodic patterns are provided. The method includes receiving an image pattern T determined from an inspection image, wherein T comprises multiple periodic segments along a spatial direction; determining, by a processor, a first reference pattern R1 by rearranging the multiple periodic segments of T in a first manner and a second reference pattern R2 by rearranging the multiple periodic segments of T in a second manner; determining whether an abnormality exists in T by comparing a part of T with a part of R1 and a part of R2; and determining that the abnormality exists in T based on a determination that the part of T is different from the part of R1 and the part of R2.

Abstract: An isolation device provides high common mode transient immunity without increasing the supply voltage rails in the transmitter side. In one aspect, the disclosed isolation device implements a self-boosting scheme to increase a voltage swing of a transmission signal under a lesser supply voltage rail. The disclosed isolation device includes a first stage circuit, a boost circuit, and a second stage circuit. The first stage circuit is configured to generate first and second signals each having a first voltage within a supply voltage range. The boost circuit is configured to provide a boosted voltage range greater than the supply voltage range responsive to at least one of the first or second signal. The second stage circuit is configured to generate an output signal based on either one of the first or second signal, such that the output signal has a second voltage within the boosted voltage range.

Abstract: A method for automatically testing a voltage regulator, including: providing an auto-test setting to a test master, wherein the auto-test setting specifies an auto-sweep setting and a loop comprising an ordered set of serial command frames; producing, in the test master, a test suite comprising a plurality of serial command frames by executing the loop multiple times according to the auto-sweep setting until an array of a preset variable corresponding to the auto-sweep setting is traversed, wherein the preset variable is changed in each iteration of the loop; sequentially transmitting every serial command frame to the voltage regulator; and receiving every resulting behavior of the voltage regulator when operated in accordance with the every serial command frame.

Abstract: A method, computer program product, and system for emulating a constant power (CP) electronic load (e-load) from a constant current (CC) e-load are disclosed. Testing metrics may be obtained for a power source to be tested, including one or more power thresholds. Further, an initial current level for a CC e-load may be obtained. The power-draw of the CC e-load connected to the power source may be determined. The determined power-draw may be compared to at least one of the one or more of the power thresholds. In response to the power-draw not satisfying the at least one power threshold, the current level of the CC e-load may be adjusted based on the power-draw and the at least one power threshold.

Abstract: Systems and methods are described for calculating a propagation delay of a transmission line. A transmitter may transmit a signal from a first end of a transmission line to a second end of the transmission line at a first time, t1. A signal reflection device (e.g., a passive resonator) connected to the second end of the transmission line may generate a reflection at a second time, t2. A reflection detector (e.g., a matched, passive resonator) at the first end of the transmission line may receive the reflection from the signal reflection device, at a third time, t3. A propagation delay calculator may calculate the propagation delay of the transmission line as corresponding to one-half of a difference between the first time, t1, and the third time, t3.

Abstract: An example test system includes a test carrier to receive a device to test. The test carrier includes test components to perform at least a structural test on the device. The example test system also includes a slot to receive the test carrier. The slot includes an interface to which the test carrier connects to enable the test carrier to communicate with a system that is part of the test system or external to the test system.

Abstract: Systems, methods, and computer-readable media for configuring automotive lamp illumination control are provided. One example method includes, at a computing device, generating a graphical user interface for configuring at an automotive lamp illumination pattern. The graphical user interface includes user input elements and is displayed by way of a display device. An input command is received by way of at least one of the plurality of user input elements. The input command corresponds to the at least one of the user input elements. A message is transmitted to an automotive lamp control device by way of a communication path including a first communication port of the computing device and a second communication port of the automotive lamp control device, based on the received input command. The message is received at the automotive lamp control device, and an action is performed in response to receiving the message.

Abstract: A compound may include a set of integrated circuits. An integrated circuit, of the set of integrated circuits, may include calibration standards integrated at a silicon layer of the integrated circuit. The integrated circuit may be included in a package, and a calibration standard, of the calibration standards, may be available to at least one port of a set of ports of the integrated circuit.

Abstract: A device under test for performing built-in self-tests to determine the functionality of one or more components of the device under test is described. The device under test includes a storage location to store a set of tests for testing the device under test; a data generator to generate a test pattern based on a test in the set of tests; a transmission unit to transmit the test pattern to a test system; a receiver unit to receive a set of loopback signals from the test system, wherein the set of loopback signals represent the test pattern; and a data checker to determine success or failure of the device under test based on the set of loopback signals.

Abstract: Provided is an electronic device includes an interface for connection to an external device; and a processor electrically connected to the interface, wherein the at least one processor is configured to: set a first radio frequency (RF) signal port of a first chipset to operate in RF signal transmission mode, and set a second RF signal port of a second chipset to operate in RF signal reception mode; obtain an error of transmission performance of the first RF signal port based on a comparison between a designated transmission reference that is input to the first RF signal port and a characteristic of a first intermediate frequency (IF) signal that is output via the second RF signal port; obtain a first compensation value to enable the transmission performance of the first RF signal port to converge to the transmission reference, on the basis of the error of the transmission performance; and store at least one of the error of the transmission performance and the first compensation value in the first chipset via

Abstract: An inspection jig includes a rigid substrate, a flexible substrate connected to the rigid substrate, a support supporting a part of the flexible substrate in a state that the part of the flexible substrate is protruded with respect to the rigid substrate in a first direction, a biasing unit configured to bias the support in the first direction with respect to the rigid substrate, and a contactor provided on a protruding portion of the flexible substrate, the protruding portion being protruded with respect to the rigid substrate. The contactor includes a contact housing, and a probe supported on the contact housing. One end of the probe is in contact with a contact portion on the protruding portion.

Abstract: A method and device for high speed broadband testing of systems and substances using a binary, spectrally sparse sequence (SSS) as a periodic excitation waveform. The sequences with controllable frequency and magnitude spectra content are designed by component manipulation method or by edge manipulation method. The excitation waveform is typically pre-calculated, and kept in waveform memory, from where it is shifted out into digital to physical quantity converter (DQC). The sparse spectrum of the SSS makes it easy to create plenty of uncorrelated frequency sets with adjacent, but sufficiently different frequencies to form multi-path test systems, where all the paths can be measured simultaneously. The response of the sample under test (SUT) is sampled and the complex transfer function is calculated directly or indirectly via Impulse Response by Discrete Fourier Transform technique and its derivatives. The sequence bit interval and sampling interval have a predetermined ratio.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design and more specifically towards determining return path quality in an electrical circuit. Embodiments may include providing, using a processor, an electronic circuit design and identifying at least one net associated with the electronic circuit design. Embodiments may further include extracting an ideal loop inductance for the at least one net and extracting a real loop inductance for the at least one net. Embodiments may also include calculating a return path quality factor based upon, at least in part, the ideal loop inductance and the real loop inductance.

Abstract: A remote radio frequency (RF) power sensing unit including a first module and a second module. The first module may be configured to generate a digital output representative of a power level of a radio frequency (RF) signal. The second module may be configured to convert the digital output of the first module to a digital signal communicating the power level and transmit the digital signal communicating the power level over a wireless communication channel using a wireless protocol.

Abstract: The inspection jig includes a rigid substrate, a flexible substrate connected to the rigid substrate, a contactor block for supporting a part of the flexible substrate in a state that the part of the flexible substrate is protruded with respect to the rigid substrate, a contactor provided on a protruding portion of the flexible substrate, and a spring probe supported by the contactor block, one end of which is in contact with a contact pad provided on a lower surface of the rigid substrate, and the other end of which protrudes from a protruding portion of the flexible substrate.

Abstract: A distributed electrical system includes a plurality of engine components each in electrical communication with one of a plurality of docking stations. An electronic engine control is positioned remote from the engine components and is configured to communicate wirelessly with each of the plurality of engine components.

Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

Abstract: A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.

Abstract: A computer-implemented method for testing an real and/or virtual automotive system through a test by a test environment interacting with the real and/or virtual part, which includes a test series with different test cases of the test for different execution conditions that are specified in test configurations. Each combination of test case and test configuration is assigned a test status value from a group of predefined test status values in accordance with an evaluation of the function of the system in the corresponding test. For further planning, execution, and/or evaluation of the test series at least once a relative test coverage of at least one of the status values is determined in the resulting test case configuration matrix and/or a relative potential for improvement of the test coverage of at least one of the status values with regard to a test case and/or with regard to a configuration is determined.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: The present application arises from the need of associating a switching matrix comprising electromechanical relays with a switching matrix comprising solid-state relays. Disclosed herein is an automated test equipment comprising an electronic controller, at least two measuring signals, at least one switching matrix comprising at least two electromechanical relays for each test point, and at least a switching matrix comprising at least one test point and at least two solid-state relays for each test point. In this equipment, each test point in a switching matrix comprising electromechanical relays is connected to a test point of the other switching matrix comprising solid-state relays, via an electromechanical relay. In practice, a reduction by half of the test time at the low voltage step is observed.

Abstract: A method for locating electrostatic discharges occurring on an aircraft in flight including a step of recording, during the flight of the aircraft, electromagnetic signals resulting in the electrostatic discharges and received by a plurality of detectors arranged at different places on an exterior surface of the aircraft, a step of analyzing the signals recorded during the flight, each of the signals, received by the various detectors and corresponding to one and the same electrostatic discharge, are processed to identify at least one zone of an exterior surface of the aircraft, determining a structural part in which the electrostatic discharge probably occurred.

Abstract: A system and method for monitoring outlier behavior in an array of n electrodes includes an electrical line, a switching circuit via which the electrodes are individually coupleable to the electrical line, a sensor; and processing circuitry, where, in each of m iterations: (i) a respective subset of electrodes is coupled by the switching circuit to the electrical line, (ii) the sensor senses an electrical parameter produced over the electrical line by the coupled subset of electrodes, and (iii) the processing circuitry obtains from the sensor a respective value of the electrical parameter, m being less than n, and the processing circuitry identifying those of the electrodes that exhibit outlier electrical behavior by finding electrical values to individually ascribe to individual ones of the electrodes of the array, which ascribed values can result in all of the respective values of all of the m iterations.

Abstract: A stimulus/response controller within a magnetic electrical test apparatus is configured for generating and transmitting stimulus waveforms to a high-speed DAC for application to a MTJ DUT. The response signal from the MTJ DUT is applied to an ADC that digitizes and transfers the response signal to the stimulus/response controller. The stimulus/response controller has a configurable function circuit that is selectively configured for performing evaluation and analysis of the digitized stimulus and response signals. The configurable functions are structured for performing any evaluation and analysis function for determining the characteristics of the MTJ DUT(s). Examples of the evaluation and analysis operations include averaging the stimulus and/or response signals, determining the differential resistance, the degradation times, failure counts, or the bit error rate of the MTJ DUT(s).

Abstract: Disclosed are a memory device, a memory package including the same, and a memory module including the same. The memory package includes a first memory device configured to operate in response to a first chip select signal from an external device, a second memory device configured to operate in response to a second chip select signal from the external device, and a third memory device configured to operate in response to a third chip select signal from the external device. The third memory device includes a buffer unit that is connected with an internal circuit of the third memory device through an internal data line, is connected with the first memory device through a first memory data line, is connected with the second memory device through a second memory data line, and is connected with the external device through a data line.

Abstract: An automatic system level testing (ASLT) system for testing smart devices is disclosed. The system comprises a system controller coupled to and operable to stress a smart device in an enclosure, wherein the enclosure comprises a plurality of components, and wherein the system controller comprises: (a) a memory comprising test logic; and (b) a processor configured to automatically control the plurality of components and test the smart device in accordance with the test logic. Further, the plurality of components comprises: (a) a robotic arm comprising a stylus affixed thereto, wherein the stylus is operable to manipulate the smart device; and (b) a platform comprising a device holder affixed thereto, wherein the device holder is operable to receive the smart device, and wherein the platform and the robotic arm are robotically controlled to move by the processor.

Abstract: Described examples include a method of providing K bits of test data to a combinatorial circuit. The method further includes generating N bits of test data using the combinatorial circuit, where N is greater than K. The method further includes providing the N bits of test data to a module under test.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either directly or via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: A first hash value is calculated by using a first input value that is stored in a first set of registers. The first hash value is then stored in a second set of registers. A second input value is stored in the first set of registers after calculating the first hash value. The second hash value is calculated based on the first hash value and the second input value. During the calculating of the second hash value, the first hash value is shifted from the second set of registers to a portion of the first set of registers when the calculating of the second hash value has reached a state where the portion of the first set of registers is no longer used to store the second input value.

Abstract: Power distribution modules are configured to distribute power to a power-consuming component(s), such as a remote antenna unit(s) (RAU(s)). By “hot” connection and/or disconnection, the power distribution modules can be connected and/or disconnected from a power unit and/or a power-consuming component(s) while power is being provided to the power distribution modules. Power is not required to be disabled in the power unit before connection and/or disconnection of power distribution modules. The power distribution modules may be configured to protect against or reduce electrical arcing or electrical contact erosion that may otherwise result from “hot” connection and/or connection of the power distribution modules.

Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

Abstract: A method for producing optoelectronic conversion semiconductor chips and a composite of conversion semiconductor chips are disclosed. In an embodiment the method includes growing a semiconductor layer sequence on a growth substrate, applying an electric contact on to a rear side of the semiconductor layer sequence facing away from the growth substrate, thinning the growth substrate, after thinning, cutting the growth substrate at least to the semiconductor layer sequence thereby forming a first intermediate space, applying a conversion layer on to the thinned growth substrate and singulating at least the thinned growth substrate and the semiconductor layer sequence.

Abstract: Embodiments of the present invention provide a system, method, and program product for accelerating a simulated memory walking sequence during a simulation conducted by a computer. In one embodiment, a simulation test-case is executed and one or more memory locations in the simulated memory are identified as eligible to contain valid data. Subsequent to commencement of the simulated memory walking sequence, it is determined whether an identified memory location is within a specified number of memory locations after a memory location to be processed by simulated hardware during the simulated memory walking sequence. If an identified memory location is within the specified number, the simulated hardware is allowed to process the memory location. If an identified memory location is not within the specified number, the simulated hardware is advanced to a subsequent memory location and is allowed to process the subsequent memory location.

Abstract: According to an aspect, a display apparatus includes: a signal line or a scanning line coupled to a plurality of pixels arranged in a display region; a driver that supplies a drive signal via a resistor to the signal line or the scanning line; and an anomaly detector that monitors a response characteristic of a node between the resistor and the signal line or a node between the resistor and the scanning line.

Abstract: A method, computer program product, computing system, and an automated test platform for testing at least one device under test includes a test head configured to receive the at least one device under test. A processing system is configured to: provide a voltage signal having a plurality of voltages to the at least one device under test, and monitor a current flow into the at least one device under test during each of the plurality of voltages, thus generating a plurality of monitored current values that correspond to the plurality of voltages. The plurality of monitored current values are stored.

Abstract: A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.

Abstract: Aircraft control surface actuation systems and methods are described herein. An example control surface actuation system includes an interface cable, a test interface, and a controller. The test interface is to be disposed in an electrical equipment (EE) bay of an aircraft and operatively coupled to an actuator associated with a control surface of the aircraft. The interface cable is to be connected between the test interface and the controller, and the controller is to transmit a signal via the interface cable to the test interface to control the actuator.

Abstract: Decompressor circuitry includes a first segment and a second segment each comprising memory elements (MEs) and (i) said first segment receives the plurality of static variables originating from the tester, and (ii) and said second segment, receives the plurality of dynamic variables originating from the tester.