Abstract: An apparatus for providing a supply voltage to a device under test includes: a controlled source; a switchable resistor circuited between the output of the controlled source and a dut port, having a comparatively smaller first resistance in a first switch state and a second resistance in a second switch state; a regulator that provides a control signal to the controlled source, to regulate a voltage to be provided to the dut. The apparatus changes a switch state of the switchable resistor while a voltage is provided to the dut via the switchable resistor. The apparatus injects a compensation signal into a control loop including the regulator, the controlled source and the switchable resistor, to thereby cause a change of the voltage provided by the controlled source, to at least partially compensate a change of a voltage drop across the switchable resistor.

Abstract: A test system for testing a control unit of a system includes a management server which is configured to provide predefined test instructions, a monitoring system, and a number of output units. The monitoring system is configured to convert test instructions provided by the management server into operating instructions for setting a test configuration on a control unit of a system using predefined assignment logic. The monitoring system is also configured to divide operating instructions for setting the test configuration into partial instructions for setting a partial configuration on the control unit and to temporally and/or logically classify the partial instructions. Respective output units of the number of output units are configured to output the partial instructions transmitted by the monitoring system.

Abstract: A method of protecting a sensitive data sequence in an integrated circuit includes generating a pseudorandom sequence according to a seed sequence; combining the sensitive data sequence with the pseudorandom sequence to generate a protected data sequence; and storing the protected data sequence and the seed sequence. The sensitive data sequence is inaccessible from outside of the integrated circuit.

Abstract: Methods, systems, and devices for targeted test fail injection are described. A memory device may include self-test circuitry configured to test one or more memory cells of a memory array. The self-test circuitry may be configured to store one or more addresses to fail during a test of the memory array based on an indication from a mode register of the memory device. The self-test circuitry may be configured to fail the stored one or more addresses regardless of the outcome of the test at the one or more memory addresses. For example, when an accessed address matches a stored address during test, the self-test circuitry may generate an indication that the accessed address has failed one or more tests of the self-test procedure. Based on the self-test circuitry failing the stored addresses, a test of the memory array may be validated.

Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

Abstract: A force-sense system can provide signals to, or receive signals from, a device under test (DUT) at a first DUT node. The system can include output buffer circuitry configured to provide a DUT signal to the DUT in response to a force control signal at a buffer control node, and controller circuitry configured to provide the force control signal at the buffer control node. The system can include bypass circuitry configured to selectively bypass the controller circuitry and provide an auxiliary control signal at the buffer control node. The auxiliary control signal can be used for system calibration. In an example, an external calibration circuit can provide the auxiliary control signal in response to information received from the DUT.

Abstract: In a test system that provides a high fidelity output signal, a transition driving circuit can selectively enable multiple, parallel current paths based on a desired voltage transition. The transition driving circuit can include a first switch configured to switch a first current path between an output node and a first current source/sink, and a second switch configured to switch a second current path between the output node and the first current source/sink. The transition driving circuit can include a control circuit that is configured to receive information about a desired voltage transition and, depending on a magnitude of the desired voltage transition, to selectively turn on one or both of the first and second switches to enable one or both of the first and second current paths to provide respective portions of the output signal from the first current source/sink to the output node of the test system.

Abstract: What is disclosed are structures and methods for testing and repairing emissive display systems. Systems are tested with use of temporary electrodes which allow operation of the system during testing and are removed afterward. Systems are repaired after identification of defective devices with use of redundant switching from defective devices to functional devices provided on repair contact pads.

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

Abstract: An inspection jig includes a flexible substrate, a block, a pressing member, and a first pin fixed to the pressing member. The block has a first positioning hole opened in a substantially center portion of an opposite surface of a main surface thereof. The first pin is inserted into the first positioning hole. A large diameter portion and a small diameter portion are provided in an inner peripheral side of the first positioning hole. A diameter of the large diameter portion is smaller than a diameter of the large diameter portion. The large diameter portion is formed so as not to contact the first pin when the block is not inclined. The block is configured to be inclined with the first pin as a fulcrum.

Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Abstract: An inspection system may include a controller communicatively coupled to one or more in-line sample analysis tools including, but not limited to, an inspection tool or a metrology tool. The controller may identify defects in a population of dies based on data received from at least one of the one or more in-line sample analysis tools, assign weights to the identified defects indicative of predicted impact of the identified defects on reliability of the dies using a weighted defectivity model, generate defectivity scores for the dies in the population by aggregating the weighted defects in the respective dies in the population, and determine a set of outlier dies based on the defectivity scores for the dies in the population, wherein at least some of the set of outlier dies are isolated from the population.

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Abstract: A monitoring terminal in a manufacturing process which is able to detect and correct a faulty product-testing machine includes a communication module, a determining module, and a recording module. The communication module receives a test log transmitted from at least one product-testing machine communicating with the monitoring terminal. The test log includes identification of the product-testing machine and status thereof. The determining module can determine according to the test log whether the product-testing machine is faulty according to several conditions. The recording module records the identification of the machine in a fault information list when the machine is deemed faulty. A robot and a method for testing products and the product-testing machines themselves are also disclosed.

Abstract: Integrated circuits (12) are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (14). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a clock generator that includes a source clock generates a source clock signal at a low frequency. A clock multiplier multiplies the source clock signal by a predetermined factor to generate a high frequency clock signal. The high frequency clock signal is corrected by a time adjustment module by applying a compensation signal. The compensation signal is determined by a jitter measurement module, which uses both the high frequency clock signal and a jitter reference signal to determine the compensation signal. There are other embodiments as well.

Abstract: A system for recycling a mobile device. A system configured in accordance with one embodiment of the present technology includes an electrical connector and testing electronics. The electrical connector is configured to be electrically connected to a mobile device, and the testing electronics are configured to produce an electrical measurement by measuring an electrical attribute associated with a hardware component of the mobile device over the electrical connector. The system is further configured to valuate, identify, and/or authenticate the mobile device based at least in part on the electrical measurement.

Abstract: A method carries out a self-test of an electrical converter circuit, by use of a control device, proceeding from a known operating point at which a predetermined electrical operating variable has a predetermined starting value, a measurement cycle is begun by the converter circuit being operated. It is additionally provided that the time since the starting of the measurement cycle is detected, and the electrical operating variable and the time constitute two monitoring variables of the self-test. The measurement cycle is ended if one of the two monitoring variables satisfies an ending criterion. A test value is then formed from a measurement value of the other of the two monitoring variables at the end of the measurement cycle and a check is made to ascertain whether the test value lies outside a predetermined reference interval. If so an error signal is generated.

Abstract: The present invention is directed to a system for testing printed circuit boards. The system is configured to test the simultaneously test a multiplicity of printed circuit boards. The system examines the electrical characteristics of a printed circuit board and is operable to identify if a printed circuit board meets a desired characteristic.

Abstract: A node in a daisy chain includes a serial data input port configured to receive input from an electronic device, a serial data output port configured to send output to another electronic device, a chip select input port configured to receive input from a master control unit, a timer, and an interface circuit. The interface circuit may be configured to, in a daisy chain mode, copy data received at the serial data input port to the serial data output port, and upon receipt of a changed edge of a chip select signal on the chip select input port, initiate the timer. The interface circuit may be configured to, upon the completion of a time to be determined by the timer, enter the daisy chain mode.

Abstract: Disclosed is a vacuum valve having a valve seat, which has a valve opening, defining an opening axis, and a first sealing surface, a valve closure having a second sealing surface corresponding to the first sealing surface, a drive unit coupled to the valve closure, which can be moved from an open position, in which the valve closure and the valve seat do not contact each other, to a closed position, in which there is a sealing contact between the first sealing surface and the second sealing surface by a seal there between, and the valve opening is sealed gastight as a result. The vacuum valve has at least one temperature sensor, where the temperature sensor is designed and arranged such that, from the temperature sensor, a measurement signal representing thermal information in respect of at least one part of the vacuum valve can be detected.

Abstract: A programmable testing apparatus imposes power interruptions on a storage device at any given point of time under at least one workload according to at least one protocol for tests. The programmable testing apparatus includes a controller unit connected to a workload unit, a power control unit, a protocol control unit and a data buffer unit. The controller unit calculates and receives and replies commands in the tests. The workload unit imposes various workloads on the storage device. The power control unit imposes power interruptions on the storage device under control of the controller unit. The protocol control unit provides commands according to the protocol for tests. The data buffer unit stores critical data and information to check whether data stored in the storage device are correct.

Abstract: Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.

Abstract: A display device includes a display panel including a display surface and a rear surface opposite to each other; and a flexible printed circuit board attachable to the display panel at the rear surface of the display panel. The flexible printed circuit board includes a conductive layer, a passivation layer defining an outer surface of the flexible printed circuit board, and a base film between the conductive layer and the passivation layer, the outer surface includes a first region at which the rear surface of the display panel is attachable to the flexible printed circuit board and a second region at which the rear surface of the display panel is not attached to the flexible printed circuit board, and the first region has greater surface roughness than the second region.

Abstract: Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, compensation can be provided to suppress a leakage current from flowing through a digital output to a load connected to the reconfigurable channel terminal, particularly when the digital output is disabled.

Abstract: A test method for a memory device including the following steps is provided. A redundancy function of the memory device is disable and a first data is written to a first memory array. The redundancy function of the memory device is enabled and a second data is written to a second memory array. The first data and the second data are complementary. A redundancy information is read from a non-volatile memory block according to a margin condition and the second memory array is read based on the redundancy information to obtain a first readout data. A first test result is generated by comparing the second data and the first readout data. The second memory array includes a part of memory cells of the first memory array and at least one redundancy memory cell.

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: A horizontal probing fixture includes two bridge modules each having two spaced-apart pedestals, and a bridge plate connecting the pedestals. A first sliding unit for carrying and sliding a probe device includes two first sliding blocks respectively mounted and slidable on the bridge plates of the bridge modules, a first slide plate having two opposite ends respectively connecting the first sliding blocks, and two locking modules respectively disposed on the first sliding blocks. Each first sliding block has a bottom end complementarily engaged to and slidable on the bridge plate of one of the bridge modules. The locking modules are operable to respectively lock or unlock the first sliding blocks relative to the bridge plates.

Abstract: A test access port circuit includes a data input terminal, a reset terminal, a mode selection terminal, at least one test data register set, an auxiliary data register set, an instruction register set, and a controller. The controller is coupled to the mode selection terminal and the instruction register set, and controls the at least one test data register set, the auxiliary data register set, and the instruction register set according to at least mode selection signal received by the mode selection terminal. In a reset terminal input mode, when the controller controls a test data register set of the at least one test data register set to store a first input data bit received by the data input terminal, the auxiliary data register set stores a second input data bit received by the reset terminal.

Abstract: A method that includes changing a probe angle with respect to the conductor surface of a substrate that has a flat conductor surface mounted on the mounting surface of a stage in a high-frequency test system, thereby changing the state of contact of the tip of a signal terminal and tip of a ground terminal with the conductor surface, outputting high-frequency signals from the signal terminal to the conductor surface and receiving reflected signals using the probe to find S-parameters at different probe angles, and determining, based on a plurality of the S-parameters, a reference probe angle at which the reference line formed connecting the tip of the signal terminal and tip of the ground terminal is parallel with the conductor surface.

Abstract: A support fixture is adapted for utilization of a test probe, and includes two pedestals and at least one moveable carriage assembly. Each pedestal includes a spacing block and at least one side plate connected to the spacing block extending in a longitudinal direction. The at least one moveable carriage includes a vertical panel and an adjustable holding device. The vertical panel is engaged with the at least one side plate of one of the two pedestals, and is slidable parallel to the longitudinal direction relative to the at least one side plate of each of the two pedestals. The adjustable holding device is operable for fixing the vertical panel to the at least one side plate of the one of the two pedestals and is adapted to hold the test probe.

Abstract: A method for a continuous mutual extended processor self-test is provided. The method is implemented by a system including a plurality of cores. The system sets an operating condition for the continuous mutual extended processor self-test. An assist processor of the plurality of cores executes a test program that implements the continuous mutual extended processor self-test on a core under test of the plurality of cores. The system determines a pattern and a response during the test program execution and repeats the test program until the test program has finished or failed.

Abstract: A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.

Abstract: Systems and methods for a wiring racetrack for aircraft are described herein. The wiring racetrack can include a wiring pallet with a plurality of channels. A plurality of different wiring groups can each be disposed within one of the channels. Each of the wiring groups can include wiring of exclusively one category or one category and neutral wires. Connectors can be electrically coupled to the wires of the group. Fabrication of the wiring racetrack can be automatically performed by one or more robots that include an end effector and a robotic transfer unit.

Abstract: System and method for testing a wireless data packet signal transceiver device under test (DUT) in which external control circuitry manages initiation of execution by a tester of test program instructions defining multiple self-terminating test control sequences in one or more desired sequences. The test control sequences may be pre-stored in a tester for subsequent execution under control of control signals sourced externally by the external control circuitry via separate control signals.

Abstract: Techniques for testing circuits, such as converter circuits, such as digital-to-analog converter circuits (DACs), are described. A digital signal processor (DSP) can generate a waveform, such as sine wave, and apply the sine wave to the circuit under test, e.g., a DAC. The DAC can generate an output and the DSP can regenerate the waveform and determine an accuracy of the DAC such as to determine whether the DAC meets one or more specified criteria. In some example implementations, the tests can be performed using variable voltage amplitude segments.

Abstract: The inspection system 100 is constructed by assembling inspection modules 10 configured to inspect inspection target objects and a transfer module 20 configured to transfer the inspection target object to the corresponding inspection module. The inspection system 100 is configured to transfer the inspection target objects into the inspection modules by the transfer module and inspect the inspection target objects in sequence. The adjustment method of the inspection system includes preparing an auxiliary element having a preset function of the inspection module 10 or a preset function of the transfer module 20; and adjusting, with respect to an adjustment which needs to be performed after the inspection system is constructed, the transfer module 20, or each of the inspection modules 10 or the inspection modules 10 as a single system by connecting the auxiliary element 60 (70, 80, 90) to the transfer module 20 or the inspection module 10.

Abstract: Systems, methods, and apparatus for maintenance over an auxiliary power line are disclosed. In one or more embodiments, a disclosed method for retrieving maintenance data from a unit on a vehicle comprises powering the unit by an auxiliary power line connected to the unit or powering the unit by a primary power line connected to the unit. The method further comprises retrieving, by a digital source controller, the maintenance data off of the unit via the auxiliary power line by using broadband over power line (BPL). Further, the method comprises providing power to the auxiliary power line by the digital source controller. In one or more embodiments, the maintenance data comprises built in test (BIT) data, built in test equipment (BITE) data, health management data, configuration data, at least one hardware (HW) part number, and/or at least one software (SW) version number.

Abstract: An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

Abstract: A semiconductor device capable of executing fault injection test on a plurality of failure detection mechanism in a short time is provided. The semiconductor device 1 has a plurality of hierarchical modules and an error control module 100 for controlling errors in the plurality of hierarchical modules. Each hierarchical module has a safety mechanism to detect failures in the functions of the components that make up the hierarchical modules. The error control module 100 includes a status register 120 configured to record data indicative of the status of failure of each hierarchical module, and a fault injection function 110 that outputs an error signal to the status register 120 to perform fault injection test. The error signal is inputted into the safety mechanism via the status register 120.

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

Abstract: Disclosed approaches for dynamically creating one or more scan chains in a programmable integrated circuit (IC) include placing elements of a circuit design on first registers of the programmable IC. A processor can determine second registers of the programmable IC that are unused by the circuit design after placing the elements of the circuit design. Data-out pins of the first registers are coupled to data-in pins of the second registers, respectively, and the second registers are coupled into a scan chain.

Abstract: A method of detecting a fault in a circuit design undergoing emulation, includes in part, computing N signatures of a corresponding reference circuit design during each of the N cycles, computing N signatures of the circuit design undergoing emulation during each of the N cycles, comparing, for each of the N cycles, the signature of the reference circuit design to the signature of the circuit design undergoing emulation, and detecting whether a mismatch exists between the reference circuit design signature and the signature of the circuit design undergoing emulation during each of the N cycles. The method further includes comparing the signatures of the submodules of the reference circuit design to the signatures of the corresponding submodules of the circuit design undergoing emulation to enable root causing submodule functional failures. Optionally, each signature may computed by performing a logic function on a multitude of output signals of the circuit design.

Abstract: A semiconductor integrated circuit test system can include a first semiconductor integrated circuit tester configured to conduct a first test of a first characteristic of one of a plurality of semiconductor integrated circuits, wherein the first test is completed by the first semiconductor integrated circuit tester within a first test time. A second semiconductor integrated circuit tester, can be coupled to the first semiconductor integrated circuit tester, where the second semiconductor integrated circuit tester can be configured to conduct a second test of a second characteristic of each of the plurality of the semiconductor integrated circuits simultaneously, wherein the second test is completed within a second test time that is at least about two orders of magnitude more than the first test time.

Abstract: A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

Abstract: The independent claims of this patent signify a concise description of embodiments. A hardware emulation system is configured to define a variable delay associated with each of a multitude of design clocks used in the circuit design, compute a compression value in accordance with the multitude of variable delays, detect a change in one or more of the variable delays, and recompute the time compression value in response to the detected change. The hardware emulation system is further configured to recompute the time compression using programmable circuitry disposed in the hardware emulation system and without stopping the hardware emulation system. Such circuitry may be disposed in a single programmable device disposed in the hardware emulation system or a multitude of programmable devices disposed in the hardware emulation system. This Abstract is not intended to limit the scope of the claims.

Abstract: A method of detecting a fault in a circuit design undergoing hardware emulation, includes, in part, comparing, in each cycle K of a clock and at the hardware emulation system, the cycle K register values of a reference circuit with the cycle K register values of the circuit design undergoing emulation. The method further includes detecting, in each cycle K of the clock and at the hardware emulation system, whether a mismatch exists between the cycle K reference circuit design register values and the cycle K register values of the circuit design undergoing emulation. Alternatively the comparison may be made between the respective signatures computed from the register values. The register values of the reference circuit design for all K cycles may be transferred to the emulation system prior to emulation. Alternatively, for each cycle K, the register values may be transferred to the hardware emulation system during that cycle.

Abstract: A technology is described for a device diagnosis station. The device diagnosis station may be configured to identify an electronic device physically connected to the device diagnosis station, evaluate an operational state of the electronic device by executing testing instructions configured to test the functionality of the electronic device and collect operational state information for the electronic device. The device diagnosis station may be configured to determine the operational state of the electronic device and execute recovery instructions to restore the electronic device to an improved state when a recoverable error is detected. The device diagnosis station may be configured to initiate a device return procedure for the electronic device when a non-recoverable error state is detected.