Abstract: A semiconductor device includes: a semiconductor body; an electrical device formed in an active region of the semiconductor body, the active region including an interface between the semiconductor body and an insulating material; and a sensor having a bandwidth tuned to at least part of an energy spectrum of light emitted by carrier recombination at the interface when the electrical device is driven between accumulation and inversion, wherein an intensity of the emitted light is proportional to a density of charge trapping states at the interface, wherein the sensor is configured to output a signal that is proportional to the intensity of the sensed light. Corresponding methods of monitoring and characterizing the semiconductor device and a test apparatus are also described.

Abstract: A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.

Abstract: A measurement system for characterizing a device under test is described. The measurement system includes a signal source, an analysis module, and a directional element that is connected to each of the device under test, the signal source, and the analysis module. The signal source is configured to generate a digital instruction signal or an analog stimulus signal for the device under test. In the case of generating the analog stimulus signal, the directional element is configured to forward the analog stimulus signal from the signal source to the device under test, wherein the device under test includes circuitry configured to generate a digital output signal based on the analog stimulus signal received.

Abstract: A test circuit and method for a display panel, and a display panel. The test circuit includes a panel test sub-circuit configured to control panel test switch units to turn on or turn off, to transmit multiple panel test signals; an array test sub-circuit configured to control array test switch units to turn on or turn off, to output short circuit determination signals at test terminals according to the multiple panel test signals, which are used to determine whether there is a short-circuited data line in the display panel; at least one set of the array test switch units are turned on in a test sub-period, and under a condition that the at least one set of the array test switch units are turned on, the panel test signals corresponding to different types of sub-pixels in the display panel change alternately to an effective level.

Abstract: A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.

Abstract: An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.

Abstract: An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

Abstract: The present disclosure provides an electrical test structure, a semiconductor structure and an electrical test method. In the electrical test structure, in a first direction, the electrical test structure includes a first layer, an interconnect hole and a second layer arranged in a stack, and the interconnect hole is in contact with the first layer; the second layer includes a body part and a test part, and the test part is connected to the body part; the interconnect hole is configured as, when an offset distance of the interconnect hole relative to a preset position in a second direction is less than a first preset distance, or an offset distance of the interconnect hole relative to the preset position in a third direction is less than a second preset distance, the interconnect hole is spaced apart from the test part.

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals.

Abstract: A test and measurement device includes an input configured to receive an analog signal from a Device Under Test (DUT), an Analog to Digital Converter (ADC) coupled to the input and structured to convert the analog signal to a digital signal, a receiver implemented in a first Field Programmable Gate Array (FPGA) and structured to accept the digital signal and perform signal analysis on the digital signal, a transmitter implemented in a second FPGA and structured to generate a digital output signal, and a Digital to Analog Converter (DAC) coupled to the transmitter and structured to convert the digital output signal from the transmitter to an analog signal, and structured to send the analog signal to the DUT. The receiver and the transmitter are coupled together by a high speed data link over which data about the current testing environment may be shared.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: Systems, devices, and methods are described herein for measuring an impedance of a DUT using an integrated impedance measurement device. A system includes a plurality of measurement circuits, a FFT processor, and a controller. The measurement circuits are coupled to the DUTs. Each measurement circuit is configured to generate a clock signal for a respective DUT, detect a voltage of the respective DUT, and generate first voltage related data using the clock signal and the voltage. The FFT processor is coupled to the measurement circuits. The FFT processor is configured to convert the first voltage related data into second voltage related data using a fast Fourier transform for each measurement circuit. The controller is coupled to the measurement circuits and the FFT processor. The controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each DUT.

Abstract: A system and method for performing in-situ measurements of semiconductor devices during chemical vapor deposition (CVD) includes disposing a chip carrier within a sealed chamber of a reactor for carrying out in-situ monitoring of partially fabricated semiconductor devices. The chip carrier includes a plurality of metallized bonding pads disposed along both peripheral edges on a same surface of the base for making electrical connections to metallized pads or contacts on the semiconductor device through bonding wires. Each of the plurality of metallized bonding pads disposed along both peripheral edges is electrically connected to each other as a pair through electrically connecting to a corresponding pair of ports which are disposed along both peripheral edges of the chip carrier. In-situ monitoring of the partially fabricated semiconductor device is performed through connecting the plurality of ports on the chip carrier to an external source-measure unit through a connector and wire harness.

Abstract: A quantum controller comprises a first quantum control pulse generation circuit and a second quantum control pulse generation circuit. The first quantum control pulse generation circuit and a second quantum control pulse generation circuit are operable to operate asynchronously during some time intervals of a quantum algorithm and synchronously during other time intervals of the quantum algorithm.

Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

Abstract: An electronic system can be used to monitor temperature. The electronic system can include a characterized dielectric located adjacent to a plurality of heat-producing electronic devices. The electronic system can also include a leakage measurement circuit that is electrically connected to the characterized dielectric. The leakage measurement circuit can be configured to measure current leakage through the characterized dielectric. The leakage measurement circuit can also be configured to convert a leakage current measurement into a corresponding output voltage. A response device, electrically connected to the leakage measurement circuit can be configured to, in response to the output voltage exceeding a voltage threshold corresponding to a known temperature, initiate a response action.

Abstract: The present invention relates to an electronic test device for at least one avionic function to be tested, intended to be embedded in an aircraft, the aircraft comprising at least one avionic equipment item, the test device being intended to be connected to the at least one avionic equipment item and comprising: an acquisition module, configured to acquire flight data from the at least one avionic equipment item, and a computing module, configured to compute simulated output data, from acquired flight data and via an implementation of the avionic function to be tested, the avionic function to be tested being able, from the flight data, to deliver the output data.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: Example implementations include a method of pre-bootup fault monitor of a LASER diode driver output, by applying a first power to a pre-bootup fault monitor device, setting a fault condition at the pre-bootup fault monitor device to a no-fault state, initiating the pre-bootup fault monitor device, determining whether a first impedance of driver output satisfies an impedance threshold, and in response to a determination that the first impedance satisfies the impedance threshold, applying a second power to the output device.

Abstract: A semiconductor test device for measuring a contact resistance includes: first fin structures, upper portions of the first fin structures protruding from an isolation insulating layer; epitaxial layers formed on the upper portions of the first fin structures, respectively; first conductive layers formed on the epitaxial layers, respectively; a first contact layer disposed on the first conductive layers at a first point; a second contact layer disposed on the first conductive layers at a second point apart from the first point; a first pad coupled to the first contact layer via a first wiring; and a second pad coupled to the second contact layer via a second wiring. The semiconductor test device is configured to measure the contact resistance between the first contact layer and the first fin structures by applying a current between the first pad and the second pad.

Abstract: Methods of sensory input integrity attestation are provided. Artifacts included within devices under test inject a known noise signal into the output signal of one or more output devices that are detectable by one or more input devices (i.e., sensors) of an embedded device, and monitor the received input data. By comparing the received signal against the expected noise signal, attestation of the validity of sensory input data is possible. Such sensory input data attestation is capable either locally or using a remote attestation device with knowledge of the expected data stream.

Abstract: Methods of performing diagnostic tests on electroencephalography (EEG) recording devices comprising at least one stimulator coupled with a plurality of EEG electrode recording channels and corresponding recording channel connectors are performed by a test fixture comprising a plurality of resistors coupled with one or more of the EEG electrode recording channels and corresponding recording channel connectors. The methods include performing an impedance test for determining if each EEG recording channel of the EEG recording device has a predefined impedance, performing a channel uniqueness test for each EEG recording channel, performing a test for verifying the state of a switch of the stimulator of the EEG recording device, and performing a test for verifying connector IDs of the recording channel connectors connecting the EEG electrodes to respective EEG recording channels.

Abstract: A device analysis apparatus is a device analysis apparatus for determining a quality of a power semiconductor device, including an application unit that applies a voltage signal to the power semiconductor device, a light detection unit that detects light from the power semiconductor device at a plurality of detection positions and outputs detection signals based on detection results, and a determination unit that determines the quality of the power semiconductor device based on temporal changes of the detection signals.

Abstract: Provided is a measuring method for testing a device under test (DUT) having a plurality of terminals and, particularly, to a means for measuring the functions and performance of various electronic devices in which an electronic circuit such as that in an electronic device, a semiconductor element, a circuit module, and a circuit board is mounted, and to: a method by which a processor supports measurement with software such that unit costs can be reduced to be lower than those of conventional means operating with various, high-cost hardware; and a device using the same.

Abstract: A test system can include a probe suitable to be coupled between a test measurement device and a device under test (DUT). The probe can include a signal input to receive an active signal from the DUT and a signal output to provide the active signal to the test measurement device. The probe can also include an input ground to connect to the DUT ground and an output ground to connect to the test measurement device ground. A probe ground connection checking device can automatically determine whether the probe ground connections to the DUT ground and test measurement device ground are solid.

Abstract: Disclosed is a flexible coil circuit for a non-destructive inspection probe. The coil circuit is made of multiple layers of thin flexible ceramic material, each ceramic layer having a metallization layer deposited thereon. The circuit is capable of continuous operation at temperatures up to 350° C. The metallized layers are able to slide freely over one another as the probe is flexed, enabling the probe to conform to the circumference of pipes as small as 2 inches in diameter.

Abstract: Example automatic test equipment (ATE) includes a first test instrument to receive a waveform from a device under test, where the waveform is based on test signals sent from the ATE to the DUT; circuitry to generate digital pulses based on the waveform; and a second test instrument to receive the digital pulses over at least two digital pins and to process the digital pulses to test the DUT.

Abstract: A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

Abstract: Techniques and devices are described for embedding data in an address stream on an interconnect, such as a memory bus. Addresses in an address stream indicate at least part of a location in memory (e.g., a memory page and offset), whereas data embedded in the address stream can indicate when metadata or other information is available to lend context to the addresses in the address stream. The indication of data in the address stream can be communicated using, for example, a mailbox, a preamble message in a messaging protocol, a checksum, repetitive transmission, or combinations thereof. The indication of data can be recorded from the address stream and may later be used to interpret memory traces recorded during a test or can be used to communicate with a memory device or other recipient of the data during testing or regular operations.

Abstract: A flexible flat cable testing system includes a first connector including a row of first contacts electrically contacting first ends of a row of wires of a flexible flat cable, a second connector including a row of second contacts electrically contacting second ends of the row of wires, a short circuit test unit including output ports electrically connected to the row of first contacts and input ports electrically connected to the row of second contacts, a potential reader reading a potential level of each of the input ports, and a judgment unit determining whether or not a quality of the flexible flat cable is qualified according to the potential level of each of the input ports. The judgment unit determines that the quality of the flexible flat cable is qualified if the potential level of each of the input ports is equal to a high level output by each of the output ports.

Abstract: An apparatus for providing a supply voltage to a device under test includes: a controlled source; a switchable resistor circuited between the output of the controlled source and a dut port, having a comparatively smaller first resistance in a first switch state and a second resistance in a second switch state; a regulator that provides a control signal to the controlled source, to regulate a voltage to be provided to the dut. The apparatus changes a switch state of the switchable resistor while a voltage is provided to the dut via the switchable resistor. The apparatus injects a compensation signal into a control loop including the regulator, the controlled source and the switchable resistor, to thereby cause a change of the voltage provided by the controlled source, to at least partially compensate a change of a voltage drop across the switchable resistor.

Abstract: A test system for testing a control unit of a system includes a management server which is configured to provide predefined test instructions, a monitoring system, and a number of output units. The monitoring system is configured to convert test instructions provided by the management server into operating instructions for setting a test configuration on a control unit of a system using predefined assignment logic. The monitoring system is also configured to divide operating instructions for setting the test configuration into partial instructions for setting a partial configuration on the control unit and to temporally and/or logically classify the partial instructions. Respective output units of the number of output units are configured to output the partial instructions transmitted by the monitoring system.

Abstract: A method of protecting a sensitive data sequence in an integrated circuit includes generating a pseudorandom sequence according to a seed sequence; combining the sensitive data sequence with the pseudorandom sequence to generate a protected data sequence; and storing the protected data sequence and the seed sequence. The sensitive data sequence is inaccessible from outside of the integrated circuit.

Abstract: Systems and methods for configuring a SPA are disclosed. The SPA comprises a plurality of input ports, a plurality of data memory units, signal processing circuitry, and an enable block including at least two counters. Each counter determines an amount of unprocessed data that is stored in a respective one of the plurality of data memory units, and the enable block is configured to disable the signal processing circuitry until a predetermined amount of data is received over the input ports.

Abstract: Methods, systems, and devices for targeted test fail injection are described. A memory device may include self-test circuitry configured to test one or more memory cells of a memory array. The self-test circuitry may be configured to store one or more addresses to fail during a test of the memory array based on an indication from a mode register of the memory device. The self-test circuitry may be configured to fail the stored one or more addresses regardless of the outcome of the test at the one or more memory addresses. For example, when an accessed address matches a stored address during test, the self-test circuitry may generate an indication that the accessed address has failed one or more tests of the self-test procedure. Based on the self-test circuitry failing the stored addresses, a test of the memory array may be validated.

Abstract: A force-sense system can provide signals to, or receive signals from, a device under test (DUT) at a first DUT node. The system can include output buffer circuitry configured to provide a DUT signal to the DUT in response to a force control signal at a buffer control node, and controller circuitry configured to provide the force control signal at the buffer control node. The system can include bypass circuitry configured to selectively bypass the controller circuitry and provide an auxiliary control signal at the buffer control node. The auxiliary control signal can be used for system calibration. In an example, an external calibration circuit can provide the auxiliary control signal in response to information received from the DUT.

Abstract: In a test system that provides a high fidelity output signal, a transition driving circuit can selectively enable multiple, parallel current paths based on a desired voltage transition. The transition driving circuit can include a first switch configured to switch a first current path between an output node and a first current source/sink, and a second switch configured to switch a second current path between the output node and the first current source/sink. The transition driving circuit can include a control circuit that is configured to receive information about a desired voltage transition and, depending on a magnitude of the desired voltage transition, to selectively turn on one or both of the first and second switches to enable one or both of the first and second current paths to provide respective portions of the output signal from the first current source/sink to the output node of the test system.

Abstract: An inspection jig includes a flexible substrate, a block, a pressing member, and a first pin fixed to the pressing member. The block has a first positioning hole opened in a substantially center portion of an opposite surface of a main surface thereof. The first pin is inserted into the first positioning hole. A large diameter portion and a small diameter portion are provided in an inner peripheral side of the first positioning hole. A diameter of the large diameter portion is smaller than a diameter of the large diameter portion. The large diameter portion is formed so as not to contact the first pin when the block is not inclined. The block is configured to be inclined with the first pin as a fulcrum.

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

Abstract: What is disclosed are structures and methods for testing and repairing emissive display systems. Systems are tested with use of temporary electrodes which allow operation of the system during testing and are removed afterward. Systems are repaired after identification of defective devices with use of redundant switching from defective devices to functional devices provided on repair contact pads.

Abstract: An inspection system may include a controller communicatively coupled to one or more in-line sample analysis tools including, but not limited to, an inspection tool or a metrology tool. The controller may identify defects in a population of dies based on data received from at least one of the one or more in-line sample analysis tools, assign weights to the identified defects indicative of predicted impact of the identified defects on reliability of the dies using a weighted defectivity model, generate defectivity scores for the dies in the population by aggregating the weighted defects in the respective dies in the population, and determine a set of outlier dies based on the defectivity scores for the dies in the population, wherein at least some of the set of outlier dies are isolated from the population.

Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Abstract: A monitoring terminal in a manufacturing process which is able to detect and correct a faulty product-testing machine includes a communication module, a determining module, and a recording module. The communication module receives a test log transmitted from at least one product-testing machine communicating with the monitoring terminal. The test log includes identification of the product-testing machine and status thereof. The determining module can determine according to the test log whether the product-testing machine is faulty according to several conditions. The recording module records the identification of the machine in a fault information list when the machine is deemed faulty. A robot and a method for testing products and the product-testing machines themselves are also disclosed.

Abstract: Integrated circuits (12) are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (14). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: A system for recycling a mobile device. A system configured in accordance with one embodiment of the present technology includes an electrical connector and testing electronics. The electrical connector is configured to be electrically connected to a mobile device, and the testing electronics are configured to produce an electrical measurement by measuring an electrical attribute associated with a hardware component of the mobile device over the electrical connector. The system is further configured to valuate, identify, and/or authenticate the mobile device based at least in part on the electrical measurement.