Abstract: A probe head includes a probe base, a film, and a probe assembly. The probe base includes first, second, and third guiding boards. The second guiding board is fixed between the first and third guiding boards. The film is fixed to the probe base and has a hole. The probe assembly passes through the first, second, and third guiding boards and the hole, and includes a probe and an outer spring sleeve. The probe has a tip passing out through the third guiding board. The outer spring sleeve is sleeved at the exterior of the probe and has a spring area and a plurality of non-spring areas. The spring area is disposed between adjacent two of the non-spring areas. One of the non-spring areas has a bonding section mounted to the probe and retained between the third guiding board and the film.

Abstract: A test system can include a probe suitable to be coupled between a test measurement device and a device under test (DUT). The probe can include a signal input to receive an active signal from the DUT and a signal output to provide the active signal to the test measurement device. The probe can also include an input ground to connect to the DUT ground and an output ground to connect to the test measurement device ground. A probe ground connection checking device can automatically determine whether the probe ground connections to the DUT ground and test measurement device ground are solid.

Abstract: A signal generation device outputs a signal based on a predetermined pattern with a logic transition to a predetermined external device. The signal generation device comprises an output driver which outputs respective signals based on at least two test patterns different in the frequency of the logic transition respectively to the predetermined external device, a regulator which supplies power to the output driver, a current compensation circuit which generates a compensation current, and a control circuit which adjusts a value of the compensation current. The control circuit adjusts, for each test pattern, the value of the compensation current such that a difference value calculated based on output voltages of the regulator becomes a determination criteria value or less.

Abstract: A test mode control circuit relating to a technology for controlling a vendor specific test mode is disclosed. The test mode control circuit includes a signal generation circuit configured to generate a plurality of set signals and a plurality of reset signals in response to a plurality of code signals and a predetermined mode register signal; and a plurality of serially-connected latch circuits configured to selectively operate in response to the plurality of set signals and the plurality of reset signals so as to control an entry signal of an output terminal.

Abstract: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: For creating a custom series of commands, a method is disclosed that includes maintaining a record of executed commands, determining a time to select a subset of executed commands, selecting a subset of the executed commands for execution, and creating a shortcut to execute the selected commands.

Abstract: An input-output circuit includes a reception circuit and a register circuit. The reception circuit operates in accordance with a normal write protocol commonly in a normal write mode and a test write mode. The reception circuit receives a plurality of input signals to generate a plurality of latch signals. The register circuit generates a plurality of test result signals based on the latch signals in the test write mode. The input-output circuit may perform the multiple-input shift register (MISR) function in accordance with the normal write path and the normal write protocol. The MISR function may be performed efficiently without consideration of additional timing adjustment for the test write operation because the MISR function is performed under the same timing condition as the normal write operation.

Abstract: A reception circuit receives, via a cable, a transmission signal STX generated by a DUT. A comparator circuit compares a reception signal SRX after signal transmission with at least one threshold signal VTH, and generates a judgment value DOUT that represents a comparison result for every sampling timing. A threshold generation circuit generates at least one threshold signal VTH. A threshold control circuit adjusts each level of at least one threshold signal VTH at a given sampling timing based on the history of the judgment value DOUT acquired at a past sampling timing.

Abstract: There are provided a display device capable of detecting a defect of a scan driver. The display device includes pixels positioned in regions demarcated by scan lines and data lines, a scan driver including a plurality of stages connected to the scan lines, an inspection unit connected to the stages to detect whether the stages are defective, and including first transistors turned on when a control signal is supplied, and a timing controller supplying the control signal, wherein the timing controller detects a position of a defective stage by reducing a period during which the control signal is supplied.

Abstract: Design techniques for multi-modulus prescaler circuits that minimize the input-to-output delay dependence on the modulus control state or history. The feed-forward signal path inside a multi-modulus prescaler is identified, as well as all feedback paths connected to the feed-forward signal path. In various embodiments, one or more of several techniques may be applied to reduce capacitive load variations and signal coupling due to the modulus control state or history. For at least one component coupled to the feed-forward signal path and having a feedback path, a buffered feedback path may be created separate but parallel to a buffered feed-forward signal path. Double buffers may be added to some feedback paths directly coupled to the feed-forward path so that the forward signal path is not affected by load variations in such feedback paths.

Abstract: A circuit for a motor comprises at least two phase windings forming one half of motor phase windings of the circuit and at least two other phase windings forming another half of the motor phase windings of the circuit. A direct current (DC) power supply receives alternating current (AC) power transferred from one or more of the motor phase windings and converts the AC power to DC power. A first stage power switch circuit comprising at least one power switch is connected between the at least two phase windings on the one half of the motor phase windings of the circuit and between the at least two other phase windings on the other half of the motor phase windings of the circuit. A second stage power switch circuit comprising at least one other power switch is connected between the one half of the motor phase windings of the circuit and the other half of the motor phase windings of the circuit, the at least one other power switch to receive AC power from one or more of the motor phase windings.

Abstract: In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers.

Abstract: Probing an integrated circuit (IC), by: electrically applying stimulation signal to said IC; scanning a selected area of said IC with a monochromatic beam; collecting beam reflection from the selected area of said IC, wherein the beam reflection correspond to modulation of the monochromatic beam by active devices of said IC; converting said beam reflection to an electrical probing signal; selecting a frequency or a band of frequencies of said probing signal; utilizing the probing signal to generate a spatial modulation map for various locations over the selected area of said IC; and displaying the spatial map on a monitor, wherein grey scale values correspond to modulation signal values.

Abstract: A method for auto-calibrating a semiconductor component tester is provided. The semiconductor component tester includes a wafer tester or a package IC tester. Firstly, an initial tester setting value and an initial board setting value are acquired through a calibration board. Then, the test record of the semiconductor component corresponding to each test time and the tester parameter and the board parameter for testing the semiconductor component are recoded. If the semiconductor component fails the test, the semiconductor component is tested again according to the previously-passed tester parameter and the previously-passed board parameter, or the semiconductor component is tested again after the tester parameter and the board parameter are adjusted. The method is capable of correcting the improper test result from the improper tester parameter.

Abstract: An improved measurement system may include a source measure unit (SMU) capable of performing accurate low-level current measurements. Based on an SMU design that provides a controlled DC voltage source with precision current limiting and a controlled 0V (zero Volt) DC at the measurement terminal, an AC design may be implemented to establish the same (or very similar) conditions over a specified frequency range. Instead of controlling each digital-to-analog converter (DAC) at respective source terminals of the SMU as a respective DC output, each DAC may be controlled as a respective function generator with programmable frequency and continuously variable phase and amplitude. Off-the-shelf pipelined analog-to-digital converters (ADCs) may be used to monitor voltage, current and the voltage at the measurement terminal, and a Fourier transform may be used to obtain both the amplitude and relative phase measurements to be provided to respective control loops.

Abstract: An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.

Abstract: Methods and apparatus are described for adding one or more features (e.g., HBM) to a qualified SSI technology programmable IC region by providing an interface (e.g., an HBM buffer region with a switch network) between the added feature device and the programmable IC region. One example IC package generally includes a package substrate; at least one interposer disposed above the package substrate; a programmable IC region disposed above the interposer; at least one fixed feature die disposed above the interposer; and an interface region disposed above the interposer and configured to couple the programmable IC region to the fixed feature die via a first set of interconnection lines routed through the interposer between a first plurality of ports of the interface region and the fixed feature die and a second set of interconnection lines routed between a second plurality of ports of the interface region and the programmable IC region.

Abstract: A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.

Abstract: An offset detection circuit includes: a comparison unit that generates a first comparison result between an amplifier output and a positive detection threshold value, and a second comparison result between the amplifier output and a negative detection threshold value; a first determination unit that generates a first offset determination result of two values indicating presence or absence of an offset according to a period during which the amplifier output exceeds the positive detection threshold value, based on the first comparison result; a second determination unit that generates a second offset determination result of two values indicating the presence or absence of an offset according to a period during which the amplifier output exceeds the negative detection threshold value, based on the second comparison result; and an output unit that generates a determination output of the offset based on the first and second offset determination results.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: A line detecting apparatus and a line detecting method for an array substrate relates to the field of line detecting technology. The detecting method comprises: arranging an input terminal sensor (30) at a signal input terminal of a wire to be detected, arranging one output terminal sensor (41, 42, 43) at a signal output terminal of the wire to be detected, and arranging other output terminal sensor (41, 42, 43) at a signal output terminal of another wire adjacent to the wire to be detected; measuring an output voltage of the wire to be detected by a voltage detector; and determining the line conduction condition of the wire to be detected according to the output voltage as measured. When the sensors perform line scan, the coordinate of the specific location where the short-circuit or open-circuit occurs can be found directly without performing scan by PDS or AOI, thus simplifying the technical processes, shortening the time for detecting, and saving the production cost.

Abstract: A switching matrix includes a plurality of input ports, a plurality of output ports, a plurality of switching devices configured to open and close, an electrical connection between the input ports and the output ports, and an electrical sensor configured to generate a signal by measuring a predetermined electrical property of the electrical connection, the open and close of switching devices is pre-determined by status read from the electrical sensor.

Abstract: A test system for performing a plurality of tests on a plurality of devices includes a tester having a plurality of tester pins and at least one socket, wherein the plurality of devices are received in the at least one socket. The test system further includes a plurality of multiplexers, wherein each of the multiplexers has an input coupled to one of the plurality of tester pins and each of the multiplexers has outputs coupled to individual device pins of the devices. The tester is configurable to perform a first test on a first plurality of devices and a second test on a second plurality of devices without disconnecting the devices from the at least one socket.

Abstract: The present invention discloses a method of testing an analog-to-digital converter (ADC). The method includes receiving a series of analog signals from a tester site, converting the series of analog signals to a series of digital code words using an ADC, evaluating the ADC based on the series of digital code words using an ADC test setup and generating an output signal identifying whether the ADC has passed the testing.

Abstract: To provide a measuring device wherein a measurement range corresponding to a wave shape to be measured can be set with a simple configuration. A measuring device (100) has: a measuring unit that measures changes of indexes with time, said indexes relating to an object event; a conversion unit that converts a measurement value measured by means of the measuring unit into a predetermined format within a previously set measurement range; and a control unit that controls the measurement range. The control unit changes the measurement range in the cases where a conversion value obtained by converting the measurement value by means of the conversion unit satisfies predetermined conditions in a predetermined period.

Abstract: A calibration board and a timing calibration method thereof are provided. The calibration board for calibrating signal delays of test channels in an automatic test equipment is pluggably disposed in the automatic test equipment and includes calibration groups, a first common node, and a switching module. Each calibration group includes a second common node and conductive pads electrically connecting to the second common node. Each conductive pad selectively and electrically connects to one test channel. The switching module electrically connects to the first common node and each second common node. When a first delay calibration procedure is performed, the connection between the first common node and each second common node is disabled. When a second delay calibration procedure is performed, the connection between the first common node and each second common node is built.

Abstract: The invention provides a method of monitoring a quality of a liquid crystal display including: selecting multiple quality parameters related to the quality of the liquid crystal display and obtaining an expression of the quality with respect to the quality parameters; acquiring a value of each of the quality parameters and substituting the value of each of the quality parameters into the expression of the quality with respect to the quality parameters to obtain a first value; judging the first value whether falls into a predetermined range; and when the first value falls into the predetermined range, determining the quality of the liquid crystal display as normal.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: A shift register circuit generates a clock enable signal in response to a start signal and in response to a clock signal. The shift register circuit generates multiple pulses in the clock enable signal in response to a single transition in the start signal and in response to control signals having values that indicate to generate more than one pulse in the clock enable signal. A multiplexer circuit provides an output signal for testing an electronic circuit based on an input signal or based on the clock signal in response to the clock enable signal.

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

Abstract: In one example case, a cross-platform system includes a first automated test platform having a first test instrument and a first glue layer interface that exposes test functions to direct testing by the first test instrument. The system further includes a second automated test platform having a second test instrument and a second glue layer interface that exposes the same test functions to direct testing by the second test instrument. In the system, the glue layers abstract the respective and different control commands used by the different, first and second test instruments. Using the glue layers, the same higher-level test code can be executed by the control computers of both the first and second automated test platforms.

Abstract: Architectures and techniques to visually indicate an operational state of an electronic device. In some instances, the electronic device comprises a voice-controlled device configured to interact with a user through voice input and visual output. The voice-controlled device may be positioned in a home environment, such as on a table in a room of the environment. The user may interact with the voice-controlled device through speech and the voice-controlled device may perform operations requested by the speech. As the voice-controlled device enters different operational states while interacting with the user, one or more lights of the voice-controlled device may be illuminated to indicate the different operational states.

Abstract: Optimized metal wires for resistance or electromigration, methods of manufacturing thereof and design methodologies are disclosed. The method includes depositing metal material within openings and on a surface of dielectric material resulting in metal filled openings and a topography of recessed areas aligned with the metal filled openings. The method further includes depositing an alloying material over the metal material, including within the recessed areas. The method further includes planarizing the metal material, leaving the alloying material within the recessed areas. The method further includes diffusing the alloying material into the metal material forming alloyed regions self-aligned with the metal filled openings.

Abstract: A system for connecting a test pin of automatic test equipment (ATE) to devices for testing includes a first handler for manipulating a first portion of the devices and a second handler for manipulating a second portion of the devices. The system includes a first socket for testing devices of the first portion, which is connected to a first wire, and a second socket for testing devices of the second portion, which is connected to a the second wire. A controller multiplexes the two handlers, or dual manipulators of a single handler, to operate the handlers asynchronously in coordination with testing, such that while the ATE is testing devices for one handler, the other handler presents next devices to the ATE for immediate switch of testing between devices for each handler. The system is suitable for conventional handlers and ATE.

Abstract: The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

Abstract: A method for constructing a scan chain for a memory sequential test, including determining an input boundary register of the memory; determining a number N of test vectors required according to the type of the memory input pins to which the input boundary register is connected; arranging the scan chain based on the number N, such that in the scan chain, upstream of the input boundary register and immediately adjacent to the input boundary register, there are at least (N?1) continuous non-boundary registers; and setting control signals of the input boundary register and the (N?1) non-boundary registers to make them receive scan test input as test vectors under memory sequential test mode.

Abstract: A noise suppression circuit comprises a switchable transistor and an amplifier having a first amplifier input terminal electrically coupled to an output terminal of the switchable transistor for sensing a voltage thereat, and an amplifier output terminal electrically coupled to a control terminal of the switchable transistor for outputting a control voltage thereto.

Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Abstract: A method is disclosed that comprises severing an I/O channel between an EMAC and an aircraft component; sending a test signal to the brake system controller; receiving, from the brake system controller, a feedback signal to the test signal; and determining an appropriateness of the feedback signal.

Abstract: A method, system, and computer program product for integrated circuit wafer and die testing. The method commences by selecting areas of interest accessible from a backside of an integrated circuit where the areas of interest correspond to electronic devices (e.g., gates or transistors or vias or pads). Then, using a small-beam light source such as a laser, illuminating the areas of interest and collecting the reflected signal returned from illuminated areas of interest. A processor analyses the reflected signal to determine logic states and timing information of the electronic devices and compares the determined logic states and timing information to a pre-determined logic pattern to identify one or more errors as observed from the actual electronic devices. Specific points within an area of interest are determined from CAD layout data, and the pre-determined logic patterns can be retrieved from CAD simulation data.

Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

Abstract: A method for performing an integrated waveform analysis without the use of an external device is disclosed.

Abstract: In an integrated circuit, a first scan chain of flip-flops is loaded with data for testing data retention of the flip-flops and a memory is loaded with data for performing a retention test by a memory built-in self-test (MBIST) wrapper circuit. A portion of the system is placed in a low-power state for a predetermined period of time before data is read from the memory and retention of data by the memory while in the low-power state is determined.

Abstract: A method for easily tracing the execution of an application in a computer system having a plurality of computing nodes interconnected by high speed data links is disclosed. While executing the application on one or more of the computing nodes, trace data is collected into a separate temporary trace buffer coupled to each computing node. A trace transfer request event may be generated after collecting a portion of the trace data. The trace data is recorded on a designated recording and analysis computing node by transferring the trace data from each trace buffer to a recording buffer in the designated recording node in response to the transfer request by performing memory mapped write transfers initiated by each computing node that has collected trace data. The address of the recording buffer is memory mapped into an address space of each computing node that has collected trace data.

Abstract: An example test system includes a bus interface to connect to a bus of a computer system; and test instruments to perform one or more test operations on a UUT, where the test instruments connect to the bus interface to enable communication between the computer system and the test instruments via the bus interface. At least one test instrument includes: ports to which the UUT is connectable, with each of the ports interfacing to a corresponding peripheral bus supported by the at least one test instrument; circuits to connect the bus interface to the peripheral buses, with each circuit being configured to convert between a bus interface protocol run on the bus interface and a peripheral bus protocol run on a peripheral bus; and a switch to identify a target circuit of the circuits, with the switch to direct communications between the computer system and the target circuit.

Abstract: A conventional power supply device has a problem in miniaturization. A power supply device generates a prediction value of an error signal from first and second error signals, and controls an output voltage so that the prediction value lies between first and second threshold values. The first error signal is obtained by converting an error voltage based on the difference between the output voltage and a reference voltage at a first timing. The second error signal is obtained by converting an error voltage based on the difference between the output voltage and the reference voltage at a second timing.

Abstract: In an embodiment, a test floor apparatus includes at least one conveyor, a vertical stack buffer, and an automated handling station. The vertical stack buffer is operable to hold a plurality of DUT (device under test) receptacles and operable to place a DUT receptacle on the at least one conveyor to enable a corresponding DUT to be inserted into the DUT receptacle. The automated handling station is operable to access the DUT receptacle from the at least one conveyor and is operable to open the DUT receptacle to position the corresponding DUT in a manner that couples the corresponding DUT to an electrical interface of the DUT receptacle and that encloses the corresponding DUT inside the DUT receptacle to facilitate testing of the corresponding DUT.

Abstract: In an embodiment, a method includes causing a test floor system to insert a DUT (device under test) into a DUT receptacle. This is performed in a manner that couples the DUT to an electrical interface of the DUT receptacle and that encloses the DUT inside the DUT receptacle to facilitate testing of the DUT. Also, the method includes causing the test floor system to transport the DUT receptacle that encloses the DUT to a tester of the test floor system and to insert the DUT receptacle into a DUT testing module of the tester. Further, the method includes causing the test floor system to determine identification information of the DUT. Furthermore, the method includes, based on the identification information, sending a test routine to the DUT testing module to perform on the DUT.