With Sampler Patents (Class 324/76.42)
  • Patent number: 9696355
    Abstract: A system and method to detect the fundamental frequency of an electric input signal using a feedback control loop including a phase error detector, a loop controller, and a digitally controlled oscillator. The frequency detector may detect the fundamental frequency of an electric input signal and produce an output signal representing the fundamental frequency of the electric input signal. The frequency detector may further include a filter that may be coupled to the frequency detector output signal in order to remove spurious tones or noise from the output signal.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 4, 2017
    Assignee: Analog Devices, Inc.
    Inventor: Gabriel Antonesei
  • Publication number: 20140159703
    Abstract: A system and method are presented for verifying the operating frequency of digital control circuitry. The system and method according to the present disclosure provide for a digitally controlled system, such as an electrosurgical system, to confirm or verify its operating frequency using a single external device, and software and/or firmware.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Applicant: Covidien LP
    Inventor: JAMES E. KRAPOHL
  • Patent number: 8664934
    Abstract: A system and method are presented for verifying the operating frequency of digital control circuitry. The system and method according to the present disclosure provide for a digitally controlled system, such as an electrosurgical system, to confirm or verify its operating frequency using a single external device, and software and/or firmware.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: March 4, 2014
    Assignee: Covidien LP
    Inventor: James E. Krapohl
  • Publication number: 20130285752
    Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.
    Type: Application
    Filed: June 28, 2013
    Publication date: October 31, 2013
    Inventors: Mahyar KARGAR, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
  • Publication number: 20130193952
    Abstract: A system and method are presented for verifying the operating frequency of digital control circuitry. The system and method according to the present disclosure provide for a digitally controlled system, such as an electrosurgical system, to confirm or verify its operating frequency using a single external device, and software and/or firmware.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 1, 2013
    Applicant: TYCO Healthcare Group LP
    Inventor: James E. Krapohl
  • Patent number: 8384372
    Abstract: A method and system is disclosed to detect and analyze an electric signal based on movement between an element and a counter electrode influenced by a nonlinear electric field produced by an electrical signal impressed between the element and counter electrode. Through detection of changes in the distance between the element and the counter electrode characteristics of the element and/or the environment of the element may be ascertained. Changes in the distance between the element and the counter electrode may be monitored based on changes in the value of capacitance between the element and counter electrode. The disclosed devices and methods may be employed to detect, for instance, presence of chemical/biological species in a sample or measure physical parameters of a sample such as pressure/acceleration, density, viscosity, magnetic force, temperature, and/or extremely small masses.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: February 26, 2013
    Assignee: Clemson University
    Inventors: Herbert W. Behlow, Jr., Bevan C. Elliott, Gayatri D. Keskar, Doyl E. Dickel, Malcolm J. Skove, Apparao M. Rao
  • Patent number: 8140283
    Abstract: Independent frequency measurement and tracking of a signal using a measurement interval where the frequency of the signal is measured and a sampling rate is calculated, and a settling interval where the frequency of the signal is not measured. The sampling rate is calculated to correspond with the frequency of the signal and updated only after the calculation of the sampling rate in the measuring interval. The signal may be a signal of an electric power system such as a voltage waveform or a current waveform. The frequency calculation may include determination of a rate of rotation of a positive-sequence phasor of the signal.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: March 20, 2012
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Gabriel Benmouyal, Angelo D'Aversa
  • Patent number: 8131490
    Abstract: A system and method for determining a received signal frequency by sampling the received signal at a rate less than twice a predefined nyquist rate. The system includes a distorting component configured to distort the received signal in a frequency dependent manner, at least one analog to digital converter configured to sample the received signal and the distorted signal at a rate less than twice a predefined nyquist rate, and a processing component configured to determine a frequency of the received signal based on the sampled received signal and the sampled distorted signal. The method includes distorting the received signal, sampling the received signal and the distorted signal at a rate less than twice a predefined nyquist rate, and determining a frequency of the received signal. In an embodiment, distorting includes at least one of distorting an amplitude or a group delay of the received signal.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: March 6, 2012
    Assignee: Honeywell International Inc.
    Inventors: Timothy P. Gibson, Jeffrey Kent Hunter
  • Patent number: 8111106
    Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: February 7, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Leo Montreuil, Larry Stephen McKinney, Jiening Ao, Joel Paul Jenkins
  • Patent number: 8040125
    Abstract: A device, in particular, a multi-channel oscilloscope, for the analysis of at least one measured signal transmitted via a multi-channel system, with several measurement channels. The device includes in each case a sampling device, a baseband mixing device, and a filter device, and an analysis device. The measured signal is supplied to the measurement channels and to the respective sampling devices for simultaneous sampling. The sampled measured signal is supplied to the baseband mixing devices connected downstream of the sampling devices for the mixing of the measured signal down into the baseband, to the filter devices connected downstream of the baseband mixing devices for the decimation of the sampled values of the measured signal in the baseband and to the analysis device connected to the filter devices for the analysis of the measured signal.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: October 18, 2011
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Thomas Kuhwald, Markus Freidhof
  • Patent number: 7652465
    Abstract: A “no dead time” data acquisition system for a measurement instrument receives a digitized signal representing an electrical signal being monitored and generates from the digitized signal a trigger signal using a fast digital trigger circuit, the trigger signal including all trigger events within the digitized signal. The digitized signal is compressed as desired and delayed by a first-in, first-out (FIFO) buffer for a period of time to assure a predetermined amount of data prior to a first trigger event in the trigger signal. The delayed digitized signal is delivered to a fast rasterizer or drawing engine upon the occurrence of the first trigger event to generate a waveform image. The waveform image is then provided to a display buffer for combination with prior waveforms and/or other graphic inputs from other drawing engines. The contents of the display buffer are provided to a display at a display update rate to show a composite of all waveform images representing the electrical signal.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: January 26, 2010
    Assignee: Tektronix, Inc.
    Inventors: Steven K. Sullivan, Terrance R. Beale, Kristie Veith
  • Patent number: 7598723
    Abstract: A method and system is disclosed that can be used to directly detect and analyze an electric signal electrostatically induced a semi-conductive or conductive element at resonance. Through detection of the changes in the characteristics of the signal from the element, the disclosed devices can detect, for instance, presence of chemical/biological species in a sample or measure physical parameters of a sample such as pressure/acceleration, magnetic force, temperature, and/or extremely small masses. The disclosed systems include one or more micro- or nano-sized elements. Through modulation of an electric charge on a counter-electrode that is located at a pre-determined distance from the element, a modulating charge can be induced upon the element. Resonance can be directly detected via electronic monitoring of the induced signal for the higher harmonics of the natural resonant frequency.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: October 6, 2009
    Inventors: Jay Gaillard, Razvan Marian Ciocan, Malcolm Skove, Apparao M. Rao
  • Patent number: 7355378
    Abstract: There is provided a method of source synchronous sampling, where a first clock signal of a first unit is synchronized to a second signal received from a second unit. The method includes determining a timing control signal on the base of the first clock signal and the second signal, generating an adjusted clock signal by adjusting the timing of the first clock signal corresponding to the timing control signal, and using the adjusted clock signal for sampling a signal received from the second unit. The second signal is a clock signal received from the second unit, the adjusted clock signal is used for sampling this clock signal itself, and a corresponding sampled clock signal is supervised to show proper clock functionality.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: April 8, 2008
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Markus Rottacker, Bernd Laquai, Klaus-Peter Behrens
  • Patent number: 7132766
    Abstract: A technique for controlling a switching circuit, such as a relay, includes one or more sensing circuits that generate signals based upon the presence of an actuating object and upon a randomly applied strobe signal. The generated signals are sampled and are used as a basis for determining the state of an output signal. The sensing circuit may generate the signals based upon capacitive coupling with the actuating object. The randomization of the sampling provides enhanced immunity to periodic or cyclic noise. Where more than one sensing circuit is included, the output of the circuits may be considered together for determining the state of the output signal, such as based upon predetermined ranges of signal levels. Signals of the sensing circuit may be sampled in the absence of the strobe to provide an indication of the relative noise level. If the noise level is determined to be elevated, the output signal may not change states.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: November 7, 2006
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Michael Lee Gasperi, David Dale Brandt, Thong T. Nguyen
  • Patent number: 7043383
    Abstract: A frequency error detection apparatus and method based on histogram information of an input signal. The apparatus includes an A/D converter for and converting an analog signal into digital values; a zero crossing point detector for detecting sign changes of the digital values, and detecting zero crossing points; a period information detector for detecting period information which is the number of the digital values corresponding to a periodic signal; a histogram information calculator for counting the number of detections for the respective period information based on the period information, and calculating error-detection-target histogram information; and a frequency error calculator for detecting a difference between the error-detection-target histogram information and a reference histogram information, and calculating a frequency error value based on the difference. This can shorten time for frequency error detections and improve accuracy of the detected frequency error value.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: May 9, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-wook Lee, Jung-hyun Lee
  • Patent number: 7026804
    Abstract: A method and system for sampling an analog signal that minimizes perturbations caused by noise. In one embodiment, the sample and hold circuit includes a plurality of switches in series between the sampled source and a hold capacitor. A resistor is located in parallel with the first switch. The two switches are controlled so as to provide three signal paths between the hold capacitor and the sampled signal. The first signal path is a closed circuit between the charge capacitor and the sampled signal. This path occurs during a first phase of operation for the sample and hold circuit. During a second phase of operation, the first switch is opened which sends any current loss from the capacitor to path through the resistor. The high resistance provided by the resistor minimizes this current loss. The third signal path occurs when the second switch is opened which present an open circuit between the capacitor and the sampled signal.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: April 11, 2006
    Assignee: Zarlink Semiconductor (U.S.) Inc.
    Inventors: Andrew Michael Bottomley, Didier Serge Sagan
  • Patent number: 6922066
    Abstract: In a sampler for use in measuring a waveform of an electric signal, a measurement target current is given as the electric signal to a sampler chip 11 and is also used to produce a trigger current Itr for determining measurement timing on the sampler chip. A comparator 20 compares a sum of a feedback current, a current derived from the measurement target current, and the trigger current Itr with a threshold value to produce an SFQ pulse when the sum exceeds the threshold value. The SFQ pulse produced by the comparator is observed or counted for a predetermined duration to measure the waveform of the electric signal.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: July 26, 2005
    Assignees: NEC Corporation, International Superconductivity Technology Center
    Inventor: Mutsuo Hidaka
  • Patent number: 6839657
    Abstract: A method of and an arrangement for characterizing non-linear behavior of RF and microwave devices under test in a near matched environment. The method comprises the steps of exciting the device by an RF signal under different load conditions, measuring signal data at input and output ports of the device, verifying whether the measurement data meet predetermined quality criteria; calculating, from the measurement data, model parameters of a predetermined model for characterizing the non-linear behavior of the device, and verifying assumptions made in the characterization model by collecting additional measurement data and comparing same with data calculated from the model using the model parameters calculated. The load conditions are obtained by connecting to the output port of the device a matched load, an open, a short and a plurality of attenuators and delays.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: January 4, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Frans Verbeyst, Jan Verspecht
  • Publication number: 20040135571
    Abstract: The invention relates to a method and apparatus for suppressing interference in an electric signal, particularly for suppressing interference in an electrocardiogram (ECG) signal in connection with magnetic resonance imaging (MRI). In order to improve the accuracy of the suppression, the electric signal is first sampled at a high sampling frequency, whereby a first sequence of samples is obtained. Some of the samples in the first sequence of samples are then selected on the basis of predetermined criteria. The first sequence is then downsampled using the selected samples, whereby a second sequence of samples is obtained. The second sequence forms a digital presentation of the electric signal in which the interference is suppressed.
    Type: Application
    Filed: November 26, 2003
    Publication date: July 15, 2004
    Inventors: Kimmo Henrik Uutela, Tor Borje Rantala, Juha Petri Virtanen
  • Publication number: 20030234641
    Abstract: A method and system for sampling an analog signal that minimizes perturbations caused by noise. In one embodiment, the sample and hold circuit includes a plurality of switches in series between the sampled source and a hold capacitor. A resistor is located in parallel with the first switch. The two switches are controlled so as to provide three signal paths between the hold capacitor and the sampled signal. The first signal path is a closed circuit between the charge capacitor and the sampled signal. This path occurs during a first phase of operation for the sample and hold circuit. During a second phase of operation, the first switch is opened which sends any current loss from the capacitor to path through the resistor. The high resistance provided by the resistor minimizes this current loss. The third signal path occurs when the second switch is opened which present an open circuit between the capacitor and the sampled signal.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Inventors: Andrew Michael Bottomley, Didier Serge Sagan
  • Patent number: 6545454
    Abstract: A system tests analog and mixed signal IC devices using an FFT algorithm, supported by a non-iterative Fast Fourier Transform (FFT) coherency analysis algorithm to establish FFT sample-set coherency. A test signal is input into the IC device, and an output signal from the IC device is analyzed using the FFT algorithm. The non-iterative FFT coherency analysis algorithm uses only one “given” value and two approximated values related to a test signal. Based on these given and approximated values, the correct set of all four values required for proper testing of the IC device is determined in a single pass, without the need for multiple iterations.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: April 8, 2003
    Assignee: Agere Systems, Inc.
    Inventor: Ronald D. Wagstaff
  • Patent number: 6541952
    Abstract: The present invention relates to a high speed sample and hold circuit having a plurality of sample and hold subcircuits coupled in parallel between an input and an output. The circuit also having a calibration sample and hold subcircuit coupled to the plurality of sample and hold subcircuits. The calibration circuit is operable to modify a timing for one or more of the plurality of sample and hold subcircuits to thereby reduce sampling mismatch between the plurality of sample and hold subcircuits. The present invention also having a method of reducing timing mismatch in a high speed, parallel coupled sample and hold circuit.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: April 1, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Krishnasawamy Nagaraj
  • Patent number: 6483287
    Abstract: A frequency synthesized signal generator outputs a frequency synthesized signal having a frequency equal to a repetition frequency of a signal under test by employing a reference signal. A phase comparator detects a phase difference between a phase of the frequency synthesized signal and a phase of the signal under test, and outputs a phase difference signal. A voltage control oscillator generates a reference signal phase-synchronized with the signal under test based on the phase difference signal output from the phase comparator, and feeds the reference signal back to the frequency synthesized signal generator. A sampling signal generator circuit generates a sampling signal applied to a sampling section by employing the reference signal output from the voltage control oscillator.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: November 19, 2002
    Assignee: Anritsu Corporation
    Inventors: Toshinobu Otsubo, Akihito Otani, Hiroto Watanabe
  • Patent number: 6344735
    Abstract: A power spectrum waveform is obtained by logarithmically amplifying a signal received by a frequency-sweep operation, detecting the amplified output of each frequency sweep, converting the detected output into a digital signal value in decibels, and converting this digital signal value into an antilogarithmic power value in watts for each display point within the width of the frequency sweep. Upon completion of the frequency sweep operation, the power values which have been converted into antilogarithmic values for each frequency sweep are averaged for each display point, the average power values are converted into logarithmic values, and the logarithmic values are displayed as a spectrum display.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: February 5, 2002
    Assignee: Advantest Corporation
    Inventors: Yuji Yoshino, Yoshiaki Miyamae
  • Patent number: 6329806
    Abstract: The present invention relates to a process for determining harmonic oscillations of a fundamental component of an electrical signal, wherein the signal is sampled with a sampling frequency corresponding to a multiple of the fundamental component's frequency. The sampled values of the signal are subjected, after analog-to-digital conversion, to a discrete Fourier transformation to determine the harmonic oscillations. The sampling is performed with a non-integer multiple of the frequency of the fundamental component and the discrete Fourier transformation is performed while the frequency resolution is increased over several periods of the fundamental component to determine the harmonic oscillations.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: December 11, 2001
    Assignee: Siemens AG
    Inventors: Thomas Reck, Tevfik Sezi
  • Patent number: 6246223
    Abstract: A method is provided for use on a parametric tester that allows the parametric tester to more effectively and precisely measure the output frequency of a periodic pulse signal generating means. The first step is to down convert the output frequency of the periodic pulse signal generating means to about 1 Hz. Then, the frequency-downconverted pulse train is sampled to thereby obtain a series of sampled signals In accordance with the magnitudes of the sampled signals, the sampled signals are registered to be at either a high-level state, an low-level state, or a intermediate-level state. Then, the integration time and the delay time involved in the sampling process are registered. The sampling process is continued until at least two sampled signals at the low-level state are registered. Based on these parameters, a delta transition time for the first intermediate-level state and a second delta transition time for the second intermediate-level state can be obtained.
    Type: Grant
    Filed: December 4, 1997
    Date of Patent: June 12, 2001
    Assignee: Winbond Electronics Corp.
    Inventor: Shi-Tron Lin