Abstract: Methods, systems, and apparatus for detecting and/or validating a detection of a state change by matching the shape of one or more of an cardiac data series, a heart rate variability data series, or at least a portion of a heart beat complex, derived from cardiac data, to an appropriate template.

Abstract: An apparatus is described that, according to an exemplary embodiment, has an RF oscillator for generating an RF oscillator signal at a first frequency and a frequency divider having a division ratio that is fixed during operation. The frequency divider is supplied with the RF oscillator signal and is configured to provide an oscillator signal at a second frequency. The apparatus further has a monitor circuit, to which the oscillator signal at the second frequency is supplied and which is configured to measure the second frequency and to provide at least one digital value that is dependent on the second frequency of the oscillator signal. The at least one digital value is provided on a test contact.

Abstract: A semiconductor device includes: a counting detection block suitable for generating a counting value of a clock signal transmitted through a first transmission path and a counting value of a target signal transmitted through a second transmission path during a counter enable section, and blocking the first transmission path and the second transmission path based on a comparison result obtained by comparing a predetermined code value with the counting value of the clock signal; and an output block suitable for outputting the counting value of the target signal corresponding to when the first and second transmission paths to a predetermined pad are blocked, based on a test mode signal.

Abstract: A multi purpose capacitive sensor suitable for indicating close proximity of a person to a surface along a large-size truck as well as along a medium-size painting or a pocket-size mobile phone is disclosed. The sensor comprises a voltage measuring device provided with a signal ground connected to a first pole of an oscillating voltage source that has a second pole connected to a signal input of the voltage measuring device. This input has a first capacitance to earth and a second capacitance to the signal ground. A third capacitance is exhibited to earth by the second pole of said voltage source. According to the invention, a prebias component is connected between the second pole of the voltage source and the signal input of the voltage measuring device.

Abstract: Disclosed are systems, apparatus, and methods for a self-contained timing and jitter measurement. In various embodiments, a device may include a first clock signal generator operative to provide a first clock signal to a transmitter of a transceiver, where the first clock signal operates at a first frequency. The device may further include a second clock signal generator operative to provide a second clock signal to a receiver of the transceiver, where the second clock signal operates at a second frequency, and where the receiver samples an output of the transmitter at a sampling rate determined by the second frequency. In some embodiments, the device may further include a logic circuit operative to receive an output signal from the receiver and further operative to determine an indication of jitter based on the received output signal.

Abstract: Apparatus and method for determining variation in a predetermined physical property of a circuit. The apparatus includes monitored circuitry for generating output pulses, and configured such that each output pulse has a pulse width which is indicative of the current value of the predetermined physical property. Circuitry is then configured to receive both the output pulses generated by the monitored circuitry and an oscillating timing reference signal. With reference to the oscillating timing reference signal, the counter circuitry produces for each output pulse an associated count value indicative of the pulse width of that output pulse. Circuitry then compares the associated count values for at least two output pulses, in order to produce a comparison result used to determine the variation in the predetermined physical property. This provides a flexible mechanism for monitoring variations in a physical property on the fly during use of a data processing circuit.

Abstract: A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width associated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control signal (CS) from a communication interface (CLK, CS, MOSI, MISO), wherein the communication interface (CLK, CS, MOSI, MISO) is designed to transfer information according to a communication protocol. The method further comprises a step of providing the frequency signal in the unit and comparing the frequency signal to a temporal sequence of signal levels of the cycle signal (CLK) received by the communication interface (CLK, CS, MOSI, MISO) in order to obtain a comparison result or controlling a counter by the control signal (CS) and the frequency signal in order to obtain a counter status.

Abstract: A frequency measuring apparatus includes: a counter section adapted to count a signal including a pulse signal for a predetermined time period, and output a binary count value corresponding to a frequency of the signal including the pulse signal; and a low pass filter section adapted to perform a filtering process on the count value, wherein the low pass filter section includes a first stage filter and a second stage filter, the first stage filter is a moving average filter to which the count value is input, and which provides a binary output with a high-frequency component reduced, and the second stage filter performs an average value calculation on the binary output to provide an output with the high-frequency component reduced.

Abstract: A frequency measurement device for measuring a frequency of a signal to be measured including a pulse signal, includes: a signal multiplier section that multiplies the signal to be measured by n (n is an integer) and outputs a multiplied signal; a counter section that counts the multiplied signal with a predetermined gate time and outputs a count value of the frequency of the signal to be measured at a predetermined period; and a low-pass filter that outputs a signal corresponding to the frequency of the signal to be measured based on the count value outputted at the predetermined period.

Abstract: A frequency measuring apparatus includes: a high-order digit calculation section adapted to measure an input signal and output a high-order digit value of a frequency value of the input signal; a low-order digit calculation section adapted to measure the input signal and output a low-order digit value of the frequency value of the input signal; and an adding section adapted to add the high-order digit value and the low-order digit value to each other to output the frequency value of the input signal.

Abstract: A measurement circuit and method for measuring a quiescent current of a circuit under test are provided. The measurement circuit comprises: a comparator having a first input terminal for receiving a reference voltage, a second input terminal coupled to the circuit under test, and an output terminal; a current source having a first terminal coupled to a first power supply voltage terminal, and a second terminal for providing a current to the circuit under test; a first switch having a first terminal coupled to the second terminal of the current source, a second terminal coupled to the circuit under test, and a control terminal coupled to the output terminal of the comparator; and a first counter having a first input terminal coupled to the output terminal of the comparator, a second input terminal for receiving a clock signal, and an output terminal for providing a first counter value associated with the quiescent current.

Abstract: The semiconductor integrated circuit includes a first oscillator, a second oscillator (PLL), a third oscillator (ring oscillator), a selector that switches, in turn, based on a clock of the third oscillator, and outputs a clock of the first oscillator or a clock of the second oscillator, and a determination circuit that counts up or counts down the clock output from the selector, based on the clock of the third oscillator, determines the correspondence of the clock output from the selector and the clock of the third oscillator, based on a result of the counting up or the counting down, and determines whether either of the clock output from the selector or the clock of the third oscillator occur an abnormal oscillation.

Abstract: An apparatus for detecting the state of a storage device prevents occurrence of a leakage current. A low-level detection unit is provided for each of blocks of a battery pack. Control units are connected to the blocks of the battery pack by way of first switches and are started upon receipt of power supply. The control units and measurement units are connected to the blocks by way of second switches. The control units activate the second switches after being started as a result of activation of the first switches, to thus receive power supply, and commence measurement of block voltages by means of the measurement units. The high-level detection unit supplies a read signal and a synchronous signal to the low-level detection units by way of the first switches.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: A frequency detection mechanism for a clock generation unit on an integrated circuit includes a clock generation unit and a detection unit. The clock generation unit may generate an output clock signal at a predetermined frequency that corresponds to a frequency multiple of a reference clock signal provided as an input to the clock generation unit. The detection unit may determine whether the output clock signal is at the predetermined frequency. As such, the detection unit includes a first counter that may generate a first count value based upon the reference clock signal and a second counter that may generate a second count value based upon the output clock signal. The detection unit also includes comparison logic that may perform a plurality of multiplication operations on the first and second count values and generate a final result that indicates whether the output clock signal is at the predetermined frequency.

Abstract: The present invention offers an object proximity detector and object position detector. The variation of frequency of an oscillator is used to detect the proximity of an object to a sensor plate. The dependence of the sensitivity of the detector on the area of the sensor plate is reduced by conducting the sensor plate to two capacitors in series. The conducting wire of the sensor plate can be flexible without causing error detection. In the sensor element of the sensor oscillator, a resistor is connected at one terminal of the sensor plate to form a high pass filter. A resistor and a capacitor are added to the sensor oscillator to form a low pass filter. The high pass filter is used to reduce the low frequency electromagnetic interference. The low pass filter is used to reduce the high frequency electromagnetic interference.

Abstract: A test circuit determines whether a frequency of an output clock signal of a clock circuit is above an output threshold frequency. An input clock signal of the clock circuit is set to an elevated frequency that is higher than a specified frequency. A first counter counts the number of clock cycles of the input clock signal in a test interval to within a tolerance of the elevated frequency. The tolerance of the elevated frequency is higher than a tolerance of the specified frequency. A second counter counts the number of clock cycles of a feedback clock signal in the test interval. A comparator determines whether the frequency of the output clock signal is above the output threshold frequency based on the number of clock cycles of the input clock signal and the number of clock cycles of the feedback clock signal.

Abstract: The inverter according to the invention includes a control microcomputer including a protector circuit that stops the inverter when an anomaly is caused, a counter that counts the driving clock signals of the microcomputer from the instance at which the protector circuit starts working, and a conversion circuit that converts the clock signals counted by the counter to a numerical time expression in the time units and outputs the converted numerical time expression. The inverter according to the invention, manufacturable with low manufacturing costs and easy to operate, facilitates informing the installation manager of the period of time from the instance at which the inverter stopped due to an anomaly and such a cause, without impairing the time measurement precision.

Abstract: A system and method for enhanced frequency measurement. Embodiments provide an effective mechanism for reducing error associated with frequency measurements by amplifying the frequency of the signal fed to the frequency counter, thereby increasing the number of counts and reducing the error associated with each frequency measurement. Reductions in error enable the gate time for the frequency counter to be reduced, thereby increasing efficiency and cost-savings. After accessing the counts provided for the amplified frequency, the original frequency before amplification may be determined by reducing the amplified frequency (e.g., represented by the accessed counts) by the amount by which the original frequency was amplified. Embodiments provide an effective and efficient mechanism for automatically determining the amount of amplification for a given signal based upon its frequency and a maximum frequency of at least one of the frequency amplification component and the frequency counter.

Abstract: A broadband receiver exhibiting reduced interference to a frequency counter caused by a local oscillator.

Abstract: The present invention provides, a pulse generator, which is configured so as to generate pulses with a predetermined pulse width, comprises: multiple pulsers each of which is configured so as to adjust the pulse width of input pulses, and so as to output pulses with a predetermined pulse width thus adjusted, and which are connected in series; multiple signal acquisition units which are provided corresponding to the multiple pulsers, and each of which allows the pulses output from a corresponding one of the pulsers to be acquired at a position immediately after the output terminal of the corresponding pulser; a selection unit which allows the pulses acquired by one of the multiple signal acquisition units to be selected; a feedback path for inputting the pulses thus selected by the selection unit to the first pulser of the multiple pulsers; and a measurement unit for measuring the pulse width of the pulses thus selected by the selection unit based upon the loop cycle time of the pulse selected by the selection

Abstract: The present invention, generally speaking, provides a time shift angle demodulator that is of simple construction and has an extended linear range. Range extension is achieved by using the input signals directly, not simply post-processing the S-PFD outputs. In accordance with one embodiment of the invention, a method of measuring the phase or frequency of a periodic input signal uses a periodic reference signal and includes comparing the input signal to the reference signal to obtain a lead signal and a lag signal; changing the count of an up/down counter in dependence on the input signal, the reference signal, the lead signal and the lag signal; and using the lead signal, the lag signal and the count signal to produce a phase or frequency signal.

Abstract: A method and circuit for measuring a time interval between transitions of periodic signals at nodes of a circuit-under-test (CUT), the signals having a periodic clock frequency, the method includes periodically latching a digital value of a first periodic signal at edges of an undersampling clock, simultaneously periodically latching a digital value of a second periodic signal at edges of the undersampling clock, combining the latched digital values of the first and second periodic signals to produce a combined output whose duty cycle is proportional to the time interval between a median edge of latched digital values of the first periodic signal and a median edge of latched digital values of the second periodic signal; and counting the number of undersampling clock cycles in which the combined output is a predetermined logic value within a predetermined time interval whereat the number is proportional to a time interval between a transition of the first periodic signal and a transition of the second periodic

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: A built-in self-test apparatus for a digital-to-analog converter uses a differentiation unit for differentiating a digital-to-analog (DA) signal to obtain the differences between pulses of the analog signal. Next, the analog signal is converted into a digital signal in the light of a threshold voltage by a Schmitt trigger unit. Then, the duty cycles of the digital signal are calculated by a duty cycle retriever, and transmitted into a signature analyzer to calculate the differential non-linearity for error analysis. For processing a high-speed DA signal, the circuit disposed before the differentiation unit may use a test pattern unit, a sample-and-hold circuit and a logic circuit to lower the speed of the DA signal.

Abstract: A circuit for detecting whether an intermittent clock waveform signal of 50 MHz is received or not includes an offset receiver, a charge pump, a capacitor and a hysteresis comparator. A circuit for detecting whether a random data waveform signal of 500 MHz is received or not includes an offset-less receiver, a transition counter, a delay circuit and an AND circuit. An OR circuit outputs as a signal detection signal a signal indicating the OR operation result of respective outputs of the hysteresis comparator and the AND circuit.

Abstract: A method of correcting a real-time clock of an electronic apparatus, notably a mobile telephone, in which the real-time clock operates with a first clock generator which generates a real-time clock while the electronic apparatus operates with a second clock generator which generates a system clock, which method includes the following steps: determining the actual frequency of the real-time clock, determining the ratio Vclock/standard of the actual frequency of the real-time clock to the reference frequency of a standard clock, determining the deviation time of the real-time clock per second from the difference (1?Vclock/standard), determining, on the basis of the deviation time per second, a time difference dt within which the real-time clock is to be corrected by a correction time difference ?t, correcting the real time by ?t after expiration of dt.

Abstract: A circuit and related method for distributing events in an event stream (i.e., an electronic signal having a plurality of rising edge transitions and falling edge transitions). The circuit distributes the events in a primary event stream across multiple secondary event streams in such a way that the event rate in each of the secondary event streams is lower than the event rate in the primary event stream, but the relative timing of the events in the primary event stream is maintained in each of the secondary event streams. The secondary event streams can then be provided to respective timestamp circuits, which record the times at which events occur in the secondary event streams. Since the relative timing of the events in the primary event stream is maintained in each of the secondary event streams, the multiple timestamp circuits collectively record the times at which events occur in the primary event stream. The circuit and related method can be used when debugging/testing semiconductor devices.

Abstract: A time difference signal having a pulse width corresponding to the time difference between an output of a resonant pressure sensor and a reference clock is prepared. The pulse width of the time difference signal is expanded by a given magnification. Based on a count value obtained by counting the reference clock during the expanded pulse width and a count value obtained by counting the reference clock during one cycle of the output of the resonant pressure sensor or a period which is integer times as long as the one cycle, the output frequency of the resonant pressure sensor is obtained. It is possible to obtain the fast processing and the high resolution without increasing the frequency of the reference clock.

Abstract: The present invention, generally speaking, provides a time shift angle demodulator that is of simple construction and has an extended linear range. Range extension is achieved by using the input signals directly, not simply post-processing the S-PFD outputs. In accordance with one embodiment of the invention, a method of measuring the phase or frequency of a periodic input signal uses a periodic reference signal and includes comparing the input signal to the reference signal to obtain a lead signal and a lag signal; changing the count of an up/down counter in dependence on the input signal, the reference signal, the lead signal and the lag signal; and using the lead signal, the lag signal and the count signal to produce a phase or frequency signal.

Abstract: A frequency measurement circuit measures a frequency of an input signal. The frequency measurement circuit includes a frequency measurement unit for counting a reference clock during a counting period having a predetermined number of waves of the input signal. The frequency measurement unit counts the reference clock by using a lighter amount of weighting to each count at a starting time and an ending time of the counting period than the amount of weighting at the other times of the counting period.

Abstract: The invention provides a semiconductor device capable of appropriately debugging any fluctuation in element characteristic even when the element characteristic fluctuates exceeding a value estimated at the designing stage. This semiconductor device includes a process monitor circuit that monitors any fluctuation in process and outputs a monitor signal M representing a result of monitoring, in addition to circuit blocks that perform respectively required functions. And a timing control circuit that controls timing of an input signal inputted to a predetermined circuit element forming the circuit blocks based on the monitor signal M from the process monitor circuit is provided in the circuit blocks.

Abstract: A method and apparatus that uses the difference between two nodal voltages, such as a temperature-independent voltage and a temperature-dependent voltage, to determine the actual temperature at a point on an integrated circuit is provided. Further, a method and apparatus that converts a difference between nodal voltages in an integrated circuit from an analog to a digital quantity on the integrated circuit such that the difference in voltage may be used by an on-chip digital system is provided. Further, a method and apparatus for quantifying a difference in voltage between a first node and a second node of a temperature sensor is provided.

Abstract: A frequency change measuring device includes frequency divider for frequency dividing a measuring signal to produce frequency-divided signals, first counter for counting the frequency-divides signals to calculate frequency-division numbers, frequency division numbers transmitter for transmitting the frequency division numbers in synchronism with the frequency-divided signals, frequency division numbers receiver for receiving the frequency division numbers transmitted from the frequency division numbers transmitter, second counter for counting outputs of a reference clock generator synchronized with a timekeeping device that keeps the standard time, latch unit for latching a count of frequency outputs of the reference clock generator synchronous for generating reference clocks on the basis of signals synchronous with the frequency division numbers, and operations unit for determining a frequency change on the basis of the count and the frequency division numbers.

Abstract: A resonance-frequency measuring method is used for measuring a resonance frequency of an information recording/reproducing device reproducing information recorded on a medium by driving a mechanism unit. The resonance-frequency measuring method comprises the measuring step of applying sine-wave oscillations at different frequencies one by one to the mechanism unit, and counting the number of times information reproduced upon application of each of the sine-wave oscillations differs from information indicating an aimed location, and the resonance-frequency determining step of determining the resonance frequency according to the number of times counted in the measuring step.

Abstract: A system for improving the duty cycle output of a vehicle speed sensor circuit is disclosed. The vehicle speed sensor circuit can be configured, for example as a binary counter, to provide a particular number of pulses per distance of vehicle travel. An output of the vehicle speed sensor circuit is generally divided by placing varying values on particular load pins of an associated counter circuit, thereby providing a substantially improved duty cycle output from the vehicle speed sensor circuit, which is independent of an associated sensor duty cycle. The output of the vehicle speed sensor circuit can be divided utilizing a toggle flip-flop circuit integrated with the vehicle speed sensor circuit. The toggle flip-flop can be configured as an edge-triggered toggle flip-flop. The vehicle speed sensor can be utilized to sense rotating members present in a vehicle. The vehicle speed sensor thus provides a digital pulse output for every tooth that passes in front of the vehicle speed sensor.

Abstract: The present inventions overcomes a drawback that although it is necessary to increase frequency of a reference clock to perform the measurement of output frequency of a resonant pressure sensor speedily with high resolution, the increase of frequency gives rise to an increase of the power consumption and hence, the use of a two-wire differential pressure/pressure transmitter is difficult. A time difference signal having a pulse width corresponding to the time difference between an output of a resonant pressure sensor and a reference clock is prepared. The pulse width of the time difference signal is expanded by a given magnification. Based on a count value obtained by counting the reference clock during the expanded pulse width and a count value obtained by counting the reference clock during one cycle of the output of the resonant pressure sensor or a period which is integer times as long as the one cycle, the output frequency of the resonant pressure sensor is obtained.

Abstract: A frequency measurement circuit comprises a plurality of frequency measurement units 10, 20, K0 each of which counts a reference clock Cb during a counting period having a predetermined number of waves of an input signal Cin, each of the frequency measurement units counts the reference clock, with shifted counting periods, respectively. Moreover, an adder 14 is provided to add the counted numbers of the plurality of the frequency measurement units. By shift the counting periods, even if the phase of the input signal agrees with the phase of the reference clock at the time counting starts and at the time counting ends on a certain frequency measurement unit, there is scarcely any possibility of agreement of the phases on other frequency measurement units. Therefore, by utilization of the added number of counts, frequency can be measured with high accuracy. In addition, by making the counting periods being shifted with overlaping each other, extension of the measurement time is not required any longer.

Abstract: An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit or externally by one or more sources external to the integrated circuit. The embedded counter assembly utilizes a reference clock signal having known characteristics, and measures the frequency of an unknown clock signal based upon the reference clock signal. The embedded counter assembly is capable of measuring the frequency of internal clock signals that are otherwise inaccessible via external output pins.

Abstract: A frequency change measuring device includes frequency divider for frequency dividing a measuring signal to produce frequency-divided signals, first counter for counting the frequency-divided signals to calculate frequency-division numbers, frequency division numbers transmitter for transmitting the frequency division numbers in synchronism with the frequency-divided signals, frequency division numbers receiver for receiving the frequency division numbers transmitted from the frequency division numbers transmitter, second counter for counting outputs of a reference clock generator synchronized with a timekeeping device that keeps the standard time, latch unit for latching a count of frequency outputs of the reference clock generator synchronous for generating reference clocks on the basis of signals synchronous with the frequency division numbers, and operations unit for determining a frequency change on the basis of the count and the frequency division numbers.

Abstract: An on-chip built-in self test apparatus for a phase locked loop module that resides on an integrated circuit, receives a reference clock signal and provides an output clock signal. The apparatus generally comprises a finite state machine and testing circuitry. The finite state machine may be for (i) receiving the reference clock signal and for (ii) producing testing signals for the phase locked loop module. The testing circuitry may be coupled to the finite state machine for (i) receiving the output clock signal, (ii) determining whether the characteristics of the output clock signal meet a predetermined criteria for open and close loop phase locked loop module operation, and (iii) outputting a test signal that indicates proper phase locked loop module operation if the characteristics of the output clock signal meet the predetermined criteria.

Abstract: A novel and useful mechanism for measuring the time duration between asynchronous events. The mechanism utilizes two metastability resolvers, one for detecting the rising edge of the input signal and one for detecting its falling edge. The input signal is typically assumed to have some known nominal clock rate, but its exact frequency and phase (timing of transitions) are not known. Each of the two metastability resolvers comprises two branches of cascaded flip flops, each clocked off the rising edge and falling edge of a fast clock. Each metastability resolver functions to output an edge event signal and a clock phase signal indicating which edge of the fast clock the rising (or falling) edge of the data signal was closer to. The edge event signals are used to start and stop a counter clocked off the fast clock. The clock phase is used to correct (i.e. compensate) the counter value depending on which half cycle of the fast clock the rising and falling edge of the data signal arrived in.

Abstract: The present invention, generally speaking, provides a time shift angle demodulator that is of simple construction and has an extended linear range. Range extension is achieved by using the input signals directly, not simply post-processing the S-PFD outputs. In accordance with one embodiment of the invention, a method of measuring the phase or frequency of a periodic input signal uses a periodic reference signal and includes comparing the input signal to the reference signal to obtain a lead signal and a lag signal; changing the count of an up/down counter in dependence on the input signal, the reference signal, the lead signal and the lag signal; and using the lead signal, the lag signal and the count signal to produce a phase or frequency signal.

Abstract: A counting apparatus having excellent fail-safe characteristics can be used in a rotation-stopped detection apparatus. As a first feature, timing of a high-frequency signal P2 is carried out by a counter 1 after completion of a counting of pulse signals P1. When the frequency of the timing output for the high-frequency signal is a predetermined value, a judgment signal, indicating that the counting is normal, is generated by a frequency discriminating circuit 30. As a second feature, a counter 100 is preset using a preset signal. Then, after verifying by an output from a self hold circuit 102 that the counter 100 has been reset, a counting output is generated from a self hold circuit 104. As a third feature, the counting apparatus is used as timer circuits 203, 300, 400, and the generation frequency of a rotation detection pulse signal IP based on a sensor signal, is obtained to thereby detect a rotation-stopped condition of a rotating body.

Abstract: A method is provided for use on a parametric tester that allows the parametric tester to more effectively and precisely measure the output frequency of a periodic pulse signal generating means. The first step is to down convert the output frequency of the periodic pulse signal generating means to about 1 Hz. Then, the frequency-downconverted pulse train is sampled to thereby obtain a series of sampled signals In accordance with the magnitudes of the sampled signals, the sampled signals are registered to be at either a high-level state, an low-level state, or a intermediate-level state. Then, the integration time and the delay time involved in the sampling process are registered. The sampling process is continued until at least two sampled signals at the low-level state are registered. Based on these parameters, a delta transition time for the first intermediate-level state and a second delta transition time for the second intermediate-level state can be obtained.